Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28837	1		T1	4		T12	152		T13	16
auto[1]	41	1		T28	4		T413	5		T416	1
auto[2]	43	1		T28	1		T72	4		T74	8
auto[3]	224	1		T24	1		T25	1		T159	2

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7290	1		T1	1		T12	38		T13	4
evic_idx[1]	7285	1		T1	1		T12	38		T13	4
evic_idx[2]	7284	1		T1	1		T12	38		T13	4
evic_idx[3]	7286	1		T1	1		T12	38		T13	4

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28106	1		T1	4		T12	152		T16	400
evic_op[2]	359	1		T13	16		T23	16		T24	1

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6972	1		T1	1		T12	38		T16	100
evic_idx[0]	evic_op[1]	auto[1]	7	1		T28	1		T413	2		T417	2
evic_idx[0]	evic_op[1]	auto[2]	2	1		T418	2		-	-		-	-
evic_idx[0]	evic_op[1]	auto[3]	45	1		T159	1		T413	4		T416	2
evic_idx[0]	evic_op[2]	auto[0]	71	1		T13	4		T23	4		T157	7
evic_idx[0]	evic_op[2]	auto[1]	3	1		T304	1		T419	1		T420	1
evic_idx[0]	evic_op[2]	auto[2]	3	1		T421	1		T422	1		T423	1
evic_idx[0]	evic_op[2]	auto[3]	17	1		T24	1		T222	1		T42	1
evic_idx[1]	evic_op[1]	auto[0]	6970	1		T1	1		T12	38		T16	100
evic_idx[1]	evic_op[1]	auto[1]	8	1		T28	1		T413	1		T418	2
evic_idx[1]	evic_op[1]	auto[2]	1	1		T418	1		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	44	1		T159	1		T413	2		T416	2
evic_idx[1]	evic_op[2]	auto[0]	73	1		T13	4		T23	4		T157	7
evic_idx[1]	evic_op[2]	auto[1]	4	1		T424	1		T425	1		T426	1
evic_idx[1]	evic_op[2]	auto[2]	4	1		T427	2		T428	1		T423	1
evic_idx[1]	evic_op[2]	auto[3]	11	1		T25	1		T429	1		T430	1
evic_idx[2]	evic_op[1]	auto[0]	6970	1		T1	1		T12	38		T16	100
evic_idx[2]	evic_op[1]	auto[1]	7	1		T28	1		T413	1		T417	4
evic_idx[2]	evic_op[1]	auto[2]	2	1		T418	1		T431	1		-	-
evic_idx[2]	evic_op[1]	auto[3]	47	1		T413	2		T416	2		T161	3
evic_idx[2]	evic_op[2]	auto[0]	75	1		T13	4		T23	4		T157	7
evic_idx[2]	evic_op[2]	auto[1]	2	1		T304	1		T432	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	4	1		T427	2		T423	1		T433	1
evic_idx[2]	evic_op[2]	auto[3]	7	1		T434	1		T435	1		T436	1
evic_idx[3]	evic_op[1]	auto[0]	6974	1		T1	1		T12	38		T16	100
evic_idx[3]	evic_op[1]	auto[1]	8	1		T28	1		T413	1		T416	1
evic_idx[3]	evic_op[1]	auto[2]	2	1		T28	1		T418	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	47	1		T413	2		T416	3		T437	5
evic_idx[3]	evic_op[2]	auto[0]	72	1		T13	4		T23	4		T157	7
evic_idx[3]	evic_op[2]	auto[1]	2	1		T304	1		T438	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	5	1		T439	1		T428	1		T421	1
evic_idx[3]	evic_op[2]	auto[3]	6	1		T211	1		T440	1		T441	1