Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	54396	1		T38	16094		T336	2325		T337	15339
rd_lvl[2]	46102	1		T38	12194		T336	976		T338	2603
rd_lvl[3]	15256	1		T339	3974		T336	377		T340	916
rd_lvl[4]	29967	1		T37	751		T341	2121		T339	3741
rd_lvl[5]	11708	1		T37	187		T341	34		T336	225
rd_lvl[6]	11476	1		T37	3		T341	25		T336	12
rd_lvl[7]	5216	1		T37	85		T341	11		T336	182
rd_lvl[8]	13546	1		T37	2		T341	25		T336	182
rd_lvl[9]	6627	1		T336	277		T342	423		T343	1012
rd_lvl[10]	6367	1		T336	87		T342	1206		T344	20
rd_lvl[11]	4130	1		T345	57		T35	203		T336	115
rd_lvl[12]	6006	1		T37	83		T345	24		T346	1309
rd_lvl[13]	6045	1		T346	274		T347	1274		T340	136
rd_lvl[14]	5622	1		T35	134		T336	115		T36	287
rd_lvl[15]	2832	1		T33	559		T36	123		T348	50