Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	349136	1		T1	2		T2	1		T3	2
all_pins[1]	349136	1		T1	2		T2	1		T3	2
all_pins[2]	349136	1		T1	2		T2	1		T3	2
all_pins[3]	349136	1		T1	2		T2	1		T3	2
all_pins[4]	349136	1		T1	2		T2	1		T3	2
all_pins[5]	349136	1		T1	2		T2	1		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1757645	1		T1	12		T2	6		T3	12
values[0x1]	337171	1		T26	1523		T33	5178		T29	1505
transitions[0x0=>0x1]	298740	1		T26	1523		T33	3148		T29	1505
transitions[0x1=>0x0]	298725	1		T26	1523		T33	3148		T29	1505

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	348982	1		T1	2		T2	1		T3	2
all_pins[0]	values[0x1]	154	1		T257	3		T330	4		T331	1
all_pins[0]	transitions[0x0=>0x1]	85	1		T331	1		T335	2		T334	3
all_pins[0]	transitions[0x1=>0x0]	76	1		T257	1		T258	2		T330	3
all_pins[1]	values[0x0]	348991	1		T1	2		T2	1		T3	2
all_pins[1]	values[0x1]	145	1		T257	4		T258	2		T330	7
all_pins[1]	transitions[0x0=>0x1]	118	1		T257	4		T258	1		T330	6
all_pins[1]	transitions[0x1=>0x0]	3892	1		T33	1015		T36	184		T350	202
all_pins[2]	values[0x0]	345217	1		T1	2		T2	1		T3	2
all_pins[2]	values[0x1]	3919	1		T33	1015		T36	184		T350	202
all_pins[2]	transitions[0x0=>0x1]	47	1		T258	1		T330	1		T331	2
all_pins[2]	transitions[0x1=>0x0]	225352	1		T33	559		T37	1111		T38	28288
all_pins[3]	values[0x0]	119912	1		T1	2		T2	1		T3	2
all_pins[3]	values[0x1]	229224	1		T33	1574		T37	1111		T38	28288
all_pins[3]	transitions[0x0=>0x1]	194818	1		T33	559		T37	822		T38	25229
all_pins[3]	transitions[0x1=>0x0]	69266	1		T26	1523		T33	1574		T29	1505
all_pins[4]	values[0x0]	245464	1		T1	2		T2	1		T3	2
all_pins[4]	values[0x1]	103672	1		T26	1523		T33	2589		T29	1505
all_pins[4]	transitions[0x0=>0x1]	103653	1		T26	1523		T33	2589		T29	1505
all_pins[4]	transitions[0x1=>0x0]	38	1		T257	3		T330	1		T331	4
all_pins[5]	values[0x0]	349079	1		T1	2		T2	1		T3	2
all_pins[5]	values[0x1]	57	1		T257	3		T330	3		T331	4
all_pins[5]	transitions[0x0=>0x1]	19	1		T257	1		T330	2		T331	4
all_pins[5]	transitions[0x1=>0x0]	101	1		T257	1		T330	2		T331	1