Unified Coverage Report :: Group :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

Group : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

---

Summary for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	99	0	99	100.00

Variables for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_interval	99	0	99	100.00	100	1	1	0

Summary for Variable read_interval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	99	0	99	100.00

User Defined Bins for read_interval

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5648320	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
duration[1]	395401	1		T3	2		T13	1		T50	3778
duration[2]	771666	1		T1	10		T3	83		T12	40
duration[3]	118724	1		T3	1		T50	483		T39	702
duration[4]	1101895	1		T1	16		T3	134		T12	657
duration[5]	68968	1		T2	1		T3	3		T50	302
duration[6]	457434	1		T3	3		T12	986		T58	110
duration[7]	54605	1		T3	5		T50	145		T39	328
duration[8]	32408	1		T2	1		T12	2		T50	83
duration[9]	40124	1		T2	2		T3	5		T12	1
duration[10]	28660	1		T2	1		T3	2		T12	1
duration[11]	31428	1		T3	1		T12	1		T14	1
duration[12]	32233	1		T14	1		T50	30		T39	87
duration[13]	28244	1		T3	1		T12	1		T50	26
duration[14]	28677	1		T3	2		T50	21		T39	72
duration[15]	25249	1		T2	1		T3	2		T50	10
duration[16]	25214	1		T3	1		T12	1		T50	13
duration[17]	25702	1		T3	1		T50	26		T39	60
duration[18]	21962	1		T3	2		T58	1		T50	5
duration[19]	23188	1		T58	1		T14	5		T50	8
duration[20]	20787	1		T12	1		T58	5		T14	16
duration[21]	19619	1		T2	1		T12	1		T14	15
duration[22]	18832	1		T2	1		T3	1		T58	9
duration[23]	14766	1		T58	2		T63	16		T50	20
duration[24]	14484	1		T12	1		T58	7		T14	4
duration[25]	13013	1		T2	1		T58	1		T14	3
duration[26]	10847	1		T58	4		T63	18		T50	2
duration[27]	7519	1		T58	1		T14	2		T63	36
duration[28]	6445	1		T58	2		T63	6		T25	1
duration[29]	5118	1		T12	1		T13	1		T58	1
duration[30]	6323	1		T2	1		T13	1		T39	39
duration[31]	3611	1		T13	1		T39	6		T100	1
duration[32]	3314	1		T12	1		T13	1		T39	4
duration[33]	4270	1		T13	1		T50	15		T39	3
duration[34]	2695	1		T13	1		T39	1		T200	1
duration[35]	2421	1		T14	2		T39	21		T28	1
duration[36]	1426	1		T39	1		T28	1		T86	7
duration[37]	1598	1		T39	1		T28	2		T64	2
duration[38]	664	1		T1	1		T12	1		T50	5
duration[39]	2098	1		T50	4		T39	4		T28	2
duration[40]	1950	1		T58	1		T50	8		T39	1
duration[41]	2880	1		T28	3		T124	1		T46	2
duration[42]	1268	1		T28	1		T86	4		T45	1
duration[43]	2251	1		T39	1		T28	1		T86	1
duration[44]	207	1		T39	1		T28	1		T124	3
duration[45]	275	1		T28	2		T86	2		T45	2
duration[46]	1972	1		T28	2		T86	1		T56	1
duration[47]	182	1		T28	2		T56	1		T100	1
duration[48]	1092	1		T28	2		T56	1		T45	2
duration[49]	231	1		T28	1		T86	1		T45	5
duration[50]	163156	1		T28	2		T86	1		T100	1
duration[51]	213763	1		T28	2		T56	8		T100	14
duration[52]	23159	1		T12	1		T56	14		T100	3
duration[53]	154589	1		T28	1		T86	2		T56	7
duration[54]	10156	1		T86	1		T56	39		T100	74
duration[55]	7502	1		T39	1		T28	2		T56	78
duration[56]	1174	1		T86	1		T56	30		T100	5
duration[57]	5110	1		T56	33		T100	73		T124	22
duration[58]	3294	1		T86	1		T56	42		T100	6
duration[59]	1223	1		T86	3		T56	29		T100	1
duration[60]	2095	1		T25	1		T28	1		T56	17
duration[61]	2009	1		T56	22		T100	25		T124	5
duration[62]	1236	1		T56	19		T100	8		T124	3
duration[63]	2541	1		T64	1		T56	14		T100	30
duration[64]	2679	1		T56	16		T100	15		T124	1
duration[65]	1396	1		T86	1		T56	8		T100	13
duration[66]	3638	1		T28	1		T86	2		T56	4
duration[67]	1308	1		T56	5		T100	21		T124	5
duration[68]	1472	1		T60	1		T86	1		T56	8
duration[69]	912	1		T24	1		T56	4		T100	11
duration[70]	2535	1		T86	2		T56	4		T100	7
duration[71]	579	1		T56	2		T100	12		T45	3
duration[72]	4813	1		T100	5		T124	1		T45	2
duration[73]	383	1		T56	4		T100	7		T124	2
duration[74]	726	1		T100	6		T124	1		T45	2
duration[75]	248	1		T28	1		T56	1		T100	2
duration[76]	2929	1		T28	1		T56	2		T100	2
duration[77]	240	1		T28	1		T60	1		T56	1
duration[78]	528	1		T56	1		T100	2		T45	2
duration[79]	191	1		T100	1		T46	3		T214	4
duration[80]	1052	1		T56	1		T100	4		T46	3
duration[81]	133	1		T46	1		T245	2		T202	1
duration[82]	134	1		T60	1		T100	3		T124	2
duration[83]	126	1		T245	1		T202	1		T193	5
duration[84]	129	1		T100	1		T124	1		T159	1
duration[85]	104	1		T100	1		T46	1		T245	1
duration[86]	94	1		T60	1		T100	1		T46	1
duration[87]	64	1		T50	1		T46	1		T245	1
duration[88]	82	1		T12	1		T60	1		T46	1
duration[89]	75	1		T86	1		T45	1		T277	1
duration[90]	100	1		T25	1		T28	1		T100	2
duration[91]	66	1		T86	1		T100	1		T193	1
duration[92]	73	1		T58	1		T100	1		T239	1
duration[93]	108	1		T10	1		T64	1		T68	1
duration[94]	157	1		T24	1		T39	1		T60	1
duration[95]	64	1		T18	1		T28	1		T38	1
duration[96]	57	1		T124	1		T53	1		T442	1
duration[97]	69	1		T12	1		T100	1		T214	1
duration[98]	57	1		T46	1		T101	1		T201	1
duration[99]	66	1		T46	2		T211	1		T193	1