Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1		T257	7		T258	7		T330	7
all_values[1]	269	1		T257	7		T258	7		T330	7
all_values[2]	269	1		T257	7		T258	7		T330	7
all_values[3]	269	1		T257	7		T258	7		T330	7
all_values[4]	269	1		T257	7		T258	7		T330	7
all_values[5]	269	1		T257	7		T258	7		T330	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	918	1		T257	25		T258	27		T330	23
auto[1]	696	1		T257	17		T258	15		T330	19

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	558	1		T257	12		T258	17		T330	8
auto[1]	1056	1		T257	30		T258	25		T330	34

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	996	1		T257	24		T258	27		T330	25
auto[1]	618	1		T257	18		T258	15		T330	17

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	101	1		T257	2		T258	4		T330	4
all_values[0]	auto[0]	auto[1]	auto[1]	65	1		T257	3		T330	2		T331	1
all_values[0]	auto[1]	auto[0]	auto[1]	53	1		T258	3		T330	1		T331	2
all_values[0]	auto[1]	auto[1]	auto[1]	50	1		T257	2		T332	2		T333	1
all_values[1]	auto[0]	auto[0]	auto[1]	93	1		T257	1		T258	2		T331	3
all_values[1]	auto[0]	auto[1]	auto[1]	76	1		T257	3		T258	2		T330	5
all_values[1]	auto[1]	auto[0]	auto[1]	66	1		T258	2		T330	2		T331	3
all_values[1]	auto[1]	auto[1]	auto[1]	34	1		T257	3		T258	1		T334	1
all_values[2]	auto[0]	auto[0]	auto[0]	90	1		T257	4		T258	2		T330	1
all_values[2]	auto[0]	auto[1]	auto[0]	76	1		T258	3		T330	2		T331	3
all_values[2]	auto[1]	auto[0]	auto[1]	55	1		T257	3		T258	1		T330	3
all_values[2]	auto[1]	auto[1]	auto[1]	48	1		T258	1		T330	1		T331	3
all_values[3]	auto[0]	auto[0]	auto[0]	78	1		T257	3		T258	1		T330	3
all_values[3]	auto[0]	auto[1]	auto[0]	77	1		T257	1		T258	3		T335	4
all_values[3]	auto[1]	auto[0]	auto[1]	65	1		T257	2		T258	1		T330	3
all_values[3]	auto[1]	auto[1]	auto[1]	49	1		T257	1		T258	2		T330	1
all_values[4]	auto[0]	auto[0]	auto[0]	69	1		T257	3		T258	1		T330	1
all_values[4]	auto[0]	auto[0]	auto[1]	23	1		T257	1		T331	1		T335	1
all_values[4]	auto[0]	auto[1]	auto[0]	47	1		T257	1		T258	1		T331	2
all_values[4]	auto[0]	auto[1]	auto[1]	31	1		T258	2		T330	3		T335	3
all_values[4]	auto[1]	auto[0]	auto[1]	67	1		T257	2		T258	3		T330	2
all_values[4]	auto[1]	auto[1]	auto[1]	32	1		T330	1		T335	1		T332	2
all_values[5]	auto[0]	auto[0]	auto[0]	75	1		T258	6		T331	1		T333	1
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T257	1		T330	2		T332	1
all_values[5]	auto[0]	auto[1]	auto[0]	46	1		T330	1		T335	3		T334	2
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T257	1		T330	1		T331	2
all_values[5]	auto[1]	auto[0]	auto[1]	58	1		T257	3		T258	1		T330	1
all_values[5]	auto[1]	auto[1]	auto[1]	41	1		T257	2		T330	2		T331	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal