FLASH_CTRL Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	5.049m	45.816us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	55.260s	16.012us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.508m	24.980us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	33.570s	118.546us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.985m	14.424ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.462m	20.422ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	34.560s	100.323us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	33.570s	118.546us	20	20	100.00
		flash_ctrl_csr_aliasing	1.462m	20.422ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	25.090s	16.336us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	29.230s	142.943us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	56.530s	23.084us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.642m	235.601us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	29.908m	83.856ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.721m	320.284ms	20	20	100.00
		flash_ctrl_lcmgr_intg	29.180s	15.329us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.031m	374.086ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.958m	11.221ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.663m	2.536ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.200h	611.398ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.908m	57.149us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.048m	36.605us	38	40	95.00
		flash_ctrl_rw_evict_all_en	1.048m	29.368us	38	40	95.00
		flash_ctrl_re_evict	1.134m	151.054us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	13.615m	1.653ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	13.615m	1.653ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.162m	31.307ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	45.900s	1.062ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	26.699m	6.150ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	53.817m	29.221ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	21.823m	1.273ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	49.590m	1.136ms	2	5	40.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	29.200s	109.018us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.798m	1.477ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	45.860s	81.322us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.700s	22.991us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	51.734m	1.730ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.327m	2.921ms	50	50	100.00
		flash_ctrl_otp_reset	4.470m	35.748us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	29.908m	83.856ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.534m	26.655ms	38	40	95.00
		flash_ctrl_intr_wr	1.555m	3.247ms	9	10	90.00
		flash_ctrl_intr_rd_slow_flash	8.297m	240.038ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	5.615m	20.866ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.971m	1.463ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.309m	1.649ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	45.980s	135.703us	5	5	100.00
		flash_ctrl_ro_derr	3.446m	1.490ms	10	10	100.00
		flash_ctrl_rw_derr	4.823m	1.693ms	10	10	100.00
		flash_ctrl_derr_detect	5.830m	1.515ms	5	5	100.00
		flash_ctrl_integrity	10.441m	10.320ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	45.460s	187.916us	5	5	100.00
		flash_ctrl_ro_serr	3.078m	1.523ms	10	10	100.00
		flash_ctrl_rw_serr	5.578m	20.912ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.885m	1.542ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.847m	1.345ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.075m	2.385ms	19	20	95.00
		flash_ctrl_write_word_sweep	19.610s	115.328us	1	1	100.00
		flash_ctrl_read_word_sweep	28.170s	47.820us	1	1	100.00
		flash_ctrl_ro	2.496m	11.593ms	19	20	95.00
		flash_ctrl_rw	10.651m	4.001ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	58.130s	1.285ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.710m	94.653ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.656m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	29.650s	66.672us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	29.720s	20.099us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	34.970s	125.944us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	34.970s	125.944us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.508m	24.980us	5	5	100.00
		flash_ctrl_csr_rw	33.570s	118.546us	20	20	100.00
		flash_ctrl_csr_aliasing	1.462m	20.422ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	53.480s	62.652us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.508m	24.980us	5	5	100.00
		flash_ctrl_csr_rw	33.570s	118.546us	20	20	100.00
		flash_ctrl_csr_aliasing	1.462m	20.422ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	53.480s	62.652us	20	20	100.00
V2		TOTAL			1000	1013	98.72
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	33.150s	30.390us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	33.150s	30.390us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	33.150s	30.390us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	33.150s	30.390us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	32.260s	193.787us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
		flash_ctrl_tl_intg_err	21.787m	1.337ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	21.787m	1.337ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	21.787m	1.337ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	1.054m	117.706us	3	3	100.00
		flash_ctrl_wr_intg	30.960s	163.713us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	5.049m	45.816us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	4.470m	35.748us	80	80	100.00
		flash_ctrl_disable	45.860s	81.322us	50	50	100.00
		flash_ctrl_sec_info_access	2.104m	2.433ms	50	50	100.00
		flash_ctrl_connect	32.700s	22.991us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	29.700s	21.502us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	33.570s	118.546us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	33.150s	30.390us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	33.570s	118.546us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	33.150s	30.390us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	33.570s	118.546us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	33.150s	30.390us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	45.860s	81.322us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	1.054m	117.706us	3	3	100.00
		flash_ctrl_access_after_disable	29.240s	47.565us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	50.870s	63.837us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	45.860s	81.322us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	45.900s	1.062ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.651m	4.001ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	5.578m	20.912ms	10	10	100.00
		flash_ctrl_rw_derr	4.823m	1.693ms	10	10	100.00
		flash_ctrl_integrity	10.441m	10.320ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	29.908m	83.856ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	34.710s	696.213us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	29.710s	18.738us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	26.590s	47.292us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.998h	3.785ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.035m	88.513us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1267	1281	98.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.28	95.73	93.98	98.31	92.52	98.25	96.99	98.21

Failure Buckets

• Job timed out after * minutes has 6 failures:

  • Test flash_ctrl_error_prog_type has 3 failures.

    • 0.flash_ctrl_error_prog_type.36375629289394912861550329408191504873555148152549885745881630503303139941134
      Log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest/run.log

        Job timed out after 60 minutes
      

    • 2.flash_ctrl_error_prog_type.1153389174786231393833755924707570867898262318509783896029595816477089019446
      Log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest/run.log

        Job timed out after 60 minutes
      

    • ... and 1 more failures.

  • Test flash_ctrl_wo has 1 failures.

    • 4.flash_ctrl_wo.13597148482766977951752094802834859515539120842515989546882009333456825033151
      Log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_rw has 1 failures.

    • 4.flash_ctrl_rw.37983013373227771645209755442853949811828641030131060902895180015458475042329
      Log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log

        Job timed out after 60 minutes
      

  • Test flash_ctrl_intr_wr has 1 failures.

    • 7.flash_ctrl_intr_wr.92790661016409227668239072507546705879530147586521672413955055790731385763118
      Log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest/run.log

        Job timed out after 60 minutes
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:

  • Test flash_ctrl_rw_evict_all_en has 2 failures.

    • 16.flash_ctrl_rw_evict_all_en.102005908014955156094132388172064232210036224191385887087472497855279319229403
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 42335.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 42335.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 39.flash_ctrl_rw_evict_all_en.78509383666462264006105945158214449134609475956148075480915387634147513133571
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 21838.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 21838.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test flash_ctrl_rw_evict has 1 failures.

    • 27.flash_ctrl_rw_evict.107733759718853208275847925779493438451816583762207866645582097518552754964078
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 9041.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 9041.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:

  • Test flash_ctrl_phy_ack_consistency has 1 failures.

    • 4.flash_ctrl_phy_ack_consistency.52690404647835169125867910089727419633338792894404157152699095776426068710390
      Line 97, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log

        UVM_ERROR @ 19343.2 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x41)
        UVM_INFO @ 19343.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *f5ec6a9_876d7f56:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 10.flash_ctrl_intr_rd.98342742365775448501728669532128545499871890959352071861836428594607257029050
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 1322198.9 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    3: obs:exp    7f5ec6a9_876d7f56:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 1322198.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:

  • Test flash_ctrl_ro has 1 failures.

    • 13.flash_ctrl_ro.33963007370754078648290118967537420791802830660019714782892453674818417482196
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest/run.log

        UVM_ERROR @ 214801.1 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
        UVM_INFO @ 214801.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1] *: obs:exp *e6d1d_35c5a2a7:ffffffff_ffffffff mismatch!! has 1 failures:

  • Test flash_ctrl_intr_rd has 1 failures.

    • 28.flash_ctrl_intr_rd.90976196060969740511702729943510815408502979329221084092626481453245330121782
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest/run.log

        UVM_ERROR @ 3062522.7 ns: (flash_ctrl_otf_scoreboard.sv:375) [rdata_comp_bank1]    6: obs:exp    486e6d1d_35c5a2a7:ffffffff_ffffffff  mismatch!!
        UVM_INFO @ 3062522.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 1 failures:

  • Test flash_ctrl_rw_evict has 1 failures.

    • 28.flash_ctrl_rw_evict.92515046341892932028237431226861900866315268695149743900908380370521184789982
      Line 95, in log /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 87409.5 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
        UVM_INFO @ 87409.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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• 2024.08.26_02.22.49
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