Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	413780	1		T1	2		T2	2		T3	1
all_values[1]	413780	1		T1	2		T2	2		T3	1
all_values[2]	413780	1		T1	2		T2	2		T3	1
all_values[3]	413780	1		T1	2		T2	2		T3	1
all_values[4]	413780	1		T1	2		T2	2		T3	1
all_values[5]	413780	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	833850	1		T1	12		T2	12		T3	6
auto[1]	1648830	1		T26	5936		T35	20724		T27	5812

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1218393	1		T1	7		T2	7		T3	4
auto[1]	1264287	1		T1	5		T2	5		T3	2

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	413637	1		T1	2		T2	2		T3	1
all_values[0]	auto[1]	auto[1]	143	1		T255	7		T260	2		T319	2
all_values[1]	auto[0]	auto[1]	413635	1		T1	2		T2	2		T3	1
all_values[1]	auto[1]	auto[1]	145	1		T255	4		T260	1		T319	5
all_values[2]	auto[0]	auto[0]	1585	1		T1	2		T2	2		T3	1
all_values[2]	auto[0]	auto[1]	56	1		T319	1		T320	1		T321	1
all_values[2]	auto[1]	auto[0]	412071	1		T26	1484		T35	5181		T27	1453
all_values[2]	auto[1]	auto[1]	68	1		T255	3		T260	1		T319	3
all_values[3]	auto[0]	auto[0]	1583	1		T1	2		T2	2		T3	1
all_values[3]	auto[0]	auto[1]	53	1		T255	2		T260	1		T319	2
all_values[3]	auto[1]	auto[0]	86661	1		T26	1484		T35	1727		T27	1453
all_values[3]	auto[1]	auto[1]	325483	1		T35	3454		T36	3320		T32	556
all_values[4]	auto[0]	auto[0]	1117	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	530	1		T1	1		T2	1		T7	1
all_values[4]	auto[1]	auto[0]	301735	1		T26	1		T35	3454		T27	1
all_values[4]	auto[1]	auto[1]	110398	1		T26	1483		T35	1727		T27	1452
all_values[5]	auto[0]	auto[0]	1563	1		T1	2		T2	2		T3	1
all_values[5]	auto[0]	auto[1]	91	1		T37	1		T38	1		T39	1
all_values[5]	auto[1]	auto[0]	412078	1		T26	1484		T35	5181		T27	1453
all_values[5]	auto[1]	auto[1]	48	1		T255	3		T319	1		T320	1