Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.73 93.97 98.31 92.52 98.27 96.89 98.21


Total tests in report: 1273
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.16 59.16 85.16 85.16 64.69 64.69 49.34 49.34 19.73 19.73 82.40 82.40 80.58 80.58 32.24 32.24 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.2734705528
67.16 7.99 88.06 2.89 67.80 3.10 69.58 20.24 37.41 17.69 85.11 2.71 81.65 1.07 40.51 8.26 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.2261200072
72.30 5.14 89.36 1.31 69.82 2.02 73.39 3.81 63.27 25.85 86.56 1.45 82.23 0.58 41.46 0.96 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3061554653
77.37 5.08 92.40 3.03 75.62 5.81 75.63 2.25 63.27 0.00 92.28 5.72 83.11 0.87 59.31 17.85 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1614576874
79.81 2.44 92.86 0.46 81.76 6.13 83.22 7.58 63.27 0.00 93.13 0.85 83.40 0.29 61.04 1.73 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.4096664767
82.11 2.30 93.47 0.61 82.13 0.37 87.18 3.97 73.47 10.20 93.83 0.70 83.50 0.10 61.16 0.12 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.1304587010
84.24 2.14 93.55 0.08 82.43 0.30 87.38 0.19 73.47 0.00 93.98 0.15 83.69 0.19 75.22 14.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2830094214
86.35 2.10 93.55 0.00 82.90 0.47 87.38 0.00 73.47 0.00 93.98 0.00 91.94 8.25 81.23 6.01 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3698435577
88.20 1.85 93.73 0.18 87.49 4.59 87.38 0.00 76.19 2.72 94.60 0.62 92.52 0.58 85.48 4.25 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3025196058
89.72 1.52 93.90 0.18 88.30 0.81 91.36 3.98 77.55 1.36 95.35 0.75 95.83 3.30 85.76 0.28 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3426125814
90.35 0.63 94.00 0.10 88.59 0.30 92.64 1.28 78.91 1.36 95.60 0.26 95.83 0.00 86.90 1.14 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.1031649439
90.97 0.62 94.14 0.14 89.04 0.45 92.64 0.00 82.31 3.40 95.73 0.13 96.02 0.19 86.90 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.2567463512
91.55 0.58 95.11 0.97 89.21 0.17 93.56 0.92 82.31 0.00 97.53 1.79 96.02 0.00 87.11 0.22 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.166078415
91.97 0.42 95.11 0.00 89.23 0.02 94.39 0.84 84.35 2.04 97.53 0.00 96.02 0.00 87.15 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.3928373917
92.37 0.40 95.27 0.15 90.01 0.78 94.39 0.00 84.35 0.00 97.53 0.00 96.02 0.00 89.00 1.85 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.399031639
92.67 0.30 95.36 0.10 90.54 0.52 95.58 1.19 84.35 0.00 97.53 0.00 96.02 0.00 89.30 0.31 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.464278764
92.89 0.22 95.36 0.00 90.54 0.01 95.58 0.00 84.35 0.00 97.53 0.00 96.02 0.00 90.84 1.54 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3716057363
93.11 0.22 95.43 0.07 90.69 0.14 95.65 0.06 84.35 0.00 97.70 0.17 96.02 0.00 91.92 1.08 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.520285668
93.32 0.21 95.44 0.01 90.72 0.03 95.71 0.06 85.71 1.36 97.74 0.04 96.02 0.00 91.92 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.395879986
93.53 0.20 95.44 0.00 90.73 0.01 95.71 0.00 87.07 1.36 97.76 0.02 96.02 0.00 91.95 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2062448798
93.73 0.20 95.45 0.01 90.78 0.06 95.74 0.03 87.07 0.00 97.78 0.02 96.02 0.00 93.25 1.29 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3984575387
93.92 0.19 95.45 0.00 90.78 0.00 95.74 0.00 88.44 1.36 97.78 0.00 96.02 0.00 93.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1867879836
94.11 0.19 95.46 0.01 90.86 0.08 96.29 0.55 89.12 0.68 97.80 0.02 96.02 0.00 93.25 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1522988587
94.29 0.18 95.46 0.00 90.99 0.13 96.63 0.34 89.80 0.68 97.87 0.06 96.02 0.00 93.28 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.4220387968
94.44 0.15 95.51 0.05 91.14 0.15 96.68 0.05 90.48 0.68 97.97 0.11 96.02 0.00 93.31 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.564068017
94.59 0.15 95.51 0.00 91.61 0.47 96.68 0.00 90.48 0.00 98.02 0.04 96.12 0.10 93.74 0.43 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.4259411572
94.73 0.14 95.51 0.00 91.61 0.00 96.68 0.00 90.48 0.00 98.02 0.00 96.21 0.10 94.64 0.89 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.400736912
94.86 0.12 95.51 0.00 91.61 0.00 96.87 0.19 91.16 0.68 98.02 0.00 96.21 0.00 94.64 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.830720143
94.98 0.12 95.61 0.10 91.72 0.10 97.32 0.45 91.16 0.00 98.02 0.00 96.21 0.00 94.85 0.22 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.2078040395
95.09 0.11 95.62 0.01 91.72 0.00 97.32 0.00 91.84 0.68 98.04 0.02 96.21 0.00 94.88 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.1691139937
95.19 0.10 95.62 0.00 91.72 0.00 97.35 0.03 92.52 0.68 98.04 0.00 96.21 0.00 94.88 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2950897779
95.27 0.08 95.62 0.00 91.84 0.12 97.35 0.00 92.52 0.00 98.04 0.00 96.50 0.29 95.04 0.15 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3038982464
95.35 0.07 95.65 0.03 92.09 0.25 97.59 0.24 92.52 0.00 98.04 0.00 96.50 0.00 95.04 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.55411257
95.40 0.05 95.65 0.00 92.09 0.00 97.59 0.00 92.52 0.00 98.04 0.00 96.50 0.00 95.41 0.37 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.239599299
95.44 0.05 95.65 0.00 92.37 0.29 97.59 0.00 92.52 0.00 98.04 0.00 96.50 0.00 95.44 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3811919896
95.49 0.04 95.65 0.00 92.40 0.03 97.78 0.19 92.52 0.00 98.06 0.02 96.50 0.00 95.50 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3123887596
95.53 0.04 95.65 0.00 92.40 0.00 97.78 0.00 92.52 0.00 98.06 0.00 96.80 0.29 95.50 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1337156986
95.57 0.04 95.65 0.00 92.53 0.13 97.85 0.06 92.52 0.00 98.06 0.00 96.80 0.00 95.59 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.2222966943
95.61 0.04 95.65 0.00 92.64 0.10 97.85 0.00 92.52 0.00 98.06 0.00 96.80 0.00 95.78 0.18 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.45687982
95.64 0.03 95.65 0.00 92.77 0.13 97.85 0.00 92.52 0.00 98.06 0.00 96.80 0.00 95.87 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.844842498
95.68 0.03 95.65 0.00 92.77 0.00 97.85 0.00 92.52 0.00 98.06 0.00 96.80 0.00 96.09 0.22 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.834220122
95.71 0.03 95.65 0.00 92.77 0.00 97.85 0.00 92.52 0.00 98.06 0.00 96.80 0.00 96.30 0.22 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2986375893
95.73 0.03 95.65 0.00 92.91 0.13 97.85 0.00 92.52 0.00 98.08 0.02 96.80 0.00 96.33 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.386803789
95.75 0.02 95.65 0.00 92.96 0.06 97.88 0.03 92.52 0.00 98.08 0.00 96.80 0.00 96.39 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2341678250
95.77 0.02 95.65 0.00 92.98 0.02 97.88 0.00 92.52 0.00 98.08 0.00 96.80 0.00 96.52 0.12 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2423290868
95.79 0.02 95.66 0.01 93.06 0.08 97.88 0.00 92.52 0.00 98.10 0.02 96.80 0.00 96.55 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.2514220781
95.81 0.02 95.66 0.00 93.07 0.01 97.91 0.03 92.52 0.00 98.10 0.00 96.80 0.00 96.64 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3136702511
95.83 0.02 95.66 0.00 93.09 0.02 97.91 0.00 92.52 0.00 98.12 0.02 96.80 0.00 96.73 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3348115682
95.85 0.02 95.68 0.03 93.11 0.02 97.91 0.00 92.52 0.00 98.21 0.09 96.80 0.00 96.73 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.3932268365
95.87 0.02 95.68 0.00 93.11 0.00 97.91 0.00 92.52 0.00 98.21 0.00 96.80 0.00 96.86 0.12 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.893558043
95.88 0.02 95.68 0.00 93.13 0.02 97.98 0.06 92.52 0.00 98.21 0.00 96.80 0.00 96.89 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3610985689
95.90 0.01 95.68 0.00 93.13 0.00 97.98 0.00 92.52 0.00 98.21 0.00 96.89 0.10 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3263463377
95.91 0.01 95.68 0.00 93.13 0.00 98.07 0.10 92.52 0.00 98.21 0.00 96.89 0.00 96.89 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.427752706
95.93 0.01 95.68 0.00 93.13 0.01 98.10 0.03 92.52 0.00 98.23 0.02 96.89 0.00 96.92 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1899204780
95.94 0.01 95.68 0.00 93.13 0.00 98.10 0.00 92.52 0.00 98.23 0.00 96.89 0.00 97.01 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.517553129
95.95 0.01 95.68 0.00 93.13 0.00 98.10 0.00 92.52 0.00 98.23 0.00 96.89 0.00 97.10 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.980349556
95.97 0.01 95.68 0.00 93.13 0.00 98.10 0.00 92.52 0.00 98.23 0.00 96.89 0.00 97.19 0.09 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.2940727111
95.98 0.01 95.73 0.04 93.13 0.00 98.12 0.02 92.52 0.00 98.23 0.00 96.89 0.00 97.23 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2145443836
95.99 0.01 95.73 0.00 93.20 0.07 98.12 0.00 92.52 0.00 98.25 0.02 96.89 0.00 97.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3965024607
96.00 0.01 95.73 0.00 93.26 0.06 98.12 0.00 92.52 0.00 98.25 0.00 96.89 0.00 97.26 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2385162847
96.02 0.01 95.73 0.00 93.32 0.06 98.12 0.00 92.52 0.00 98.25 0.00 96.89 0.00 97.29 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2379409940
96.03 0.01 95.73 0.00 93.38 0.07 98.14 0.02 92.52 0.00 98.25 0.00 96.89 0.00 97.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.649002100
96.04 0.01 95.73 0.00 93.38 0.00 98.19 0.05 92.52 0.00 98.25 0.00 96.89 0.00 97.32 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1885147341
96.05 0.01 95.73 0.00 93.39 0.01 98.25 0.06 92.52 0.00 98.25 0.00 96.89 0.00 97.32 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.3677061408
96.06 0.01 95.73 0.00 93.40 0.01 98.25 0.00 92.52 0.00 98.25 0.00 96.89 0.00 97.38 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.1825295816
96.07 0.01 95.73 0.00 93.41 0.01 98.25 0.00 92.52 0.00 98.27 0.02 96.89 0.00 97.41 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3424587397
96.08 0.01 95.73 0.00 93.41 0.00 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.47 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3835898422
96.09 0.01 95.73 0.00 93.41 0.00 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.53 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.3630034197
96.10 0.01 95.73 0.00 93.41 0.00 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.60 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.3000269678
96.10 0.01 95.73 0.00 93.41 0.00 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.66 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.3477487625
96.11 0.01 95.73 0.00 93.41 0.00 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.72 0.06 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.2409698452
96.12 0.01 95.73 0.00 93.44 0.03 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1723400753
96.13 0.01 95.73 0.00 93.50 0.06 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3734203158
96.14 0.01 95.73 0.00 93.54 0.05 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2182384485
96.14 0.01 95.73 0.00 93.59 0.05 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2571865653
96.15 0.01 95.73 0.00 93.64 0.05 98.25 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.75 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.2716221758
96.16 0.01 95.73 0.00 93.64 0.00 98.27 0.02 92.52 0.00 98.27 0.00 96.89 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.1203358065
96.16 0.01 95.73 0.00 93.65 0.01 98.27 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3864774394
96.17 0.01 95.73 0.00 93.69 0.04 98.27 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.81 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.708888649
96.17 0.01 95.73 0.00 93.69 0.00 98.30 0.03 92.52 0.00 98.27 0.00 96.89 0.00 97.81 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.777599515
96.18 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2357923111
96.18 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2078665818
96.19 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.3544167338
96.19 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.699117571
96.19 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.2409060342
96.20 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2572684252
96.20 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.3923338189
96.21 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.1580575990
96.21 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.2166580134
96.22 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.1143901935
96.22 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.15 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.1411968853
96.23 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.18 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.3621029685
96.23 0.01 95.73 0.00 93.69 0.00 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.03 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.2134302025
96.23 0.01 95.73 0.00 93.72 0.03 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3726661261
96.24 0.01 95.73 0.00 93.74 0.03 98.30 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1650364018
96.24 0.01 95.73 0.00 93.75 0.01 98.31 0.02 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2984285186
96.24 0.01 95.73 0.00 93.77 0.02 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3971241453
96.25 0.01 95.73 0.00 93.79 0.02 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3308935747
96.25 0.01 95.73 0.00 93.81 0.02 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.3709811594
96.25 0.01 95.73 0.00 93.83 0.02 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3342664614
96.25 0.01 95.73 0.00 93.85 0.02 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.4198094818
96.26 0.01 95.73 0.00 93.87 0.02 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3535425804
96.26 0.01 95.73 0.00 93.88 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3504536798
96.26 0.01 95.73 0.00 93.89 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.3358780340
96.26 0.01 95.73 0.00 93.90 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.3367985510
96.26 0.01 95.73 0.00 93.91 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.4283859966
96.26 0.01 95.73 0.00 93.92 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.4016777050
96.27 0.01 95.73 0.00 93.92 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.4229110201
96.27 0.01 95.73 0.00 93.93 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.3950812706
96.27 0.01 95.73 0.00 93.94 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.802527482
96.27 0.01 95.73 0.00 93.95 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1025600623
96.27 0.01 95.73 0.00 93.96 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.201647409
96.27 0.01 95.73 0.00 93.97 0.01 98.31 0.00 92.52 0.00 98.27 0.00 96.89 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3135480968

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.321384906
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2462251014
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4079675516
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2242317563
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2275040335
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.905525964
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3564747151
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1753614162
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2760833278
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1792838790
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2181052747
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3073329864
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1823146597
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1336186886
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1661541583
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2132618043
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2400662758
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1791165455
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3071057770
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.522491724
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2161945938
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3279065010
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2858804608
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1932633561
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.737179666
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2655635100
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3660334138
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1880928035
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2297959757
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.450900308
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.495223726
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.50503518
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1949185429
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1496290047
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2910820437
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3556848550
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.639878298
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.136746242
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2482195240
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.3587801054
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1851088424
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1336968754
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2390739563
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1872461487
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1152230368
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2707894017
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1420302663
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3034720460
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2384859348
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.956671034
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3229015925
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2645349247
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3734164146
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.87916
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.394562884
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2593007831
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2662017283
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2936179597
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1278910248
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2825077430
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1692650476
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3993467657
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.4222515949
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2528560326
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2839687269
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.24442401
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2176392397
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1285340070
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2906861826
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1630109192
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1324303838
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3397349981
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2944865450
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3966601079
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/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.672989782
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3786132412
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.4075788765
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3423187570
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.4261614176
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.181299392
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2135490089
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1257115800
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.3267834389
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3227740346
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.547686267
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.3545380586



Total test records in report: 1273
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1626821293 Sep 04 08:49:39 AM UTC 24 Sep 04 08:49:56 AM UTC 24 48282800 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.3034522227 Sep 04 08:49:39 AM UTC 24 Sep 04 08:49:57 AM UTC 24 73356600 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.1343046327 Sep 04 08:49:29 AM UTC 24 Sep 04 08:50:00 AM UTC 24 48868800 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.649002100 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:03 AM UTC 24 14630400 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.674122046 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:03 AM UTC 24 37389200 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.876433027 Sep 04 08:49:29 AM UTC 24 Sep 04 08:50:05 AM UTC 24 54144700 ps
T13 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.2734705528 Sep 04 08:49:29 AM UTC 24 Sep 04 08:50:05 AM UTC 24 4285603900 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.2621948233 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:07 AM UTC 24 29252300 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.2261200072 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:12 AM UTC 24 43724200 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.313547951 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:13 AM UTC 24 18680300 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.166078415 Sep 04 08:49:58 AM UTC 24 Sep 04 08:50:15 AM UTC 24 16820100 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.1348106428 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:16 AM UTC 24 66574100 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1885147341 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:16 AM UTC 24 45460200 ps
T15 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.3544167338 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:18 AM UTC 24 17244900 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.4096664767 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:21 AM UTC 24 253773500 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.396962435 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:22 AM UTC 24 137601800 ps
T14 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3308935747 Sep 04 08:50:01 AM UTC 24 Sep 04 08:50:24 AM UTC 24 65956900 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.4220387968 Sep 04 08:50:06 AM UTC 24 Sep 04 08:50:24 AM UTC 24 86832600 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1650364018 Sep 04 08:49:57 AM UTC 24 Sep 04 08:50:25 AM UTC 24 700608900 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.1086436495 Sep 04 08:49:39 AM UTC 24 Sep 04 08:50:25 AM UTC 24 50693000 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.3471652629 Sep 04 08:50:03 AM UTC 24 Sep 04 08:50:25 AM UTC 24 40752800 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3475765397 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:30 AM UTC 24 877161000 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.2673682014 Sep 04 08:50:06 AM UTC 24 Sep 04 08:50:30 AM UTC 24 22251700 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2735977065 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:33 AM UTC 24 1493032900 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2808021780 Sep 04 08:50:15 AM UTC 24 Sep 04 08:50:35 AM UTC 24 171250900 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3506183277 Sep 04 08:49:29 AM UTC 24 Sep 04 08:50:36 AM UTC 24 36031300 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.1031649439 Sep 04 08:49:40 AM UTC 24 Sep 04 08:50:44 AM UTC 24 4589877100 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.1401758245 Sep 04 08:49:39 AM UTC 24 Sep 04 08:50:45 AM UTC 24 326831100 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3458854788 Sep 04 08:50:19 AM UTC 24 Sep 04 08:50:52 AM UTC 24 55608800 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.2055424187 Sep 04 08:50:15 AM UTC 24 Sep 04 08:50:53 AM UTC 24 44462900 ps
T73 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.81432692 Sep 04 08:49:39 AM UTC 24 Sep 04 08:50:58 AM UTC 24 7126869300 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3549733800 Sep 04 08:50:20 AM UTC 24 Sep 04 08:51:14 AM UTC 24 32344500 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.4016777050 Sep 04 08:50:37 AM UTC 24 Sep 04 08:51:17 AM UTC 24 1308503800 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.1815028505 Sep 04 08:49:29 AM UTC 24 Sep 04 08:51:30 AM UTC 24 4072317000 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3061554653 Sep 04 08:49:39 AM UTC 24 Sep 04 08:51:34 AM UTC 24 672597800 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.464278764 Sep 04 08:50:24 AM UTC 24 Sep 04 08:51:46 AM UTC 24 3578896300 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2990185666 Sep 04 08:50:13 AM UTC 24 Sep 04 08:51:46 AM UTC 24 87262600 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1876723833 Sep 04 08:49:40 AM UTC 24 Sep 04 08:51:51 AM UTC 24 692993400 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.345608135 Sep 04 08:49:39 AM UTC 24 Sep 04 08:51:53 AM UTC 24 462512100 ps
T74 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.3709811594 Sep 04 08:49:29 AM UTC 24 Sep 04 08:52:03 AM UTC 24 1059424700 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3419335573 Sep 04 08:51:31 AM UTC 24 Sep 04 08:52:04 AM UTC 24 85052300 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.3928373917 Sep 04 08:49:29 AM UTC 24 Sep 04 08:52:06 AM UTC 24 71377400 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2620745761 Sep 04 08:49:39 AM UTC 24 Sep 04 08:52:09 AM UTC 24 2609676900 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.1387363815 Sep 04 08:50:55 AM UTC 24 Sep 04 08:52:12 AM UTC 24 20283690400 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.4202592180 Sep 04 08:50:59 AM UTC 24 Sep 04 08:52:32 AM UTC 24 3749433100 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.3025196058 Sep 04 08:49:39 AM UTC 24 Sep 04 08:52:42 AM UTC 24 1601396700 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1356999849 Sep 04 08:51:52 AM UTC 24 Sep 04 08:52:49 AM UTC 24 1326681700 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1890850311 Sep 04 08:52:06 AM UTC 24 Sep 04 08:52:49 AM UTC 24 60025400 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.4259411572 Sep 04 08:49:40 AM UTC 24 Sep 04 08:52:50 AM UTC 24 1795660700 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3473288656 Sep 04 08:50:08 AM UTC 24 Sep 04 08:52:50 AM UTC 24 10012868500 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2830094214 Sep 04 08:49:29 AM UTC 24 Sep 04 08:52:53 AM UTC 24 12186875700 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.1039966150 Sep 04 08:49:40 AM UTC 24 Sep 04 08:52:55 AM UTC 24 6667321500 ps
T138 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.2881443955 Sep 04 08:49:39 AM UTC 24 Sep 04 08:52:59 AM UTC 24 4850356200 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.2112303709 Sep 04 08:51:15 AM UTC 24 Sep 04 08:53:02 AM UTC 24 529234900 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.499523877 Sep 04 08:50:31 AM UTC 24 Sep 04 08:53:05 AM UTC 24 42235100 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.563456895 Sep 04 08:52:42 AM UTC 24 Sep 04 08:53:07 AM UTC 24 32277900 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.3213609064 Sep 04 08:51:06 AM UTC 24 Sep 04 08:53:23 AM UTC 24 6132473100 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.3682718694 Sep 04 08:52:11 AM UTC 24 Sep 04 08:53:24 AM UTC 24 1912138900 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.532667291 Sep 04 08:49:40 AM UTC 24 Sep 04 08:53:24 AM UTC 24 6618446000 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.2790742667 Sep 04 08:53:00 AM UTC 24 Sep 04 08:53:25 AM UTC 24 86542600 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3058885617 Sep 04 08:50:24 AM UTC 24 Sep 04 08:53:25 AM UTC 24 280382700 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.10473070 Sep 04 08:52:50 AM UTC 24 Sep 04 08:53:26 AM UTC 24 73075900 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.3218185779 Sep 04 08:52:51 AM UTC 24 Sep 04 08:53:28 AM UTC 24 45907700 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3726661261 Sep 04 08:49:40 AM UTC 24 Sep 04 08:53:31 AM UTC 24 39029063800 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.592199173 Sep 04 08:53:06 AM UTC 24 Sep 04 08:53:32 AM UTC 24 46383400 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.4283859966 Sep 04 08:53:08 AM UTC 24 Sep 04 08:53:34 AM UTC 24 40895000 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.533811551 Sep 04 08:49:29 AM UTC 24 Sep 04 08:53:36 AM UTC 24 39137300 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.2341678250 Sep 04 08:52:51 AM UTC 24 Sep 04 08:53:39 AM UTC 24 28936500 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.3568932810 Sep 04 08:50:22 AM UTC 24 Sep 04 08:53:39 AM UTC 24 125664100 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3322655516 Sep 04 08:51:47 AM UTC 24 Sep 04 08:53:41 AM UTC 24 6464027200 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3057880405 Sep 04 08:53:26 AM UTC 24 Sep 04 08:53:44 AM UTC 24 39141200 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.386803789 Sep 04 08:53:25 AM UTC 24 Sep 04 08:53:48 AM UTC 24 837662300 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1283033480 Sep 04 08:53:25 AM UTC 24 Sep 04 08:53:49 AM UTC 24 43652100 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.784858595 Sep 04 08:50:19 AM UTC 24 Sep 04 08:53:49 AM UTC 24 68155800 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3978327138 Sep 04 08:53:29 AM UTC 24 Sep 04 08:53:50 AM UTC 24 47647600 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.3069993682 Sep 04 08:53:25 AM UTC 24 Sep 04 08:53:51 AM UTC 24 23620800 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.4279025989 Sep 04 08:52:51 AM UTC 24 Sep 04 08:53:52 AM UTC 24 79574900 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3424587397 Sep 04 08:53:32 AM UTC 24 Sep 04 08:53:52 AM UTC 24 25401800 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2780559817 Sep 04 08:49:40 AM UTC 24 Sep 04 08:53:55 AM UTC 24 859888300 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1664174078 Sep 04 08:53:03 AM UTC 24 Sep 04 08:54:01 AM UTC 24 618162900 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.1516616678 Sep 04 08:50:16 AM UTC 24 Sep 04 08:54:04 AM UTC 24 68874500 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.1777869586 Sep 04 08:53:37 AM UTC 24 Sep 04 08:54:05 AM UTC 24 75678100 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.3634712997 Sep 04 08:51:35 AM UTC 24 Sep 04 08:54:06 AM UTC 24 2194752800 ps
T269 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2751653818 Sep 04 08:53:24 AM UTC 24 Sep 04 08:54:06 AM UTC 24 685995400 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.862425546 Sep 04 08:49:40 AM UTC 24 Sep 04 08:54:09 AM UTC 24 12220325900 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.48557389 Sep 04 08:53:34 AM UTC 24 Sep 04 08:54:14 AM UTC 24 27495700 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.11176927 Sep 04 08:52:54 AM UTC 24 Sep 04 08:54:19 AM UTC 24 3222928200 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.32221366 Sep 04 08:53:40 AM UTC 24 Sep 04 08:54:19 AM UTC 24 49204200 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.1798527731 Sep 04 08:53:45 AM UTC 24 Sep 04 08:54:29 AM UTC 24 79869200 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.1203358065 Sep 04 08:52:09 AM UTC 24 Sep 04 08:54:30 AM UTC 24 1314998400 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.3450836048 Sep 04 08:54:07 AM UTC 24 Sep 04 08:54:35 AM UTC 24 1296482100 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3342664614 Sep 04 08:52:08 AM UTC 24 Sep 04 08:54:38 AM UTC 24 1995798100 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3308421965 Sep 04 08:52:08 AM UTC 24 Sep 04 08:54:55 AM UTC 24 6457308500 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.2311050807 Sep 04 08:53:32 AM UTC 24 Sep 04 08:55:17 AM UTC 24 10034238100 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.4156847594 Sep 04 08:54:40 AM UTC 24 Sep 04 08:55:22 AM UTC 24 80131300 ps
T250 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.394526272 Sep 04 08:53:40 AM UTC 24 Sep 04 08:55:22 AM UTC 24 66002900 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.2094051933 Sep 04 08:53:50 AM UTC 24 Sep 04 08:55:24 AM UTC 24 6409317600 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.519531389 Sep 04 08:53:48 AM UTC 24 Sep 04 08:55:32 AM UTC 24 47008400 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.2622830124 Sep 04 08:51:47 AM UTC 24 Sep 04 08:55:33 AM UTC 24 4002715500 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.3311824361 Sep 04 08:49:29 AM UTC 24 Sep 04 08:55:39 AM UTC 24 3706650000 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.4229110201 Sep 04 08:52:08 AM UTC 24 Sep 04 08:55:46 AM UTC 24 6893283500 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.802527482 Sep 04 08:54:20 AM UTC 24 Sep 04 08:55:56 AM UTC 24 648286000 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.2352634752 Sep 04 08:53:49 AM UTC 24 Sep 04 08:56:00 AM UTC 24 1247312200 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2240165521 Sep 04 08:55:23 AM UTC 24 Sep 04 08:56:02 AM UTC 24 18882900 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.535392844 Sep 04 08:54:31 AM UTC 24 Sep 04 08:56:03 AM UTC 24 616360700 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.45687982 Sep 04 08:54:19 AM UTC 24 Sep 04 08:56:11 AM UTC 24 5392747800 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3847334189 Sep 04 08:52:33 AM UTC 24 Sep 04 08:56:12 AM UTC 24 69216792900 ps
T248 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3864774394 Sep 04 08:52:08 AM UTC 24 Sep 04 08:56:13 AM UTC 24 7825847300 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.2165229614 Sep 04 08:50:26 AM UTC 24 Sep 04 08:56:21 AM UTC 24 2950939300 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2955496142 Sep 04 08:55:23 AM UTC 24 Sep 04 08:56:28 AM UTC 24 6812156400 ps
T215 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.844842498 Sep 04 08:49:39 AM UTC 24 Sep 04 08:56:36 AM UTC 24 3738909300 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.4147564140 Sep 04 08:56:11 AM UTC 24 Sep 04 08:56:40 AM UTC 24 78100300 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.1199523818 Sep 04 08:53:56 AM UTC 24 Sep 04 08:56:55 AM UTC 24 51243800 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.83727359 Sep 04 08:55:18 AM UTC 24 Sep 04 08:56:57 AM UTC 24 661288900 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3833154942 Sep 04 08:56:29 AM UTC 24 Sep 04 08:57:11 AM UTC 24 12595500 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.63288133 Sep 04 08:56:13 AM UTC 24 Sep 04 08:57:14 AM UTC 24 28470200 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.1818074940 Sep 04 08:56:56 AM UTC 24 Sep 04 08:57:17 AM UTC 24 25107900 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.3117026660 Sep 04 08:56:14 AM UTC 24 Sep 04 08:57:18 AM UTC 24 43698000 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.1825295816 Sep 04 08:56:22 AM UTC 24 Sep 04 08:57:21 AM UTC 24 115672800 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3692015234 Sep 04 08:54:51 AM UTC 24 Sep 04 08:57:25 AM UTC 24 1240086300 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.3559876021 Sep 04 08:57:15 AM UTC 24 Sep 04 08:57:34 AM UTC 24 12221300 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.520285668 Sep 04 08:52:15 AM UTC 24 Sep 04 08:57:40 AM UTC 24 12080524600 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.962943015 Sep 04 08:55:25 AM UTC 24 Sep 04 08:57:44 AM UTC 24 1489199500 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.338226619 Sep 04 08:56:01 AM UTC 24 Sep 04 08:57:44 AM UTC 24 2276868300 ps
T249 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2182384485 Sep 04 08:57:12 AM UTC 24 Sep 04 08:57:44 AM UTC 24 45777100 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.3932268365 Sep 04 08:57:23 AM UTC 24 Sep 04 08:57:47 AM UTC 24 116968500 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.3678008934 Sep 04 08:52:55 AM UTC 24 Sep 04 08:57:49 AM UTC 24 84608700 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.3059348155 Sep 04 08:57:26 AM UTC 24 Sep 04 08:57:51 AM UTC 24 25032100 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.3188245841 Sep 04 08:56:42 AM UTC 24 Sep 04 08:57:54 AM UTC 24 5879284000 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.2058424459 Sep 04 08:57:18 AM UTC 24 Sep 04 08:57:55 AM UTC 24 696296200 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.3260260879 Sep 04 08:56:58 AM UTC 24 Sep 04 08:57:59 AM UTC 24 208518000 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.3918665829 Sep 04 08:57:35 AM UTC 24 Sep 04 08:58:02 AM UTC 24 20960300 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.3038982464 Sep 04 08:50:35 AM UTC 24 Sep 04 08:58:03 AM UTC 24 140335205300 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3044542478 Sep 04 08:57:45 AM UTC 24 Sep 04 08:58:07 AM UTC 24 15467800 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3348115682 Sep 04 08:57:45 AM UTC 24 Sep 04 08:58:15 AM UTC 24 16013700 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2853263044 Sep 04 08:57:17 AM UTC 24 Sep 04 08:58:17 AM UTC 24 1146750600 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.4085698446 Sep 04 08:57:50 AM UTC 24 Sep 04 08:58:19 AM UTC 24 95944300 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.1223712340 Sep 04 08:54:29 AM UTC 24 Sep 04 08:58:24 AM UTC 24 10642227400 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.2222966943 Sep 04 08:55:41 AM UTC 24 Sep 04 08:58:24 AM UTC 24 1139000400 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3466883338 Sep 04 08:57:48 AM UTC 24 Sep 04 08:58:32 AM UTC 24 28026200 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.791912203 Sep 04 08:55:32 AM UTC 24 Sep 04 08:58:43 AM UTC 24 3098635600 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.4141693107 Sep 04 08:49:29 AM UTC 24 Sep 04 08:58:45 AM UTC 24 12211587000 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.217314715 Sep 04 08:58:01 AM UTC 24 Sep 04 08:58:46 AM UTC 24 78937500 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.2866769684 Sep 04 08:57:55 AM UTC 24 Sep 04 08:58:52 AM UTC 24 50896600 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.4111883756 Sep 04 08:56:04 AM UTC 24 Sep 04 08:58:57 AM UTC 24 58646584800 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.2567463512 Sep 04 08:49:29 AM UTC 24 Sep 04 08:59:11 AM UTC 24 5612260000 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3429621785 Sep 04 08:54:56 AM UTC 24 Sep 04 08:59:12 AM UTC 24 4369371800 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.554924541 Sep 04 08:58:03 AM UTC 24 Sep 04 08:59:14 AM UTC 24 186479200 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.277225542 Sep 04 08:49:40 AM UTC 24 Sep 04 08:59:22 AM UTC 24 8248268100 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.1606742495 Sep 04 08:58:44 AM UTC 24 Sep 04 08:59:33 AM UTC 24 1150112200 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3123887596 Sep 04 08:57:45 AM UTC 24 Sep 04 08:59:35 AM UTC 24 10021521600 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.167594713 Sep 04 08:57:52 AM UTC 24 Sep 04 08:59:48 AM UTC 24 186350700 ps
T251 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.4155613624 Sep 04 08:50:24 AM UTC 24 Sep 04 08:59:52 AM UTC 24 80060600 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3655686098 Sep 04 08:56:03 AM UTC 24 Sep 04 08:59:52 AM UTC 24 6119815000 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.3222952722 Sep 04 08:55:57 AM UTC 24 Sep 04 09:00:01 AM UTC 24 1455757000 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.3030501807 Sep 04 08:55:34 AM UTC 24 Sep 04 09:00:02 AM UTC 24 1228636800 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.418243698 Sep 04 08:59:36 AM UTC 24 Sep 04 09:00:12 AM UTC 24 46941500 ps
T216 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.817593614 Sep 04 08:51:18 AM UTC 24 Sep 04 09:00:18 AM UTC 24 8843461200 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.2291516 Sep 04 08:58:16 AM UTC 24 Sep 04 09:00:25 AM UTC 24 1189554700 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.2197938535 Sep 04 09:00:06 AM UTC 24 Sep 04 09:00:35 AM UTC 24 225224500 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.2829129986 Sep 04 08:54:06 AM UTC 24 Sep 04 09:00:39 AM UTC 24 17581904700 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1865983191 Sep 04 08:53:50 AM UTC 24 Sep 04 09:00:49 AM UTC 24 725043900 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.1478941657 Sep 04 08:59:11 AM UTC 24 Sep 04 09:00:51 AM UTC 24 1937481000 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.1696999606 Sep 04 08:59:12 AM UTC 24 Sep 04 09:01:07 AM UTC 24 13681195000 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.3328626488 Sep 04 08:59:53 AM UTC 24 Sep 04 09:01:18 AM UTC 24 618642200 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2126922211 Sep 04 08:52:09 AM UTC 24 Sep 04 09:01:20 AM UTC 24 5984043200 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.4203443289 Sep 04 08:58:25 AM UTC 24 Sep 04 09:01:22 AM UTC 24 41643700 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2945853691 Sep 04 08:59:23 AM UTC 24 Sep 04 09:01:42 AM UTC 24 980911800 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1577286886 Sep 04 09:00:01 AM UTC 24 Sep 04 09:01:42 AM UTC 24 2750268100 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.2800777342 Sep 04 08:53:52 AM UTC 24 Sep 04 09:01:47 AM UTC 24 4542256400 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3416711662 Sep 04 08:59:15 AM UTC 24 Sep 04 09:01:48 AM UTC 24 3409813800 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.77244242 Sep 04 09:01:21 AM UTC 24 Sep 04 09:01:49 AM UTC 24 42517500 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.2563239344 Sep 04 08:58:04 AM UTC 24 Sep 04 09:01:53 AM UTC 24 1409192300 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.4087676389 Sep 04 09:01:23 AM UTC 24 Sep 04 09:02:07 AM UTC 24 30164900 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.1530045448 Sep 04 08:59:48 AM UTC 24 Sep 04 09:02:10 AM UTC 24 606891000 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.532028888 Sep 04 08:59:53 AM UTC 24 Sep 04 09:02:16 AM UTC 24 4633312400 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.3839639415 Sep 04 08:54:37 AM UTC 24 Sep 04 09:02:16 AM UTC 24 7379295100 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.4070656524 Sep 04 09:00:13 AM UTC 24 Sep 04 09:02:16 AM UTC 24 426777000 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.1411968853 Sep 04 09:01:47 AM UTC 24 Sep 04 09:02:26 AM UTC 24 12921500 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.4106627679 Sep 04 09:02:08 AM UTC 24 Sep 04 09:02:30 AM UTC 24 25441400 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.28257945 Sep 04 09:01:43 AM UTC 24 Sep 04 09:02:31 AM UTC 24 80590000 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2789796301 Sep 04 09:01:42 AM UTC 24 Sep 04 09:02:33 AM UTC 24 160421800 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.2514220781 Sep 04 09:02:17 AM UTC 24 Sep 04 09:02:39 AM UTC 24 45118300 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3965024607 Sep 04 09:02:17 AM UTC 24 Sep 04 09:02:39 AM UTC 24 17046900 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.2831622722 Sep 04 09:02:16 AM UTC 24 Sep 04 09:02:42 AM UTC 24 818080900 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.4061787200 Sep 04 09:02:28 AM UTC 24 Sep 04 09:02:53 AM UTC 24 98513800 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.3588800719 Sep 04 08:57:55 AM UTC 24 Sep 04 09:02:56 AM UTC 24 34702100 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.110703327 Sep 04 09:02:32 AM UTC 24 Sep 04 09:02:59 AM UTC 24 49419000 ps
T270 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3012916561 Sep 04 09:02:32 AM UTC 24 Sep 04 09:03:01 AM UTC 24 30877100 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.3381705748 Sep 04 09:00:53 AM UTC 24 Sep 04 09:03:02 AM UTC 24 17377877100 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2423290868 Sep 04 09:02:11 AM UTC 24 Sep 04 09:03:05 AM UTC 24 341590300 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.4206687913 Sep 04 08:55:47 AM UTC 24 Sep 04 09:03:09 AM UTC 24 6425203600 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.2078040395 Sep 04 09:02:40 AM UTC 24 Sep 04 09:03:11 AM UTC 24 82873300 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.3739140405 Sep 04 09:02:43 AM UTC 24 Sep 04 09:03:18 AM UTC 24 31804800 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.893558043 Sep 04 09:01:50 AM UTC 24 Sep 04 09:03:18 AM UTC 24 1991656900 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.4194979373 Sep 04 09:00:50 AM UTC 24 Sep 04 09:03:21 AM UTC 24 2200294900 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.3226980291 Sep 04 09:00:36 AM UTC 24 Sep 04 09:03:35 AM UTC 24 1484464800 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3373998957 Sep 04 09:02:53 AM UTC 24 Sep 04 09:03:41 AM UTC 24 25458400 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.3553204795 Sep 04 08:56:52 AM UTC 24 Sep 04 09:03:42 AM UTC 24 81419100 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.1304587010 Sep 04 08:50:27 AM UTC 24 Sep 04 09:03:45 AM UTC 24 180181237100 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1168073835 Sep 04 09:01:08 AM UTC 24 Sep 04 09:03:48 AM UTC 24 11644529800 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2373462141 Sep 04 08:58:17 AM UTC 24 Sep 04 09:03:54 AM UTC 24 6159781100 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.947959103 Sep 04 09:03:22 AM UTC 24 Sep 04 09:04:01 AM UTC 24 550303600 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1025600623 Sep 04 09:00:19 AM UTC 24 Sep 04 09:04:11 AM UTC 24 6588787500 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.2665162937 Sep 04 09:02:57 AM UTC 24 Sep 04 09:04:21 AM UTC 24 121347700 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.4187005368 Sep 04 09:01:19 AM UTC 24 Sep 04 09:04:28 AM UTC 24 31781836300 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.879583188 Sep 04 08:49:29 AM UTC 24 Sep 04 09:04:30 AM UTC 24 80141398400 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1409981821 Sep 04 09:00:26 AM UTC 24 Sep 04 09:04:36 AM UTC 24 8804458500 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2821256549 Sep 04 08:53:42 AM UTC 24 Sep 04 09:05:10 AM UTC 24 242076800 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3070265067 Sep 04 09:04:28 AM UTC 24 Sep 04 09:05:15 AM UTC 24 308034200 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.2472459892 Sep 04 09:03:03 AM UTC 24 Sep 04 09:05:18 AM UTC 24 44292579100 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1867879836 Sep 04 09:03:55 AM UTC 24 Sep 04 09:05:25 AM UTC 24 1895028100 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.1695756836 Sep 04 08:58:33 AM UTC 24 Sep 04 09:05:33 AM UTC 24 31838380000 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3469069586 Sep 04 09:03:49 AM UTC 24 Sep 04 09:05:40 AM UTC 24 2979924100 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1899204780 Sep 04 09:02:34 AM UTC 24 Sep 04 09:05:50 AM UTC 24 10011624200 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.475294198 Sep 04 09:05:19 AM UTC 24 Sep 04 09:06:07 AM UTC 24 32125400 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.3755157454 Sep 04 09:02:59 AM UTC 24 Sep 04 09:06:09 AM UTC 24 1575863100 ps
T280 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.903329812 Sep 04 09:08:17 AM UTC 24 Sep 04 09:08:40 AM UTC 24 15516000 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.708888649 Sep 04 09:04:12 AM UTC 24 Sep 04 09:06:10 AM UTC 24 2053539800 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.698667783 Sep 04 09:05:12 AM UTC 24 Sep 04 09:06:15 AM UTC 24 490178700 ps
T307 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.3095172310 Sep 04 09:02:40 AM UTC 24 Sep 04 09:06:17 AM UTC 24 71685700 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1294446208 Sep 04 09:04:30 AM UTC 24 Sep 04 09:06:27 AM UTC 24 2605340400 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.3241500863 Sep 04 09:03:12 AM UTC 24 Sep 04 09:06:27 AM UTC 24 151061300 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.3534241842 Sep 04 08:58:07 AM UTC 24 Sep 04 09:06:56 AM UTC 24 5463289800 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.3252131569 Sep 04 09:04:02 AM UTC 24 Sep 04 09:07:09 AM UTC 24 12944338000 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1126756086 Sep 04 09:06:11 AM UTC 24 Sep 04 09:07:10 AM UTC 24 3990076800 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2391599221 Sep 04 09:05:16 AM UTC 24 Sep 04 09:07:19 AM UTC 24 4809419600 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.1518604602 Sep 04 09:06:28 AM UTC 24 Sep 04 09:07:20 AM UTC 24 28212400 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2864087921 Sep 04 08:53:27 AM UTC 24 Sep 04 09:07:29 AM UTC 24 80585082200 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.3230851910 Sep 04 09:07:11 AM UTC 24 Sep 04 09:07:38 AM UTC 24 20398700 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2848441739 Sep 04 09:06:57 AM UTC 24 Sep 04 09:07:53 AM UTC 24 96764700 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2242064070 Sep 04 08:50:05 AM UTC 24 Sep 04 09:07:54 AM UTC 24 446864594500 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.2842448068 Sep 04 09:01:54 AM UTC 24 Sep 04 09:07:55 AM UTC 24 219558400 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.1638753266 Sep 04 09:07:38 AM UTC 24 Sep 04 09:08:08 AM UTC 24 23982400 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.2563280891 Sep 04 09:04:37 AM UTC 24 Sep 04 09:08:08 AM UTC 24 1346084100 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.3356664680 Sep 04 08:59:34 AM UTC 24 Sep 04 09:08:16 AM UTC 24 4576935200 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1345959973 Sep 04 09:02:48 AM UTC 24 Sep 04 09:08:16 AM UTC 24 810936700 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.2727986237 Sep 04 09:07:10 AM UTC 24 Sep 04 09:08:19 AM UTC 24 88703600 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2571865653 Sep 04 09:07:55 AM UTC 24 Sep 04 09:08:25 AM UTC 24 635872200 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.37071030 Sep 04 09:07:56 AM UTC 24 Sep 04 09:08:27 AM UTC 24 15624400 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.716670866 Sep 04 09:05:26 AM UTC 24 Sep 04 09:08:31 AM UTC 24 2687039200 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1723400753 Sep 04 09:08:10 AM UTC 24 Sep 04 09:08:35 AM UTC 24 52449800 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.1666414361 Sep 04 09:07:21 AM UTC 24 Sep 04 09:08:39 AM UTC 24 8761662900 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2682194097 Sep 04 09:08:10 AM UTC 24 Sep 04 09:08:41 AM UTC 24 15604600 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1074533461 Sep 04 09:07:54 AM UTC 24 Sep 04 09:08:43 AM UTC 24 1338806400 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.4037478355 Sep 04 09:03:19 AM UTC 24 Sep 04 09:08:44 AM UTC 24 27100631700 ps
T271 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.1195654398 Sep 04 09:08:17 AM UTC 24 Sep 04 09:08:44 AM UTC 24 20614300 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.99703664 Sep 04 09:08:26 AM UTC 24 Sep 04 09:08:53 AM UTC 24 34341800 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.3714063403 Sep 04 09:05:51 AM UTC 24 Sep 04 09:08:57 AM UTC 24 1007401000 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.1725839853 Sep 04 08:53:53 AM UTC 24 Sep 04 09:09:03 AM UTC 24 80134535400 ps
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