Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	243322	1		T2	14		T7	5		T11	10
auto[FlashEraseBank]	269101	1		T1	20		T7	3		T11	1

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	262047	1		T1	20		T7	2		T12	2
auto[FlashOpProgram]	230533	1		T2	14		T7	4		T11	11
auto[FlashOpErase]	15843	1		T7	2		T12	1		T15	1
auto[FlashOpInvalid]	4000	1		T73	200		T92	200		T147	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	262047	1		T1	20		T7	2		T12	2
op[FlashOpProgram]	230533	1		T2	14		T7	4		T11	11
op[FlashOpErase]	15843	1		T7	2		T12	1		T15	1
read_erase_read	553	1		T23	13		T74	2		T30	6
read_prog_read	787	1		T22	1		T20	3		T59	2

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	371985	1		T1	20		T2	14		T7	8
auto[FlashPartInfo]	136387	1		T11	10		T8	3		T9	1
auto[FlashPartInfo1]	804	1		T20	1		T38	2		T68	1
auto[FlashPartInfo2]	3247	1		T23	1		T24	2		T20	13

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	192528	1		T1	20		T7	2		T12	2
auto[FlashPartData]	auto[FlashOpProgram]	171949	1		T2	14		T7	4		T11	1
auto[FlashPartData]	auto[FlashOpErase]	3604	1		T7	2		T12	1		T23	10
auto[FlashPartData]	auto[FlashOpInvalid]	3904	1		T73	196		T92	200		T147	194
auto[FlashPartInfo]	auto[FlashOpRead]	67166	1		T22	6		T23	20		T24	7
auto[FlashPartInfo]	auto[FlashOpProgram]	56952	1		T11	10		T8	3		T9	1
auto[FlashPartInfo]	auto[FlashOpErase]	12189	1		T15	1		T23	9		T29	14
auto[FlashPartInfo]	auto[FlashOpInvalid]	80	1		T73	4		T147	4		T149	12
auto[FlashPartInfo1]	auto[FlashOpRead]	624	1		T20	1		T38	2		T68	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	166	1		T30	1		T133	1		T151	32
auto[FlashPartInfo1]	auto[FlashOpErase]	6	1		T30	1		T133	1		T134	1
auto[FlashPartInfo1]	auto[FlashOpInvalid]	8	1		T133	2		T152	2		T417	2
auto[FlashPartInfo2]	auto[FlashOpRead]	1729	1		T23	1		T24	2		T20	10
auto[FlashPartInfo2]	auto[FlashOpProgram]	1466	1		T20	3		T37	8		T38	3
auto[FlashPartInfo2]	auto[FlashOpErase]	44	1		T146	2		T147	1		T148	3
auto[FlashPartInfo2]	auto[FlashOpInvalid]	8	1		T147	2		T418	2		T152	2