Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	30956	1		T12	4		T59	12		T29	8
auto[1]	66	1		T23	6		T419	4		T167	9
auto[2]	58	1		T23	4		T148	3		T175	4
auto[3]	208	1		T22	1		T23	17		T25	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7828	1		T12	1		T23	6		T59	3
evic_idx[1]	7823	1		T12	1		T23	6		T59	3
evic_idx[2]	7817	1		T12	1		T23	7		T59	3
evic_idx[3]	7820	1		T12	1		T22	1		T23	8

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	30423	1		T12	4		T23	27		T29	4
evic_op[2]	322	1		T22	1		T59	12		T29	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7545	1		T12	1		T29	1		T73	100
evic_idx[0]	evic_op[1]	auto[1]	16	1		T23	1		T167	3		T420	1
evic_idx[0]	evic_op[1]	auto[2]	5	1		T148	1		T421	4		-	-
evic_idx[0]	evic_op[1]	auto[3]	45	1		T23	5		T146	1		T148	2
evic_idx[0]	evic_op[2]	auto[0]	63	1		T59	3		T29	1		T74	4
evic_idx[0]	evic_op[2]	auto[1]	2	1		T419	1		T422	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	5	1		T423	1		T424	1		T425	1
evic_idx[0]	evic_op[2]	auto[3]	11	1		T25	1		T426	1		T427	1
evic_idx[1]	evic_op[1]	auto[0]	7544	1		T12	1		T29	1		T73	100
evic_idx[1]	evic_op[1]	auto[1]	16	1		T23	2		T167	3		T420	1
evic_idx[1]	evic_op[1]	auto[2]	6	1		T23	1		T148	1		T167	1
evic_idx[1]	evic_op[1]	auto[3]	42	1		T23	3		T146	2		T148	2
evic_idx[1]	evic_op[2]	auto[0]	63	1		T59	3		T29	1		T74	4
evic_idx[1]	evic_op[2]	auto[1]	1	1		T419	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	4	1		T428	1		T423	1		T424	1
evic_idx[1]	evic_op[2]	auto[3]	11	1		T40	1		T429	1		T430	1
evic_idx[2]	evic_op[1]	auto[0]	7542	1		T12	1		T29	1		T73	100
evic_idx[2]	evic_op[1]	auto[1]	13	1		T23	2		T167	2		T420	1
evic_idx[2]	evic_op[1]	auto[2]	5	1		T148	1		T420	1		T421	3
evic_idx[2]	evic_op[1]	auto[3]	41	1		T23	5		T146	2		T148	2
evic_idx[2]	evic_op[2]	auto[0]	66	1		T59	3		T29	1		T74	4
evic_idx[2]	evic_op[2]	auto[1]	2	1		T419	1		T428	1		-	-
evic_idx[2]	evic_op[2]	auto[2]	2	1		T428	1		T431	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T392	1		T432	1		T433	1
evic_idx[3]	evic_op[1]	auto[0]	7544	1		T12	1		T29	1		T73	100
evic_idx[3]	evic_op[1]	auto[1]	14	1		T23	1		T167	1		T420	1
evic_idx[3]	evic_op[1]	auto[2]	9	1		T23	3		T167	1		T420	1
evic_idx[3]	evic_op[1]	auto[3]	36	1		T23	4		T146	3		T148	1
evic_idx[3]	evic_op[2]	auto[0]	62	1		T59	3		T29	1		T74	4
evic_idx[3]	evic_op[2]	auto[1]	2	1		T419	1		T434	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	6	1		T428	3		T423	1		T425	1
evic_idx[3]	evic_op[2]	auto[3]	12	1		T22	1		T427	1		T435	1