Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	55210	1		T327	2001		T328	1807		T329	15836
rd_lvl[2]	59046	1		T330	2474		T327	1075		T331	1451
rd_lvl[3]	17962	1		T330	2006		T327	508		T332	966
rd_lvl[4]	27652	1		T333	4954		T330	947		T327	507
rd_lvl[5]	15229	1		T333	950		T334	783		T330	1693
rd_lvl[6]	26758	1		T35	2761		T36	2673		T333	31
rd_lvl[7]	13696	1		T35	380		T36	647		T333	15
rd_lvl[8]	13471	1		T333	46		T335	1848		T336	1441
rd_lvl[9]	8523	1		T335	1333		T337	60		T327	329
rd_lvl[10]	7890	1		T34	307		T337	60		T338	1253
rd_lvl[11]	5757	1		T299	583		T33	59		T34	244
rd_lvl[12]	9129	1		T299	1059		T33	13		T339	1462
rd_lvl[13]	2027	1		T34	8		T340	518		T341	159
rd_lvl[14]	4863	1		T33	2		T340	1137		T342	1218
rd_lvl[15]	3750	1		T32	307		T343	144		T341	6