Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	413780	1		T1	2		T2	2		T3	1
all_pins[1]	413780	1		T1	2		T2	2		T3	1
all_pins[2]	413780	1		T1	2		T2	2		T3	1
all_pins[3]	413780	1		T1	2		T2	2		T3	1
all_pins[4]	413780	1		T1	2		T2	2		T3	1
all_pins[5]	413780	1		T1	2		T2	2		T3	1

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2076749	1		T1	12		T2	12		T3	6
values[0x1]	405931	1		T26	1483		T35	4868		T27	1452
transitions[0x0=>0x1]	363741	1		T26	1483		T35	4868		T27	1452
transitions[0x1=>0x0]	363724	1		T26	1483		T35	4868		T27	1452

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	413637	1		T1	2		T2	2		T3	1
all_pins[0]	values[0x1]	143	1		T255	7		T260	2		T319	2
all_pins[0]	transitions[0x0=>0x1]	67	1		T255	3		T260	1		T320	1
all_pins[0]	transitions[0x1=>0x0]	69	1		T319	3		T320	4		T325	4
all_pins[1]	values[0x0]	413635	1		T1	2		T2	2		T3	1
all_pins[1]	values[0x1]	145	1		T255	4		T260	1		T319	5
all_pins[1]	transitions[0x0=>0x1]	109	1		T255	2		T319	3		T320	3
all_pins[1]	transitions[0x1=>0x0]	5215	1		T32	236		T343	1099		T345	145
all_pins[2]	values[0x0]	408529	1		T1	2		T2	2		T3	1
all_pins[2]	values[0x1]	5251	1		T32	236		T343	1099		T345	145
all_pins[2]	transitions[0x0=>0x1]	50	1		T255	3		T260	1		T319	2
all_pins[2]	transitions[0x1=>0x0]	271441	1		T35	3141		T36	3320		T32	320
all_pins[3]	values[0x0]	137138	1		T1	2		T2	2		T3	1
all_pins[3]	values[0x1]	276642	1		T35	3141		T36	3320		T32	556
all_pins[3]	transitions[0x0=>0x1]	239807	1		T35	3141		T36	3320		T32	320
all_pins[3]	transitions[0x1=>0x0]	86867	1		T26	1483		T35	1727		T27	1452
all_pins[4]	values[0x0]	290078	1		T1	2		T2	2		T3	1
all_pins[4]	values[0x1]	123702	1		T26	1483		T35	1727		T27	1452
all_pins[4]	transitions[0x0=>0x1]	123684	1		T26	1483		T35	1727		T27	1452
all_pins[4]	transitions[0x1=>0x0]	30	1		T255	2		T319	1		T320	1
all_pins[5]	values[0x0]	413732	1		T1	2		T2	2		T3	1
all_pins[5]	values[0x1]	48	1		T255	3		T319	1		T320	1
all_pins[5]	transitions[0x0=>0x1]	24	1		T319	1		T325	2		T346	4
all_pins[5]	transitions[0x1=>0x0]	102	1		T255	4		T260	2		T319	1