Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	284	1		T255	7		T260	4		T319	7
all_values[1]	284	1		T255	7		T260	4		T319	7
all_values[2]	284	1		T255	7		T260	4		T319	7
all_values[3]	284	1		T255	7		T260	4		T319	7
all_values[4]	284	1		T255	7		T260	4		T319	7
all_values[5]	284	1		T255	7		T260	4		T319	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	953	1		T255	15		T260	12		T319	19
auto[1]	751	1		T255	27		T260	12		T319	23

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	534	1		T255	12		T260	11		T319	12
auto[1]	1170	1		T255	30		T260	13		T319	30

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	986	1		T255	23		T260	16		T319	21
auto[1]	718	1		T255	19		T260	8		T319	21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	105	1		T260	1		T319	4		T320	2
all_values[0]	auto[0]	auto[1]	auto[1]	73	1		T255	5		T260	2		T319	1
all_values[0]	auto[1]	auto[0]	auto[1]	74	1		T255	1		T319	2		T320	3
all_values[0]	auto[1]	auto[1]	auto[1]	32	1		T255	1		T260	1		T321	1
all_values[1]	auto[0]	auto[0]	auto[1]	91	1		T260	1		T319	2		T320	2
all_values[1]	auto[0]	auto[1]	auto[1]	72	1		T255	2		T260	1		T319	2
all_values[1]	auto[1]	auto[0]	auto[1]	68	1		T255	2		T260	1		T319	1
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T255	3		T260	1		T319	2
all_values[2]	auto[0]	auto[0]	auto[0]	83	1		T255	2		T260	2		T319	1
all_values[2]	auto[0]	auto[1]	auto[0]	77	1		T255	2		T260	1		T319	2
all_values[2]	auto[1]	auto[0]	auto[1]	64	1		T255	1		T319	1		T320	1
all_values[2]	auto[1]	auto[1]	auto[1]	60	1		T255	2		T260	1		T319	3
all_values[3]	auto[0]	auto[0]	auto[0]	83	1		T255	4		T260	2		T321	2
all_values[3]	auto[0]	auto[1]	auto[0]	78	1		T255	1		T319	2		T320	2
all_values[3]	auto[1]	auto[0]	auto[1]	68	1		T255	1		T260	1		T319	3
all_values[3]	auto[1]	auto[1]	auto[1]	55	1		T255	1		T260	1		T319	2
all_values[4]	auto[0]	auto[0]	auto[0]	56	1		T260	1		T319	3		T320	1
all_values[4]	auto[0]	auto[0]	auto[1]	26	1		T255	1		T320	1		T321	1
all_values[4]	auto[0]	auto[1]	auto[0]	37	1		T255	2		T260	1		T322	1
all_values[4]	auto[0]	auto[1]	auto[1]	39	1		T255	1		T320	1		T321	1
all_values[4]	auto[1]	auto[0]	auto[1]	69	1		T255	2		T319	1		T321	2
all_values[4]	auto[1]	auto[1]	auto[1]	57	1		T255	1		T260	2		T319	3
all_values[5]	auto[0]	auto[0]	auto[0]	67	1		T260	3		T319	1		T320	1
all_values[5]	auto[0]	auto[0]	auto[1]	27	1		T320	1		T323	1		T324	3
all_values[5]	auto[0]	auto[1]	auto[0]	53	1		T255	1		T260	1		T319	3
all_values[5]	auto[0]	auto[1]	auto[1]	19	1		T255	2		T325	1		T326	1
all_values[5]	auto[1]	auto[0]	auto[1]	72	1		T255	1		T320	3		T321	2
all_values[5]	auto[1]	auto[1]	auto[1]	46	1		T255	3		T319	3		T325	5

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal