Unified Coverage Report :: Module :: prim_generic_ram_1p

Module : prim_generic_ram_1p

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1p_0/rtl/prim_generic_ram_1p.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic	95.24	85.71				100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[0].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[1].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.24	85.71				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_info_types[2].u_info_mem

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T1 T2 T3 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T2 T10 T18 
66         1/1                    if (wmask[i]) begin
           Tests:       T2 T10 T18 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T2 T10 T18 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T1 T2 T3 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Module : prim_generic_ram_1p

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T10,T18
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_ram_1p

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	8424	8424	0	0
gen_wmask[0].MaskCheck_A	2147483647	175234826	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8424	8424	0	0
T1	8	8	0	0
T2	8	8	0	0
T3	8	8	0	0
T4	8	8	0	0
T10	8	8	0	0
T11	8	8	0	0
T16	8	8	0	0
T17	8	8	0	0
T18	8	8	0	0
T19	8	8	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	175234826	0	0
T4	7000	9	0	0
T10	3756	1950	0	0
T11	9216	0	0	0
T17	1864	0	0	0
T18	311206	9602	0	0
T19	3674	0	0	0
T26	795826	917504	0	0
T27	74134	0	0	0
T29	341014	3850	0	0
T30	190332	0	0	0
T31	0	1280	0	0
T32	0	655360	0	0
T33	389490	7950	0	0
T37	260065	0	0	0
T39	0	256	0	0
T58	0	2800	0	0
T63	100229	800	0	0
T64	95279	0	0	0
T69	3022	0	0	0
T71	0	750	0	0
T80	0	300	0	0
T83	0	131072	0	0
T108	0	131784	0	0
T124	3286	0	0	0
T137	0	524288	0	0
T138	0	12800	0	0
T139	0	786432	0	0
T140	0	720896	0	0
T141	0	65536	0	0
T142	0	458752	0	0
T143	51171	0	0	0
T144	1381	0	0	0
T145	2894	0	0	0
T146	84594	0	0	0
T147	64751	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T1 T2 T3 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T2 T18 T11 
66         1/1                    if (wmask[i]) begin
           Tests:       T2 T18 T11 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T2 T18 T11 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T1 T2 T3 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T2,T18,T11
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	60634004	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	60634004	0	0
T2	2364	506	0	0
T3	9069	0	0	0
T4	3500	0	0	0
T10	3756	0	0	0
T11	4608	300	0	0
T16	2282	0	0	0
T17	1864	0	0	0
T18	155603	16880	0	0
T19	1837	0	0	0
T25	0	67604	0	0
T29	170507	53950	0	0
T30	0	7012	0	0
T31	0	1024	0	0
T33	0	72050	0	0
T58	0	27600	0	0
T63	0	32700	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T1 T2 T3 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T10 T18 T4 
66         1/1                    if (wmask[i]) begin
           Tests:       T10 T18 T4 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T10 T18 T4 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T1 T2 T3 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T10,T18,T4
1	0	Covered	T1,T2,T3
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	15303332	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	15303332	0	0
T4	3500	9	0	0
T10	3756	1950	0	0
T11	4608	0	0	0
T17	1864	0	0	0
T18	155603	7378	0	0
T19	1837	0	0	0
T29	170507	3800	0	0
T30	95166	0	0	0
T31	0	1024	0	0
T33	194745	7950	0	0
T39	0	256	0	0
T58	0	2800	0	0
T63	0	800	0	0
T69	1511	0	0	0
T108	0	131784	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T18 T58 T45 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T26 T32 T80 
66         1/1                    if (wmask[i]) begin
           Tests:       T26 T32 T80 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T26 T32 T80 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T18 T58 T45 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T26,T32,T80
1	0	Covered	T18,T58,T45
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	6186284	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	6186284	0	0
T26	795826	458752	0	0
T27	74134	0	0	0
T32	0	655360	0	0
T37	260065	0	0	0
T64	95279	0	0	0
T80	0	300	0	0
T83	0	131072	0	0
T124	3286	0	0	0
T137	0	524288	0	0
T138	0	12800	0	0
T139	0	786432	0	0
T140	0	720896	0	0
T141	0	65536	0	0
T142	0	458752	0	0
T143	51171	0	0	0
T144	1381	0	0	0
T145	2894	0	0	0
T146	84594	0	0	0
T147	64751	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T18 T29 T63 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T18 T29 T31 
66         1/1                    if (wmask[i]) begin
           Tests:       T18 T29 T31 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T18 T29 T31 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T18 T29 T63 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T29,T31
1	0	Covered	T18,T29,T63
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	6515262	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	6515262	0	0
T4	3500	0	0	0
T11	4608	0	0	0
T12	53469	0	0	0
T18	155603	2224	0	0
T19	1837	0	0	0
T26	0	458752	0	0
T29	170507	50	0	0
T30	95166	0	0	0
T31	0	256	0	0
T33	194745	0	0	0
T37	0	18000	0	0
T50	0	1350	0	0
T54	0	600	0	0
T63	100229	0	0	0
T69	1511	0	0	0
T71	0	750	0	0
T72	0	200	0	0
T87	0	2730	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T3 T16 T17 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T18 T11 T29 
66         1/1                    if (wmask[i]) begin
           Tests:       T18 T11 T29 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T18 T11 T29 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T3 T16 T17 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T11,T29
1	0	Covered	T3,T16,T17
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	64706890	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	64706890	0	0
T4	3500	0	0	0
T5	0	50	0	0
T6	0	100	0	0
T11	4608	1700	0	0
T12	53469	0	0	0
T18	155603	9758	0	0
T19	1837	0	0	0
T29	170507	71050	0	0
T30	95166	9528	0	0
T31	0	512	0	0
T33	194745	58100	0	0
T58	0	18450	0	0
T63	100229	38500	0	0
T69	1511	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T18 T31 T87 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T18 T87 T26 
66         1/1                    if (wmask[i]) begin
           Tests:       T18 T87 T26 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T18 T87 T26 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T18 T31 T87 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T87,T26
1	0	Covered	T18,T31,T87
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	8010236	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	8010236	0	0
T4	3500	0	0	0
T11	4608	0	0	0
T12	53469	0	0	0
T18	155603	6166	0	0
T19	1837	0	0	0
T26	0	250	0	0
T29	170507	0	0	0
T30	95166	0	0	0
T32	0	863488	0	0
T33	194745	0	0	0
T51	0	50	0	0
T63	100229	0	0	0
T69	1511	0	0	0
T80	0	720896	0	0
T87	0	5104	0	0
T88	0	350	0	0
T148	0	768	0	0
T149	0	5254	0	0
T150	0	256	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T18 T87 T88 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T32 T80 T86 
66         1/1                    if (wmask[i]) begin
           Tests:       T32 T80 T86 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T32 T80 T86 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T18 T87 T88 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T32,T80,T86
1	0	Covered	T18,T87,T88
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	6854144	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	6854144	0	0
T32	190146	786432	0	0
T51	2019	0	0	0
T80	105732	720896	0	0
T86	0	327680	0	0
T125	3822	0	0	0
T139	0	917504	0	0
T151	0	327680	0	0
T152	0	720896	0	0
T153	0	12800	0	0
T154	0	65536	0	0
T155	0	524288	0	0
T156	0	12800	0	0
T157	1866	0	0	0
T158	1722	0	0	0
T159	55237	0	0	0
T160	128773	0	0	0
T161	177649	0	0	0
T162	60021	0	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		7	6	85.71
CONT_ASSIGN	42	1	0	0.00
CONT_ASSIGN	52	0	0
ALWAYS	63	6	6	100.00

41                        logic unused_cfg;
42         0/1     ==>    assign unused_cfg = ^cfg_i;
43                      
44                        // Width of internal write mask. Note wmask_i input into the module is always assumed
45                        // to be the full bit mask
46                        localparam int MaskWidth = Width / DataBitsPerMask;
47                      
48                        logic [Width-1:0]     mem [Depth];
49                        logic [MaskWidth-1:0] wmask;
50                      
51                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
52         unreachable      assign wmask[k] = &wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
53                      
54                          // Ensure that all mask bits within a group have the same value for a write
55                          `ASSERT(MaskCheck_A, req_i && write_i |->
56                              wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
57                              clk_i, '0)
58                        end
59                      
60                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
61                        // thrown when using $readmemh system task to backdoor load an image
62                        always @(posedge clk_i) begin
63         1/1              if (req_i) begin
           Tests:       T1 T2 T3 
64         1/1                if (write_i) begin
           Tests:       T18 T34 T31 
65         1/1                  for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T18 T34 T31 
66         1/1                    if (wmask[i]) begin
           Tests:       T18 T34 T31 
67         1/1                      mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T18 T34 T31 
68                                    wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                                end
                   ==>  MISSING_ELSE
70                              end
71                            end else begin
72         1/1                  rdata_o <= mem[addr_i];
           Tests:       T18 T34 T31 
73                            end
74                          end
                        MISSING_ELSE

---

Branch Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	63	3	3	100.00

63             if (req_i) begin
               -1-  
64               if (write_i) begin
                 -2-  
65                 for (int i=0; i < MaskWidth; i = i + 1) begin
                   ==>
66                   if (wmask[i]) begin
67                     mem[addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
68                       wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
69                   end
70                 end
71               end else begin
72                 rdata_o <= mem[addr_i];
                   ==>
73               end
74             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	1	Covered	T18,T34,T31
1	0	Covered	T18,T34,T31
0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataBitsPerMaskCheck_A	1053	1053	0	0
gen_wmask[0].MaskCheck_A	399654659	7024674	0	0

DataBitsPerMaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1053	1053	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0

gen_wmask[0].MaskCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	399654659	7024674	0	0
T4	3500	0	0	0
T11	4608	0	0	0
T12	53469	0	0	0
T18	155603	7428	0	0
T19	1837	0	0	0
T29	170507	0	0	0
T30	95166	0	0	0
T31	0	512	0	0
T32	0	786432	0	0
T33	194745	0	0	0
T34	0	50	0	0
T35	0	50	0	0
T63	100229	0	0	0
T69	1511	0	0	0
T80	0	720896	0	0
T87	0	3286	0	0
T88	0	200	0	0
T149	0	7178	0	0
T163	0	100	0	0