Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	316293	1		T1	2		T2	2		T3	2
all_values[1]	316293	1		T1	2		T2	2		T3	2
all_values[2]	316293	1		T1	2		T2	2		T3	2
all_values[3]	316293	1		T1	2		T2	2		T3	2
all_values[4]	316293	1		T1	2		T2	2		T3	2
all_values[5]	316293	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	638988	1		T1	12		T2	12		T3	12
auto[1]	1258770	1		T37	6836		T43	4576		T40	6396

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	930999	1		T1	7		T2	7		T3	7
auto[1]	966759	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	316133	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	160	1		T266	3		T274	6		T347	2
all_values[1]	auto[0]	auto[1]	316161	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	132	1		T266	5		T274	2		T347	3
all_values[2]	auto[0]	auto[0]	1605	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	59	1		T274	1		T348	1		T349	2
all_values[2]	auto[1]	auto[0]	314567	1		T37	1709		T43	1144		T40	1599
all_values[2]	auto[1]	auto[1]	62	1		T266	3		T274	2		T347	1
all_values[3]	auto[0]	auto[0]	1619	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	54	1		T266	2		T274	2		T349	1
all_values[3]	auto[1]	auto[0]	78198	1		T37	1709		T43	572		T40	1599
all_values[3]	auto[1]	auto[1]	236422	1		T43	572		T45	1550		T47	3418
all_values[4]	auto[0]	auto[0]	1156	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	517	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	217729	1		T37	1		T43	572		T40	1
all_values[4]	auto[1]	auto[1]	96891	1		T37	1708		T43	572		T40	1598
all_values[5]	auto[0]	auto[0]	1579	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	105	1		T30	1		T48	1		T104	1
all_values[5]	auto[1]	auto[0]	314546	1		T37	1709		T43	1144		T40	1599
all_values[5]	auto[1]	auto[1]	63	1		T266	1		T347	1		T351	4