Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.24 93.99 98.31 92.52 97.18 96.99 98.21


Total tests in report: 1266
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
58.89 58.89 85.14 85.14 65.36 65.36 49.00 49.00 19.73 19.73 82.41 82.41 81.19 81.19 29.41 29.41 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1744163721
67.36 8.47 88.21 3.07 73.38 8.02 67.28 18.28 39.46 19.73 85.19 2.78 82.69 1.51 35.30 5.89 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1918722090
72.94 5.59 91.24 3.03 79.03 5.66 69.15 1.86 39.46 0.00 90.85 5.66 91.16 8.47 49.72 14.43 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2767182243
77.27 4.32 91.77 0.53 80.70 1.67 69.15 0.00 48.98 9.52 91.37 0.51 91.91 0.75 67.02 17.29 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.2631326438
80.87 3.60 92.39 0.62 80.98 0.28 76.77 7.63 64.63 15.65 92.24 0.88 92.00 0.09 67.08 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.781465403
82.92 2.05 92.64 0.25 81.57 0.59 83.92 7.15 66.67 2.04 92.93 0.68 92.00 0.00 70.75 3.67 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.2017915021
84.44 1.52 92.82 0.18 82.43 0.87 87.94 4.02 68.03 1.36 93.68 0.75 95.20 3.20 71.02 0.28 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2603499035
85.94 1.50 93.33 0.51 82.97 0.53 91.26 3.32 73.47 5.44 94.27 0.60 95.20 0.00 71.12 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3380858598
87.30 1.36 93.33 0.01 83.44 0.48 91.65 0.39 73.47 0.00 94.34 0.06 95.67 0.47 79.22 8.11 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1093405107
88.52 1.22 93.52 0.19 84.03 0.59 92.02 0.37 79.59 6.12 94.62 0.28 95.86 0.19 80.02 0.80 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1263482587
89.65 1.13 93.62 0.10 87.62 3.59 92.92 0.90 80.95 1.36 95.00 0.38 96.14 0.28 81.32 1.29 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.699888762
90.24 0.59 93.80 0.18 88.39 0.77 95.29 2.38 80.95 0.00 95.09 0.09 96.14 0.00 82.03 0.71 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.2108579531
90.82 0.58 93.93 0.13 88.66 0.27 95.29 0.00 84.35 3.40 95.21 0.13 96.24 0.09 82.06 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.585204661
91.32 0.49 93.95 0.02 88.99 0.33 95.29 0.00 85.03 0.68 95.30 0.09 96.24 0.00 84.40 2.34 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2003446700
91.72 0.41 93.95 0.00 89.09 0.10 95.29 0.00 85.03 0.00 95.30 0.00 96.24 0.00 87.15 2.74 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1831323808
92.10 0.38 94.24 0.29 89.73 0.64 95.92 0.63 85.03 0.00 95.81 0.51 96.33 0.09 87.61 0.46 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1999852505
92.42 0.33 94.44 0.20 89.86 0.13 96.18 0.26 86.39 1.36 96.05 0.24 96.43 0.09 87.61 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.3062684202
92.71 0.29 94.44 0.00 89.86 0.00 96.18 0.00 88.44 2.04 96.05 0.00 96.43 0.00 87.61 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.2529458722
92.94 0.22 94.55 0.12 89.87 0.01 96.18 0.00 88.44 0.00 96.05 0.00 96.43 0.00 89.06 1.45 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.449959285
93.13 0.19 94.56 0.01 89.94 0.07 96.21 0.03 88.44 0.00 96.07 0.02 96.43 0.00 90.29 1.23 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.659190939
93.32 0.19 94.62 0.05 90.12 0.18 96.48 0.27 89.12 0.68 96.15 0.09 96.43 0.00 90.32 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1391671461
93.49 0.17 94.69 0.07 90.23 0.11 96.58 0.10 89.12 0.00 96.28 0.13 96.43 0.00 91.12 0.80 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.462035438
93.66 0.16 94.72 0.04 91.13 0.90 96.58 0.00 89.12 0.00 96.28 0.00 96.43 0.00 91.34 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1172362840
93.80 0.15 94.77 0.04 91.33 0.20 96.64 0.06 89.12 0.00 96.32 0.04 96.52 0.09 91.92 0.59 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2035449062
93.94 0.14 94.83 0.06 91.47 0.14 97.00 0.35 89.12 0.00 96.45 0.13 96.52 0.00 92.20 0.28 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.214028084
94.07 0.13 94.83 0.00 91.54 0.08 97.16 0.16 89.80 0.68 96.47 0.02 96.52 0.00 92.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.1570413762
94.20 0.12 94.85 0.02 91.57 0.03 97.22 0.06 90.48 0.68 96.54 0.06 96.52 0.00 92.20 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.674717991
94.32 0.12 94.95 0.10 91.68 0.10 97.67 0.45 90.48 0.00 96.54 0.00 96.52 0.00 92.39 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.3374806323
94.43 0.12 94.95 0.00 91.70 0.02 97.67 0.00 90.48 0.00 96.54 0.00 96.61 0.09 93.09 0.71 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2953173677
94.55 0.11 94.96 0.02 91.76 0.07 97.67 0.00 91.16 0.68 96.56 0.02 96.61 0.00 93.09 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.887446161
94.65 0.10 94.96 0.00 91.76 0.00 97.69 0.02 91.84 0.68 96.56 0.00 96.61 0.00 93.13 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1738784316
94.75 0.10 94.97 0.01 92.17 0.41 97.69 0.00 91.84 0.00 96.58 0.02 96.61 0.00 93.40 0.28 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1137151106
94.85 0.10 94.97 0.00 92.18 0.01 97.69 0.00 92.52 0.68 96.58 0.00 96.61 0.00 93.40 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.2959607328
94.93 0.08 95.03 0.05 92.37 0.19 97.69 0.00 92.52 0.00 96.69 0.11 96.61 0.00 93.59 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4219345601
94.98 0.06 95.03 0.00 92.46 0.09 97.69 0.00 92.52 0.00 96.69 0.00 96.61 0.00 93.90 0.31 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.898017281
95.04 0.06 95.03 0.00 92.48 0.02 97.69 0.00 92.52 0.00 96.69 0.00 96.61 0.00 94.27 0.37 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3800215096
95.09 0.05 95.03 0.00 92.49 0.01 97.69 0.00 92.52 0.00 96.69 0.00 96.61 0.00 94.64 0.37 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.714609654
95.14 0.05 95.05 0.03 92.51 0.02 97.69 0.00 92.52 0.00 96.71 0.02 96.71 0.09 94.79 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2423461685
95.18 0.04 95.05 0.00 92.51 0.00 97.69 0.00 92.52 0.00 96.71 0.00 96.71 0.00 95.10 0.31 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.615953232
95.22 0.04 95.08 0.03 92.63 0.12 97.77 0.08 92.52 0.00 96.77 0.06 96.71 0.00 95.10 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2949486032
95.27 0.04 95.08 0.00 92.64 0.01 97.77 0.00 92.52 0.00 96.77 0.00 96.71 0.00 95.38 0.28 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.230173543
95.31 0.04 95.08 0.00 92.64 0.00 97.77 0.00 92.52 0.00 96.77 0.00 96.99 0.28 95.38 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1891352283
95.34 0.04 95.09 0.01 92.67 0.03 97.90 0.13 92.52 0.00 96.82 0.04 96.99 0.00 95.44 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1413046204
95.38 0.04 95.09 0.00 92.71 0.04 97.90 0.00 92.52 0.00 96.86 0.04 96.99 0.00 95.62 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.501931155
95.41 0.03 95.09 0.00 92.93 0.22 97.90 0.00 92.52 0.00 96.86 0.00 96.99 0.00 95.62 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4193541466
95.44 0.03 95.09 0.00 92.93 0.00 97.90 0.00 92.52 0.00 96.86 0.00 96.99 0.00 95.84 0.22 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3632730652
95.48 0.03 95.09 0.00 92.95 0.03 97.90 0.00 92.52 0.00 96.86 0.00 96.99 0.00 96.02 0.18 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.1140163956
95.50 0.03 95.11 0.02 93.02 0.07 97.90 0.00 92.52 0.00 96.92 0.06 96.99 0.00 96.05 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1804162642
95.53 0.03 95.16 0.05 93.04 0.02 97.93 0.03 92.52 0.00 96.97 0.04 96.99 0.00 96.09 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.1886281140
95.55 0.02 95.16 0.00 93.06 0.02 97.93 0.00 92.52 0.00 96.97 0.00 96.99 0.00 96.24 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1359176657
95.58 0.02 95.17 0.01 93.14 0.09 97.93 0.00 92.52 0.00 97.01 0.04 96.99 0.00 96.27 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2944157395
95.60 0.02 95.18 0.01 93.16 0.02 97.93 0.00 92.52 0.00 97.05 0.04 96.99 0.00 96.36 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3727830254
95.62 0.02 95.18 0.00 93.16 0.00 97.93 0.00 92.52 0.00 97.05 0.00 96.99 0.00 96.52 0.15 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3653510941
95.64 0.02 95.18 0.00 93.23 0.07 98.01 0.08 92.52 0.00 97.05 0.00 96.99 0.00 96.52 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.4240398509
95.66 0.02 95.18 0.00 93.25 0.02 98.01 0.00 92.52 0.00 97.05 0.00 96.99 0.00 96.64 0.12 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1950184425
95.68 0.02 95.18 0.00 93.29 0.04 98.04 0.03 92.52 0.00 97.05 0.00 96.99 0.00 96.70 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.3668916246
95.70 0.02 95.22 0.04 93.29 0.00 98.06 0.02 92.52 0.00 97.05 0.00 96.99 0.00 96.76 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.773892498
95.71 0.01 95.22 0.00 93.30 0.01 98.06 0.00 92.52 0.00 97.05 0.00 96.99 0.00 96.86 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1769057929
95.73 0.01 95.22 0.00 93.31 0.01 98.06 0.00 92.52 0.00 97.05 0.00 96.99 0.00 96.95 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.1408244546
95.74 0.01 95.22 0.00 93.31 0.00 98.15 0.10 92.52 0.00 97.05 0.00 96.99 0.00 96.95 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3288850494
95.75 0.01 95.22 0.00 93.31 0.00 98.15 0.00 92.52 0.00 97.05 0.00 96.99 0.00 97.04 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2088289047
95.77 0.01 95.22 0.00 93.31 0.00 98.15 0.00 92.52 0.00 97.05 0.00 96.99 0.00 97.13 0.09 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.290374973
95.78 0.01 95.23 0.01 93.32 0.01 98.15 0.00 92.52 0.00 97.09 0.04 96.99 0.00 97.16 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3390421439
95.79 0.01 95.24 0.01 93.33 0.01 98.15 0.00 92.52 0.00 97.14 0.04 96.99 0.00 97.19 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4038616867
95.81 0.01 95.24 0.00 93.37 0.05 98.15 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.23 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.3929946759
95.82 0.01 95.24 0.00 93.45 0.08 98.15 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2679221789
95.83 0.01 95.24 0.00 93.46 0.01 98.22 0.06 92.52 0.00 97.14 0.00 96.99 0.00 97.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2760067718
95.84 0.01 95.24 0.00 93.47 0.01 98.22 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.29 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.4164391464
95.85 0.01 95.24 0.00 93.53 0.07 98.22 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.29 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1594680349
95.86 0.01 95.24 0.00 93.53 0.00 98.25 0.03 92.52 0.00 97.14 0.00 96.99 0.00 97.32 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.2980950265
95.86 0.01 95.24 0.00 93.53 0.00 98.28 0.03 92.52 0.00 97.14 0.00 96.99 0.00 97.35 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.3779773727
95.87 0.01 95.24 0.00 93.53 0.00 98.28 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.41 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2588836150
95.88 0.01 95.24 0.00 93.53 0.00 98.28 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.47 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3948285917
95.89 0.01 95.24 0.00 93.53 0.00 98.28 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.53 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.1244109272
95.90 0.01 95.24 0.00 93.53 0.00 98.28 0.00 92.52 0.00 97.14 0.00 96.99 0.00 97.60 0.06 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2220108217
95.91 0.01 95.24 0.00 93.57 0.04 98.28 0.00 92.52 0.00 97.16 0.02 96.99 0.00 97.60 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1380072259
95.92 0.01 95.24 0.00 93.59 0.02 98.28 0.00 92.52 0.00 97.16 0.00 96.99 0.00 97.63 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2786365864
95.92 0.01 95.24 0.00 93.61 0.02 98.28 0.00 92.52 0.00 97.16 0.00 96.99 0.00 97.66 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.2477797694
95.93 0.01 95.24 0.00 93.63 0.02 98.28 0.00 92.52 0.00 97.16 0.00 96.99 0.00 97.69 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3678331051
95.94 0.01 95.24 0.00 93.68 0.05 98.28 0.00 92.52 0.00 97.16 0.00 96.99 0.00 97.69 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.1101578229
95.94 0.01 95.24 0.00 93.70 0.02 98.28 0.00 92.52 0.00 97.18 0.02 96.99 0.00 97.69 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.1370899406
95.95 0.01 95.24 0.00 93.71 0.01 98.28 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.72 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.17694469
95.95 0.01 95.24 0.00 93.74 0.04 98.28 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.2348108026
95.96 0.01 95.24 0.00 93.78 0.04 98.28 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1231480408
95.96 0.01 95.24 0.00 93.82 0.04 98.28 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.375992580
95.97 0.01 95.24 0.00 93.82 0.00 98.31 0.03 92.52 0.00 97.18 0.00 96.99 0.00 97.72 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.674051694
95.97 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2753161349
95.98 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2805021425
95.98 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2177241631
95.99 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.886219588
95.99 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3092292618
95.99 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.204769329
96.00 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2585626278
96.00 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.2432285774
96.01 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.2180070168
96.01 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.3378324052
96.02 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.4235633932
96.02 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.2825939710
96.03 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.1122402547
96.03 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.15 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.3620781786
96.03 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.18 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.1911381444
96.04 0.01 95.24 0.00 93.82 0.00 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.03 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.963233541
96.04 0.01 95.24 0.00 93.85 0.03 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1663405587
96.05 0.01 95.24 0.00 93.88 0.03 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.541308293
96.05 0.01 95.24 0.00 93.91 0.03 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1385143825
96.05 0.01 95.24 0.00 93.92 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.100967329
96.05 0.01 95.24 0.00 93.92 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.521686450
96.06 0.01 95.24 0.00 93.93 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1171881714
96.06 0.01 95.24 0.00 93.94 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.3455718224
96.06 0.01 95.24 0.00 93.95 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.2227888279
96.06 0.01 95.24 0.00 93.96 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.3810829143
96.06 0.01 95.24 0.00 93.97 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3163980887
96.06 0.01 95.24 0.00 93.98 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.3208676928
96.06 0.01 95.24 0.00 93.99 0.01 98.31 0.00 92.52 0.00 97.18 0.00 96.99 0.00 98.21 0.00 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2517992461

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3851371001
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2258727223
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4003270127
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1749698136
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1965556248
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4208692987
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3436977323
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1473609385
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3504514495
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2423490089
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.243570265
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3291419109
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2031613836
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.369229044
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3514828216
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.740633049
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2248422668
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.105729948
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.16068557
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3176531054
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.256517955
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3547377630
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.157797776
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2911605329
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2312824418
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2849518003
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.2453423822
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.503702178
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2959325731
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.246360965
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.174910039
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1694924575
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2679827749
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.749934394
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4170269568
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.497031524
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1602124740
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1796337724
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2781522833
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1892560610
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1686692287
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1928473432
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1411369498
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1559094567
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3571626834
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.949888582
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2077803214
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1079223467
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2881440459
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.373518145
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.534372136
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1226633201
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4282818541
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3872532270
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2009520822
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2524101468
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1395169905
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1791782353
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1026058079
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1295485171
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.531374201
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2709091900
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.526030590
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2753123746
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1326441448
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1842275882
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1641088598
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4169592576
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.478026917
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1564322446
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3656109484
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.995968095
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/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.3077381085
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1219086713
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.3691308970
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1050088214
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.2552324193
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.4107770709



Total test records in report: 1266
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.35424103 Sep 18 04:57:21 PM UTC 24 Sep 18 04:57:41 PM UTC 24 42251200 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2051054430 Sep 18 04:57:21 PM UTC 24 Sep 18 04:57:43 PM UTC 24 268032200 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.908069296 Sep 18 04:57:21 PM UTC 24 Sep 18 04:57:48 PM UTC 24 75546300 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.2017915021 Sep 18 04:57:27 PM UTC 24 Sep 18 04:57:48 PM UTC 24 45477300 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.642702920 Sep 18 04:57:23 PM UTC 24 Sep 18 04:57:50 PM UTC 24 27176100 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1744163721 Sep 18 04:57:21 PM UTC 24 Sep 18 04:57:51 PM UTC 24 904298000 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.4039152013 Sep 18 04:57:20 PM UTC 24 Sep 18 04:57:52 PM UTC 24 28154200 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.3068649695 Sep 18 04:57:23 PM UTC 24 Sep 18 04:57:54 PM UTC 24 31467600 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.773892498 Sep 18 04:57:27 PM UTC 24 Sep 18 04:57:55 PM UTC 24 17248700 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.2592672781 Sep 18 04:57:20 PM UTC 24 Sep 18 04:58:02 PM UTC 24 177358000 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2949486032 Sep 18 04:57:38 PM UTC 24 Sep 18 04:58:07 PM UTC 24 13000100 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.204769329 Sep 18 04:57:23 PM UTC 24 Sep 18 04:58:07 PM UTC 24 71142000 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3262841158 Sep 18 04:57:51 PM UTC 24 Sep 18 04:58:08 PM UTC 24 71638900 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1999852505 Sep 18 04:57:23 PM UTC 24 Sep 18 04:58:10 PM UTC 24 106301200 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.333492468 Sep 18 04:57:44 PM UTC 24 Sep 18 04:58:10 PM UTC 24 24329000 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2679221789 Sep 18 04:57:27 PM UTC 24 Sep 18 04:58:13 PM UTC 24 1090800100 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1918722090 Sep 18 04:57:44 PM UTC 24 Sep 18 04:58:15 PM UTC 24 876189600 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2944157395 Sep 18 04:57:51 PM UTC 24 Sep 18 04:58:15 PM UTC 24 22609800 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1391671461 Sep 18 04:57:51 PM UTC 24 Sep 18 04:58:16 PM UTC 24 25643900 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2474303351 Sep 18 04:57:23 PM UTC 24 Sep 18 04:58:18 PM UTC 24 834671800 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2177241631 Sep 18 04:57:51 PM UTC 24 Sep 18 04:58:18 PM UTC 24 30592100 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.3374806323 Sep 18 04:57:55 PM UTC 24 Sep 18 04:58:21 PM UTC 24 73817700 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2038766948 Sep 18 04:57:23 PM UTC 24 Sep 18 04:58:23 PM UTC 24 1083581900 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3613869881 Sep 18 04:57:58 PM UTC 24 Sep 18 04:58:36 PM UTC 24 17541800 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2017818190 Sep 18 04:57:44 PM UTC 24 Sep 18 04:58:39 PM UTC 24 645929400 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.1703259018 Sep 18 04:58:03 PM UTC 24 Sep 18 04:58:39 PM UTC 24 33349700 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.2341517620 Sep 18 04:57:20 PM UTC 24 Sep 18 04:58:40 PM UTC 24 4164097300 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4219345601 Sep 18 04:57:21 PM UTC 24 Sep 18 04:58:42 PM UTC 24 3441043600 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.2965265070 Sep 18 04:57:53 PM UTC 24 Sep 18 04:58:44 PM UTC 24 64691800 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1263482587 Sep 18 04:57:21 PM UTC 24 Sep 18 04:58:49 PM UTC 24 3754550300 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1380072259 Sep 18 04:58:19 PM UTC 24 Sep 18 04:58:52 PM UTC 24 1545409300 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.2267951939 Sep 18 04:57:27 PM UTC 24 Sep 18 04:58:56 PM UTC 24 2871890700 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2349901453 Sep 18 04:57:53 PM UTC 24 Sep 18 04:59:00 PM UTC 24 277636300 ps
T104 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.699888762 Sep 18 04:57:21 PM UTC 24 Sep 18 04:59:03 PM UTC 24 2031541900 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1663405587 Sep 18 04:57:23 PM UTC 24 Sep 18 04:59:05 PM UTC 24 5086807000 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.3113852221 Sep 18 04:57:21 PM UTC 24 Sep 18 04:59:14 PM UTC 24 2622402200 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.2108579531 Sep 18 04:58:11 PM UTC 24 Sep 18 04:59:19 PM UTC 24 2478806200 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1137151106 Sep 18 04:57:23 PM UTC 24 Sep 18 04:59:21 PM UTC 24 1069089800 ps
T234 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.413879614 Sep 18 04:58:44 PM UTC 24 Sep 18 04:59:27 PM UTC 24 40546000 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2035449062 Sep 18 04:57:23 PM UTC 24 Sep 18 04:59:49 PM UTC 24 1032102800 ps
T72 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.3956116240 Sep 18 04:59:04 PM UTC 24 Sep 18 04:59:50 PM UTC 24 59713200 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1359176657 Sep 18 04:57:23 PM UTC 24 Sep 18 04:59:54 PM UTC 24 1346509100 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.3806431010 Sep 18 04:57:21 PM UTC 24 Sep 18 04:59:59 PM UTC 24 2139989800 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1589413993 Sep 18 04:57:23 PM UTC 24 Sep 18 05:00:04 PM UTC 24 5509889200 ps
T107 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.4079727336 Sep 18 04:57:20 PM UTC 24 Sep 18 05:00:09 PM UTC 24 59060600 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2154575473 Sep 18 04:57:20 PM UTC 24 Sep 18 05:00:12 PM UTC 24 297265600 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2026065745 Sep 18 04:58:40 PM UTC 24 Sep 18 05:00:12 PM UTC 24 4227577900 ps
T282 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1567766389 Sep 18 04:59:01 PM UTC 24 Sep 18 05:00:13 PM UTC 24 1285318600 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.2996597524 Sep 18 04:57:23 PM UTC 24 Sep 18 05:00:15 PM UTC 24 754079900 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.781465403 Sep 18 04:57:20 PM UTC 24 Sep 18 05:00:17 PM UTC 24 76332100 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.4253453448 Sep 18 05:00:00 PM UTC 24 Sep 18 05:00:24 PM UTC 24 27380400 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.3884120809 Sep 18 04:57:23 PM UTC 24 Sep 18 05:00:25 PM UTC 24 7428130700 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.2193297405 Sep 18 04:58:58 PM UTC 24 Sep 18 05:00:35 PM UTC 24 727789500 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.1408526664 Sep 18 04:57:20 PM UTC 24 Sep 18 05:00:43 PM UTC 24 78880100 ps
T235 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.1441735128 Sep 18 04:57:56 PM UTC 24 Sep 18 05:00:44 PM UTC 24 55876900 ps
T110 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3380858598 Sep 18 04:57:53 PM UTC 24 Sep 18 05:00:46 PM UTC 24 10019047200 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.3900975125 Sep 18 04:58:41 PM UTC 24 Sep 18 05:00:48 PM UTC 24 1035504400 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3725470498 Sep 18 05:00:10 PM UTC 24 Sep 18 05:00:49 PM UTC 24 28395400 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.1411140396 Sep 18 05:00:25 PM UTC 24 Sep 18 05:00:54 PM UTC 24 29584500 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1331250738 Sep 18 05:00:35 PM UTC 24 Sep 18 05:00:56 PM UTC 24 12903900 ps
T283 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.3772151943 Sep 18 05:00:15 PM UTC 24 Sep 18 05:00:57 PM UTC 24 30311900 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.529839108 Sep 18 05:00:35 PM UTC 24 Sep 18 05:01:01 PM UTC 24 47367500 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.1332847274 Sep 18 04:58:40 PM UTC 24 Sep 18 05:01:04 PM UTC 24 11808499700 ps
T232 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.1140163956 Sep 18 04:58:08 PM UTC 24 Sep 18 05:01:05 PM UTC 24 171482300 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2340989880 Sep 18 05:00:08 PM UTC 24 Sep 18 05:01:07 PM UTC 24 80325600 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3469633330 Sep 18 05:00:50 PM UTC 24 Sep 18 05:01:09 PM UTC 24 53266600 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1334453831 Sep 18 05:00:27 PM UTC 24 Sep 18 05:01:09 PM UTC 24 89533200 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.1020148175 Sep 18 04:58:50 PM UTC 24 Sep 18 05:01:12 PM UTC 24 2737201700 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.1612068364 Sep 18 04:59:50 PM UTC 24 Sep 18 05:01:13 PM UTC 24 9329251900 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.541308293 Sep 18 05:00:50 PM UTC 24 Sep 18 05:01:14 PM UTC 24 15955800 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.490718363 Sep 18 05:01:05 PM UTC 24 Sep 18 05:01:34 PM UTC 24 66821100 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.517174168 Sep 18 04:57:23 PM UTC 24 Sep 18 05:01:16 PM UTC 24 56925287200 ps
T177 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.674051694 Sep 18 05:00:58 PM UTC 24 Sep 18 05:01:16 PM UTC 24 15492100 ps
T236 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.3455718224 Sep 18 05:00:48 PM UTC 24 Sep 18 05:01:16 PM UTC 24 42875200 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1782773072 Sep 18 05:00:15 PM UTC 24 Sep 18 05:01:18 PM UTC 24 433640600 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.2348108026 Sep 18 05:00:46 PM UTC 24 Sep 18 05:01:20 PM UTC 24 637016700 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3675241430 Sep 18 05:00:58 PM UTC 24 Sep 18 05:01:23 PM UTC 24 17953400 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2078378159 Sep 18 04:58:09 PM UTC 24 Sep 18 05:01:28 PM UTC 24 130356000 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.512538108 Sep 18 04:57:23 PM UTC 24 Sep 18 05:01:32 PM UTC 24 62774053300 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.2839440618 Sep 18 04:58:08 PM UTC 24 Sep 18 05:01:35 PM UTC 24 2522327100 ps
T90 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2003446700 Sep 18 04:57:23 PM UTC 24 Sep 18 05:01:35 PM UTC 24 742482100 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1769057929 Sep 18 05:00:17 PM UTC 24 Sep 18 05:01:41 PM UTC 24 5614760100 ps
T259 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2553374475 Sep 18 05:01:05 PM UTC 24 Sep 18 05:01:42 PM UTC 24 65733300 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.3098920990 Sep 18 05:01:09 PM UTC 24 Sep 18 05:01:45 PM UTC 24 142119000 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.4294006071 Sep 18 04:58:41 PM UTC 24 Sep 18 05:01:47 PM UTC 24 2426638100 ps
T211 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.2569375250 Sep 18 04:59:06 PM UTC 24 Sep 18 05:01:47 PM UTC 24 572658900 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.3342596689 Sep 18 05:00:45 PM UTC 24 Sep 18 05:01:49 PM UTC 24 1394566300 ps
T223 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1710528820 Sep 18 04:58:52 PM UTC 24 Sep 18 05:01:57 PM UTC 24 2830041800 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.587339260 Sep 18 05:01:32 PM UTC 24 Sep 18 05:01:59 PM UTC 24 566087800 ps
T311 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.1230390235 Sep 18 05:01:14 PM UTC 24 Sep 18 05:02:07 PM UTC 24 42106700 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.2631326438 Sep 18 04:58:17 PM UTC 24 Sep 18 05:02:10 PM UTC 24 17863976100 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3948285917 Sep 18 04:59:22 PM UTC 24 Sep 18 05:02:13 PM UTC 24 3042805600 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1269743053 Sep 18 04:58:17 PM UTC 24 Sep 18 05:02:18 PM UTC 24 55492900 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.875005747 Sep 18 05:01:58 PM UTC 24 Sep 18 05:02:40 PM UTC 24 26100200 ps
T77 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.714620678 Sep 18 04:59:52 PM UTC 24 Sep 18 05:02:45 PM UTC 24 6043761400 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.512065529 Sep 18 04:59:15 PM UTC 24 Sep 18 05:02:46 PM UTC 24 2457809500 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.3665188508 Sep 18 05:01:17 PM UTC 24 Sep 18 05:02:56 PM UTC 24 8998873100 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2937187851 Sep 18 05:02:18 PM UTC 24 Sep 18 05:03:03 PM UTC 24 197766500 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.462035438 Sep 18 04:59:36 PM UTC 24 Sep 18 05:03:17 PM UTC 24 1738305500 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1413046204 Sep 18 05:01:01 PM UTC 24 Sep 18 05:03:21 PM UTC 24 10012047100 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2162789607 Sep 18 05:01:43 PM UTC 24 Sep 18 05:03:22 PM UTC 24 8266557300 ps
T64 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.887446161 Sep 18 05:01:46 PM UTC 24 Sep 18 05:03:23 PM UTC 24 2212599200 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.2477797694 Sep 18 04:59:20 PM UTC 24 Sep 18 05:03:29 PM UTC 24 911235800 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3876458235 Sep 18 05:02:12 PM UTC 24 Sep 18 05:03:32 PM UTC 24 396000400 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.4229985088 Sep 18 05:03:24 PM UTC 24 Sep 18 05:03:47 PM UTC 24 121361900 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.2598790438 Sep 18 05:01:14 PM UTC 24 Sep 18 05:03:59 PM UTC 24 55583000 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.4196459457 Sep 18 05:01:15 PM UTC 24 Sep 18 05:04:12 PM UTC 24 347380900 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.794169475 Sep 18 05:01:59 PM UTC 24 Sep 18 05:04:20 PM UTC 24 1129630500 ps
T207 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2207190866 Sep 18 05:02:13 PM UTC 24 Sep 18 05:04:23 PM UTC 24 3601419200 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2388090589 Sep 18 05:01:48 PM UTC 24 Sep 18 05:04:26 PM UTC 24 5215609600 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.4083454725 Sep 18 05:03:33 PM UTC 24 Sep 18 05:04:30 PM UTC 24 29892500 ps
T233 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1013389742 Sep 18 05:05:17 PM UTC 24 Sep 18 05:08:23 PM UTC 24 95673700 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.4176280622 Sep 18 05:03:17 PM UTC 24 Sep 18 05:04:31 PM UTC 24 8762731000 ps
T130 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3175015998 Sep 18 05:04:00 PM UTC 24 Sep 18 05:04:36 PM UTC 24 21150100 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.3161250836 Sep 18 05:01:48 PM UTC 24 Sep 18 05:04:37 PM UTC 24 4208625000 ps
T160 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.3990976686 Sep 18 05:01:10 PM UTC 24 Sep 18 05:04:43 PM UTC 24 151074400 ps
T161 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.1754949572 Sep 18 05:03:48 PM UTC 24 Sep 18 05:04:43 PM UTC 24 243930200 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.2896874833 Sep 18 05:04:26 PM UTC 24 Sep 18 05:04:51 PM UTC 24 26604500 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.610026103 Sep 18 05:02:07 PM UTC 24 Sep 18 05:05:02 PM UTC 24 1841575100 ps
T93 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.828913171 Sep 18 05:01:20 PM UTC 24 Sep 18 05:05:02 PM UTC 24 38282000 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.3810829143 Sep 18 05:04:32 PM UTC 24 Sep 18 05:05:03 PM UTC 24 14281900 ps
T123 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3595420406 Sep 18 05:04:31 PM UTC 24 Sep 18 05:05:04 PM UTC 24 161875800 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.907119487 Sep 18 05:04:30 PM UTC 24 Sep 18 05:05:07 PM UTC 24 216491700 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2013976740 Sep 18 05:04:44 PM UTC 24 Sep 18 05:05:11 PM UTC 24 45189900 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3768244806 Sep 18 05:01:07 PM UTC 24 Sep 18 05:05:13 PM UTC 24 46913300 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.317720401 Sep 18 05:04:52 PM UTC 24 Sep 18 05:05:15 PM UTC 24 20305700 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.3248293706 Sep 18 05:02:41 PM UTC 24 Sep 18 05:05:17 PM UTC 24 2401673500 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.1101578229 Sep 18 05:04:38 PM UTC 24 Sep 18 05:05:17 PM UTC 24 755088300 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3756131806 Sep 18 05:04:37 PM UTC 24 Sep 18 05:05:24 PM UTC 24 334771700 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3621339590 Sep 18 05:02:54 PM UTC 24 Sep 18 05:05:26 PM UTC 24 877138400 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.2082410212 Sep 18 05:01:15 PM UTC 24 Sep 18 05:05:27 PM UTC 24 9756355100 ps
T178 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3556472868 Sep 18 05:05:03 PM UTC 24 Sep 18 05:05:30 PM UTC 24 15562900 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.2607746064 Sep 18 05:05:04 PM UTC 24 Sep 18 05:05:30 PM UTC 24 204567900 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.1838062409 Sep 18 05:02:45 PM UTC 24 Sep 18 05:05:42 PM UTC 24 6038914000 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.1818746445 Sep 18 05:05:12 PM UTC 24 Sep 18 05:05:42 PM UTC 24 65564000 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.918379324 Sep 18 05:05:08 PM UTC 24 Sep 18 05:05:47 PM UTC 24 62071700 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.585204661 Sep 18 04:57:20 PM UTC 24 Sep 18 05:05:51 PM UTC 24 2130424200 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.2391772554 Sep 18 05:05:15 PM UTC 24 Sep 18 05:05:58 PM UTC 24 37447500 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1014858400 Sep 18 04:57:27 PM UTC 24 Sep 18 05:06:00 PM UTC 24 365329300 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3889857142 Sep 18 04:58:11 PM UTC 24 Sep 18 05:06:02 PM UTC 24 2784069400 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.708722330 Sep 18 05:05:18 PM UTC 24 Sep 18 05:06:02 PM UTC 24 91981500 ps
T254 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1171881714 Sep 18 04:57:21 PM UTC 24 Sep 18 05:06:03 PM UTC 24 3698095000 ps
T255 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.2335057007 Sep 18 04:58:43 PM UTC 24 Sep 18 05:06:06 PM UTC 24 4111129800 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2068519930 Sep 18 05:03:22 PM UTC 24 Sep 18 05:06:09 PM UTC 24 5892686300 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.3897893284 Sep 18 05:02:47 PM UTC 24 Sep 18 05:06:09 PM UTC 24 1207914500 ps
T179 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.1244109272 Sep 18 05:04:21 PM UTC 24 Sep 18 05:06:17 PM UTC 24 4408465500 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2639109258 Sep 18 05:03:05 PM UTC 24 Sep 18 05:06:36 PM UTC 24 5841217100 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.2493259236 Sep 18 05:05:53 PM UTC 24 Sep 18 05:06:36 PM UTC 24 1679320400 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1620106361 Sep 18 04:59:56 PM UTC 24 Sep 18 05:06:42 PM UTC 24 201363824100 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.532159778 Sep 18 05:05:04 PM UTC 24 Sep 18 05:06:58 PM UTC 24 10016935000 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.3208430080 Sep 18 05:06:37 PM UTC 24 Sep 18 05:07:07 PM UTC 24 194964000 ps
T319 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3202604373 Sep 18 04:57:23 PM UTC 24 Sep 18 05:07:13 PM UTC 24 15836259200 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.1291367831 Sep 18 04:57:20 PM UTC 24 Sep 18 05:07:14 PM UTC 24 184224100 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.552281008 Sep 18 05:05:25 PM UTC 24 Sep 18 05:07:32 PM UTC 24 93891300 ps
T162 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.523646137 Sep 18 05:06:04 PM UTC 24 Sep 18 05:07:46 PM UTC 24 3916820500 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.1260248949 Sep 18 05:07:14 PM UTC 24 Sep 18 05:07:55 PM UTC 24 18576400 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.1105539312 Sep 18 05:06:59 PM UTC 24 Sep 18 05:08:14 PM UTC 24 6712265000 ps
T230 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3168397441 Sep 18 05:06:10 PM UTC 24 Sep 18 05:08:18 PM UTC 24 3335897300 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.3786356837 Sep 18 05:07:08 PM UTC 24 Sep 18 05:08:20 PM UTC 24 1447079200 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.2565449762 Sep 18 05:06:07 PM UTC 24 Sep 18 05:08:20 PM UTC 24 3293388400 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3398149826 Sep 18 05:05:13 PM UTC 24 Sep 18 05:08:37 PM UTC 24 35670500 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3227048036 Sep 18 05:05:28 PM UTC 24 Sep 18 05:08:39 PM UTC 24 2231399000 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3603970231 Sep 18 05:06:10 PM UTC 24 Sep 18 05:08:55 PM UTC 24 8229776400 ps
T231 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1950184425 Sep 18 05:01:50 PM UTC 24 Sep 18 05:09:04 PM UTC 24 3898796400 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2911409903 Sep 18 05:06:37 PM UTC 24 Sep 18 05:09:05 PM UTC 24 2664528000 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.161955412 Sep 18 05:08:38 PM UTC 24 Sep 18 05:09:06 PM UTC 24 54958600 ps
T139 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.3692057801 Sep 18 05:05:43 PM UTC 24 Sep 18 05:09:09 PM UTC 24 429678800 ps
T284 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.3914977359 Sep 18 05:05:18 PM UTC 24 Sep 18 05:09:18 PM UTC 24 430139700 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.88402075 Sep 18 05:01:17 PM UTC 24 Sep 18 05:09:18 PM UTC 24 1426480600 ps
T225 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.1017059533 Sep 18 05:06:44 PM UTC 24 Sep 18 05:09:23 PM UTC 24 2388930000 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.68559561 Sep 18 05:03:23 PM UTC 24 Sep 18 05:09:32 PM UTC 24 44086129200 ps
T128 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2070089724 Sep 18 05:09:06 PM UTC 24 Sep 18 05:09:33 PM UTC 24 30598100 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.250299286 Sep 18 05:08:40 PM UTC 24 Sep 18 05:09:39 PM UTC 24 31949400 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1669505670 Sep 18 05:08:21 PM UTC 24 Sep 18 05:09:41 PM UTC 24 5279926100 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.891184140 Sep 18 05:09:19 PM UTC 24 Sep 18 05:09:43 PM UTC 24 21261400 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.3532787318 Sep 18 05:08:55 PM UTC 24 Sep 18 05:09:44 PM UTC 24 63042000 ps
T237 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.1536559270 Sep 18 05:09:34 PM UTC 24 Sep 18 05:09:55 PM UTC 24 23822400 ps
T163 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.3874493568 Sep 18 04:57:20 PM UTC 24 Sep 18 05:09:56 PM UTC 24 797244600 ps
T102 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1231480408 Sep 18 05:09:33 PM UTC 24 Sep 18 05:09:59 PM UTC 24 685976900 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.1339507103 Sep 18 05:09:41 PM UTC 24 Sep 18 05:10:03 PM UTC 24 35094400 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1299027362 Sep 18 05:09:40 PM UTC 24 Sep 18 05:10:03 PM UTC 24 27176500 ps
T316 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.1021196039 Sep 18 05:07:14 PM UTC 24 Sep 18 05:10:04 PM UTC 24 2379544200 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.2605021555 Sep 18 05:09:45 PM UTC 24 Sep 18 05:10:06 PM UTC 24 27048600 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.310418939 Sep 18 05:09:43 PM UTC 24 Sep 18 05:10:09 PM UTC 24 48546000 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.230173543 Sep 18 05:09:04 PM UTC 24 Sep 18 05:10:10 PM UTC 24 72147600 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.898017281 Sep 18 05:09:24 PM UTC 24 Sep 18 05:10:12 PM UTC 24 362329500 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.198321408 Sep 18 05:09:58 PM UTC 24 Sep 18 05:10:19 PM UTC 24 47620600 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.2248666790 Sep 18 05:09:10 PM UTC 24 Sep 18 05:10:20 PM UTC 24 903242800 ps
T226 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.135848136 Sep 18 05:07:56 PM UTC 24 Sep 18 05:10:30 PM UTC 24 3857681200 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.41930606 Sep 18 05:10:04 PM UTC 24 Sep 18 05:10:48 PM UTC 24 13819500 ps
T78 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1806911212 Sep 18 05:01:28 PM UTC 24 Sep 18 05:10:55 PM UTC 24 30915521400 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3893097902 Sep 18 05:10:05 PM UTC 24 Sep 18 05:10:56 PM UTC 24 70393600 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.375992580 Sep 18 05:07:33 PM UTC 24 Sep 18 05:11:05 PM UTC 24 3366049100 ps
T170 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.536154915 Sep 18 05:10:13 PM UTC 24 Sep 18 05:11:12 PM UTC 24 4708327100 ps
T171 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.3852561358 Sep 18 05:10:07 PM UTC 24 Sep 18 05:11:20 PM UTC 24 123539200 ps
T172 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.238130045 Sep 18 04:59:28 PM UTC 24 Sep 18 05:11:26 PM UTC 24 4237645600 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.360685276 Sep 18 05:07:47 PM UTC 24 Sep 18 05:11:33 PM UTC 24 1281506100 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.2412489013 Sep 18 05:10:57 PM UTC 24 Sep 18 05:11:33 PM UTC 24 611078200 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.714609654 Sep 18 05:08:19 PM UTC 24 Sep 18 05:11:42 PM UTC 24 595207400 ps
T111 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.886312494 Sep 18 05:09:55 PM UTC 24 Sep 18 05:11:52 PM UTC 24 10027867500 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.549055822 Sep 18 04:58:15 PM UTC 24 Sep 18 05:12:10 PM UTC 24 160172113900 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.530303679 Sep 18 05:10:10 PM UTC 24 Sep 18 05:12:20 PM UTC 24 279199200 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.501931155 Sep 18 05:08:21 PM UTC 24 Sep 18 05:12:30 PM UTC 24 22176721200 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.1570413762 Sep 18 04:57:51 PM UTC 24 Sep 18 05:12:31 PM UTC 24 167187055600 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3092292618 Sep 18 04:57:21 PM UTC 24 Sep 18 05:12:32 PM UTC 24 33780353200 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.2864506056 Sep 18 04:57:20 PM UTC 24 Sep 18 05:12:33 PM UTC 24 160169098300 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.1597563936 Sep 18 05:10:01 PM UTC 24 Sep 18 05:12:54 PM UTC 24 61372200 ps
T256 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1607606329 Sep 18 05:10:11 PM UTC 24 Sep 18 05:12:54 PM UTC 24 679497600 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3893744125 Sep 18 05:12:21 PM UTC 24 Sep 18 05:13:00 PM UTC 24 68355300 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.882035535 Sep 18 05:10:31 PM UTC 24 Sep 18 05:13:01 PM UTC 24 44823300 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.4120651448 Sep 18 05:11:34 PM UTC 24 Sep 18 05:13:01 PM UTC 24 2517171100 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.1704815599 Sep 18 05:11:33 PM UTC 24 Sep 18 05:13:06 PM UTC 24 2031996100 ps
T257 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2195822229 Sep 18 05:05:30 PM UTC 24 Sep 18 05:13:17 PM UTC 24 5560535600 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.4269545751 Sep 18 05:12:55 PM UTC 24 Sep 18 05:13:23 PM UTC 24 34525700 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.1308158048 Sep 18 05:11:53 PM UTC 24 Sep 18 05:13:44 PM UTC 24 2258394200 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.4265112097 Sep 18 05:12:33 PM UTC 24 Sep 18 05:13:59 PM UTC 24 693973700 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.1275793097 Sep 18 05:06:18 PM UTC 24 Sep 18 05:14:09 PM UTC 24 80060432200 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2063951558 Sep 18 05:12:34 PM UTC 24 Sep 18 05:14:13 PM UTC 24 1431426400 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.2568962672 Sep 18 05:11:43 PM UTC 24 Sep 18 05:14:32 PM UTC 24 5906215600 ps
T312 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.2156519228 Sep 18 05:14:10 PM UTC 24 Sep 18 05:14:34 PM UTC 24 22149600 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.3261918377 Sep 18 05:12:31 PM UTC 24 Sep 18 05:14:40 PM UTC 24 1718099600 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.3507519159 Sep 18 05:13:24 PM UTC 24 Sep 18 05:14:42 PM UTC 24 2539140500 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.3713046587 Sep 18 05:14:14 PM UTC 24 Sep 18 05:15:01 PM UTC 24 30813800 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.2862826767 Sep 18 05:10:56 PM UTC 24 Sep 18 05:15:11 PM UTC 24 7663608100 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2266830838 Sep 18 05:14:33 PM UTC 24 Sep 18 05:15:12 PM UTC 24 124462600 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.208065457 Sep 18 05:14:35 PM UTC 24 Sep 18 05:15:21 PM UTC 24 118779700 ps
T276 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.339749585 Sep 18 05:14:42 PM UTC 24 Sep 18 05:15:27 PM UTC 24 35050000 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1113811373 Sep 18 05:08:24 PM UTC 24 Sep 18 05:15:38 PM UTC 24 144471805500 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.474243316 Sep 18 05:08:15 PM UTC 24 Sep 18 05:15:40 PM UTC 24 21366143600 ps
T320 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.793251439 Sep 18 05:15:13 PM UTC 24 Sep 18 05:15:41 PM UTC 24 14900400 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.657272460 Sep 18 05:15:27 PM UTC 24 Sep 18 05:15:50 PM UTC 24 775965800 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2866673459 Sep 18 05:13:02 PM UTC 24 Sep 18 05:15:51 PM UTC 24 1479533300 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.2007866487 Sep 18 05:13:17 PM UTC 24 Sep 18 05:15:52 PM UTC 24 614061500 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1016194253 Sep 18 05:12:56 PM UTC 24 Sep 18 05:15:59 PM UTC 24 1102276400 ps
T224 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1804162642 Sep 18 05:15:38 PM UTC 24 Sep 18 05:16:06 PM UTC 24 45728600 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3090266605 Sep 18 05:15:42 PM UTC 24 Sep 18 05:16:07 PM UTC 24 29801400 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.2191128914 Sep 18 05:15:22 PM UTC 24 Sep 18 05:16:09 PM UTC 24 337689700 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.79284797 Sep 18 05:15:52 PM UTC 24 Sep 18 05:16:09 PM UTC 24 46925900 ps
T239 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3282575782 Sep 18 05:15:40 PM UTC 24 Sep 18 05:16:10 PM UTC 24 110876700 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.509557642 Sep 18 05:15:51 PM UTC 24 Sep 18 05:16:12 PM UTC 24 25197000 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3619835801 Sep 18 05:13:46 PM UTC 24 Sep 18 05:16:14 PM UTC 24 5833824900 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1496438280 Sep 18 05:16:00 PM UTC 24 Sep 18 05:16:21 PM UTC 24 279220900 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2111899031 Sep 18 05:15:02 PM UTC 24 Sep 18 05:16:38 PM UTC 24 6850768200 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2899455439 Sep 18 05:13:02 PM UTC 24 Sep 18 05:16:44 PM UTC 24 1301139300 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.247205218 Sep 18 05:13:02 PM UTC 24 Sep 18 05:16:49 PM UTC 24 2309515000 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2821771480 Sep 18 05:16:22 PM UTC 24 Sep 18 05:16:57 PM UTC 24 412679900 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.569510126 Sep 18 05:12:32 PM UTC 24 Sep 18 05:17:06 PM UTC 24 1631466800 ps
T258 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.3076119261 Sep 18 05:05:27 PM UTC 24 Sep 18 05:17:11 PM UTC 24 2720809300 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.2925395581 Sep 18 05:01:18 PM UTC 24 Sep 18 05:17:28 PM UTC 24 160168006700 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.956495155 Sep 18 05:15:53 PM UTC 24 Sep 18 05:18:12 PM UTC 24 10017103200 ps
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