Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	223487	1		T1	20		T2	14		T3	20
auto[FlashEraseBank]	256384	1		T4	3		T5	1		T8	5

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	244295	1		T1	20		T3	20		T5	1
auto[FlashOpProgram]	216889	1		T2	14		T4	5		T10	1
auto[FlashOpErase]	14687	1		T10	1		T6	1		T25	19
auto[FlashOpInvalid]	4000	1		T32	200		T82	200		T89	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	244295	1		T1	20		T3	20		T5	1
op[FlashOpProgram]	216889	1		T2	14		T4	5		T10	1
op[FlashOpErase]	14687	1		T10	1		T6	1		T25	19
read_erase_read	558	1		T25	17		T42	1		T71	2
read_prog_read	817	1		T6	1		T31	1		T30	4

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	336906	1		T1	20		T3	20		T4	2
auto[FlashPartInfo]	135335	1		T2	14		T4	3		T5	1
auto[FlashPartInfo1]	2237	1		T67	1		T32	80		T104	1
auto[FlashPartInfo2]	5393	1		T31	4		T25	10		T30	4

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	173009	1		T1	20		T3	20		T8	49
auto[FlashPartData]	auto[FlashOpProgram]	159321	1		T4	2		T10	1		T6	3
auto[FlashPartData]	auto[FlashOpErase]	2584	1		T10	1		T6	1		T25	4
auto[FlashPartData]	auto[FlashOpInvalid]	1992	1		T32	84		T82	102		T89	118
auto[FlashPartInfo]	auto[FlashOpRead]	67225	1		T5	1		T31	5		T25	24
auto[FlashPartInfo]	auto[FlashOpProgram]	55724	1		T2	14		T4	3		T12	3
auto[FlashPartInfo]	auto[FlashOpErase]	11718	1		T25	11		T55	170		T32	20
auto[FlashPartInfo]	auto[FlashOpInvalid]	668	1		T32	40		T82	32		T89	32
auto[FlashPartInfo1]	auto[FlashOpRead]	1400	1		T67	1		T32	40		T104	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	160	1		T150	32		T153	32		T438	32
auto[FlashPartInfo1]	auto[FlashOpErase]	3	1		T147	1		T439	2		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	674	1		T32	40		T82	34		T89	20
auto[FlashPartInfo2]	auto[FlashOpRead]	2661	1		T31	3		T25	6		T67	1
auto[FlashPartInfo2]	auto[FlashOpProgram]	1684	1		T31	1		T30	4		T48	9
auto[FlashPartInfo2]	auto[FlashOpErase]	382	1		T25	4		T32	18		T82	16
auto[FlashPartInfo2]	auto[FlashOpInvalid]	666	1		T32	36		T82	32		T89	30