Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28356	1		T10	4		T26	4		T55	344
auto[1]	47	1		T39	1		T440	8		T441	4
auto[2]	96	1		T124	1		T34	4		T35	4
auto[3]	217	1		T31	1		T25	12		T38	1

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7183	1		T10	1		T25	3		T26	1
evic_idx[1]	7168	1		T10	1		T25	2		T26	1
evic_idx[2]	7194	1		T10	1		T31	1		T25	3
evic_idx[3]	7171	1		T10	1		T25	4		T26	1

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	27728	1		T10	4		T25	12		T26	4
evic_op[2]	335	1		T31	1		T107	32		T71	16

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6862	1		T10	1		T26	1		T55	86
evic_idx[0]	evic_op[1]	auto[1]	9	1		T440	2		T442	3		T443	3
evic_idx[0]	evic_op[1]	auto[2]	17	1		T440	1		T228	3		T444	5
evic_idx[0]	evic_op[1]	auto[3]	48	1		T25	3		T414	4		T161	2
evic_idx[0]	evic_op[2]	auto[0]	68	1		T107	8		T71	4		T232	7
evic_idx[0]	evic_op[2]	auto[1]	2	1		T441	1		T445	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	4	1		T124	1		T446	1		T447	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T448	1		T449	1		T450	1
evic_idx[1]	evic_op[1]	auto[0]	6863	1		T10	1		T26	1		T55	86
evic_idx[1]	evic_op[1]	auto[1]	8	1		T440	2		T442	2		T443	3
evic_idx[1]	evic_op[1]	auto[2]	13	1		T440	1		T228	2		T444	4
evic_idx[1]	evic_op[1]	auto[3]	43	1		T25	2		T414	2		T161	3
evic_idx[1]	evic_op[2]	auto[0]	64	1		T107	8		T71	4		T232	7
evic_idx[1]	evic_op[2]	auto[1]	3	1		T39	1		T441	1		T451	1
evic_idx[1]	evic_op[2]	auto[2]	3	1		T51	1		T452	2		-	-
evic_idx[1]	evic_op[2]	auto[3]	8	1		T453	1		T454	1		T455	1
evic_idx[2]	evic_op[1]	auto[0]	6866	1		T10	1		T26	1		T55	86
evic_idx[2]	evic_op[1]	auto[1]	10	1		T440	2		T442	3		T456	1
evic_idx[2]	evic_op[1]	auto[2]	15	1		T440	1		T228	2		T444	4
evic_idx[2]	evic_op[1]	auto[3]	48	1		T25	3		T414	6		T161	5
evic_idx[2]	evic_op[2]	auto[0]	65	1		T107	8		T71	4		T232	7
evic_idx[2]	evic_op[2]	auto[1]	5	1		T441	1		T457	1		T446	1
evic_idx[2]	evic_op[2]	auto[2]	7	1		T458	1		T449	1		T446	1
evic_idx[2]	evic_op[2]	auto[3]	15	1		T31	1		T38	1		T459	1
evic_idx[3]	evic_op[1]	auto[0]	6867	1		T10	1		T26	1		T55	86
evic_idx[3]	evic_op[1]	auto[1]	8	1		T440	2		T442	3		T456	1
evic_idx[3]	evic_op[1]	auto[2]	14	1		T440	1		T228	2		T444	3
evic_idx[3]	evic_op[1]	auto[3]	37	1		T25	4		T414	3		T161	2
evic_idx[3]	evic_op[2]	auto[0]	68	1		T107	8		T71	4		T232	7
evic_idx[3]	evic_op[2]	auto[1]	2	1		T441	1		T460	1		-	-
evic_idx[3]	evic_op[2]	auto[2]	3	1		T461	1		T446	1		T462	1
evic_idx[3]	evic_op[2]	auto[3]	9	1		T51	1		T332	1		T463	1