Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	35438	1		T174	1456		T356	2922		T357	15266
rd_lvl[2]	45972	1		T174	712		T358	1342		T356	2324
rd_lvl[3]	6238	1		T174	284		T359	1000		T358	372
rd_lvl[4]	30624	1		T174	484		T360	5667		T359	1181
rd_lvl[5]	12677	1		T174	188		T361	784		T362	710
rd_lvl[6]	17016	1		T174	63		T361	223		T362	218
rd_lvl[7]	9707	1		T47	738		T174	175		T363	1801
rd_lvl[8]	11552	1		T47	1669		T174	193		T361	7
rd_lvl[9]	4516	1		T47	1009		T174	255		T364	48
rd_lvl[10]	4163	1		T174	132		T359	1		T364	45
rd_lvl[11]	4170	1		T174	305		T361	7		T362	24
rd_lvl[12]	9179	1		T43	407		T174	1		T365	1044
rd_lvl[13]	2673	1		T43	107		T45	321		T174	2
rd_lvl[14]	5995	1		T45	1229		T174	194		T46	358
rd_lvl[15]	2508	1		T43	58		T46	195		T366	344