Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	316293	1		T1	2		T2	2		T3	2
all_pins[1]	316293	1		T1	2		T2	2		T3	2
all_pins[2]	316293	1		T1	2		T2	2		T3	2
all_pins[3]	316293	1		T1	2		T2	2		T3	2
all_pins[4]	316293	1		T1	2		T2	2		T3	2
all_pins[5]	316293	1		T1	2		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1584387	1		T1	12		T2	12		T3	12
values[0x1]	313371	1		T37	1708		T43	1144		T40	1598
transitions[0x0=>0x1]	283733	1		T37	1708		T43	1144		T40	1598
transitions[0x1=>0x0]	283716	1		T37	1708		T43	1144		T40	1598

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	316133	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	160	1		T266	3		T274	6		T347	2
all_pins[0]	transitions[0x0=>0x1]	90	1		T274	4		T349	1		T351	5
all_pins[0]	transitions[0x1=>0x0]	62	1		T266	2		T347	1		T348	1
all_pins[1]	values[0x0]	316161	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	132	1		T266	5		T274	2		T347	3
all_pins[1]	transitions[0x0=>0x1]	114	1		T266	3		T274	2		T347	3
all_pins[1]	transitions[0x1=>0x0]	2706	1		T46	6		T371	1302		T117	1027
all_pins[2]	values[0x0]	313569	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	2724	1		T46	6		T371	1302		T117	1027
all_pins[2]	transitions[0x0=>0x1]	42	1		T266	3		T274	1		T347	1
all_pins[2]	transitions[0x1=>0x0]	202514	1		T43	572		T45	1550		T47	3416
all_pins[3]	values[0x0]	111097	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	205196	1		T43	572		T45	1550		T47	3416
all_pins[3]	transitions[0x0=>0x1]	178380	1		T43	572		T45	1550		T47	2727
all_pins[3]	transitions[0x1=>0x0]	78280	1		T37	1708		T43	572		T40	1598
all_pins[4]	values[0x0]	211197	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	105096	1		T37	1708		T43	572		T40	1598
all_pins[4]	transitions[0x0=>0x1]	105082	1		T37	1708		T43	572		T40	1598
all_pins[4]	transitions[0x1=>0x0]	49	1		T266	1		T347	1		T351	4
all_pins[5]	values[0x0]	316230	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	63	1		T266	1		T347	1		T351	4
all_pins[5]	transitions[0x0=>0x1]	25	1		T266	1		T347	1		T351	2
all_pins[5]	transitions[0x1=>0x0]	105	1		T266	2		T274	5		T347	1