Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281	1		T266	7		T274	7		T347	4
all_values[1]	281	1		T266	7		T274	7		T347	4
all_values[2]	281	1		T266	7		T274	7		T347	4
all_values[3]	281	1		T266	7		T274	7		T347	4
all_values[4]	281	1		T266	7		T274	7		T347	4
all_values[5]	281	1		T266	7		T274	7		T347	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	945	1		T266	29		T274	22		T347	12
auto[1]	741	1		T266	13		T274	20		T347	12

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	566	1		T266	13		T274	13		T347	14
auto[1]	1120	1		T266	29		T274	29		T347	10

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1001	1		T266	26		T274	21		T347	20
auto[1]	685	1		T266	16		T274	21		T347	4

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	96	1		T266	4		T347	1		T348	3
all_values[0]	auto[0]	auto[1]	auto[1]	73	1		T266	2		T274	3		T347	2
all_values[0]	auto[1]	auto[0]	auto[1]	57	1		T266	1		T274	1		T347	1
all_values[0]	auto[1]	auto[1]	auto[1]	55	1		T274	3		T349	1		T350	3
all_values[1]	auto[0]	auto[0]	auto[1]	101	1		T266	2		T274	4		T347	1
all_values[1]	auto[0]	auto[1]	auto[1]	58	1		T266	2		T347	2		T349	3
all_values[1]	auto[1]	auto[0]	auto[1]	79	1		T266	2		T349	3		T351	2
all_values[1]	auto[1]	auto[1]	auto[1]	43	1		T266	1		T274	3		T347	1
all_values[2]	auto[0]	auto[0]	auto[0]	79	1		T266	2		T274	1		T347	2
all_values[2]	auto[0]	auto[1]	auto[0]	81	1		T266	2		T274	3		T347	1
all_values[2]	auto[1]	auto[0]	auto[1]	70	1		T274	2		T348	1		T349	2
all_values[2]	auto[1]	auto[1]	auto[1]	51	1		T266	3		T274	1		T347	1
all_values[3]	auto[0]	auto[0]	auto[0]	86	1		T266	3		T274	2		T347	3
all_values[3]	auto[0]	auto[1]	auto[0]	81	1		T266	1		T274	1		T347	1
all_values[3]	auto[1]	auto[0]	auto[1]	56	1		T266	2		T274	3		T349	1
all_values[3]	auto[1]	auto[1]	auto[1]	58	1		T266	1		T274	1		T348	1
all_values[4]	auto[0]	auto[0]	auto[0]	82	1		T347	3		T348	3		T349	4
all_values[4]	auto[0]	auto[0]	auto[1]	23	1		T266	3		T349	1		T351	1
all_values[4]	auto[0]	auto[1]	auto[0]	42	1		T266	1		T274	2		T347	1
all_values[4]	auto[0]	auto[1]	auto[1]	30	1		T350	1		T352	1		T353	1
all_values[4]	auto[1]	auto[0]	auto[1]	49	1		T266	3		T274	3		T348	1
all_values[4]	auto[1]	auto[1]	auto[1]	55	1		T274	2		T349	1		T351	1
all_values[5]	auto[0]	auto[0]	auto[0]	63	1		T266	4		T274	4		T347	1
all_values[5]	auto[0]	auto[0]	auto[1]	25	1		T274	1		T350	1		T352	1
all_values[5]	auto[0]	auto[1]	auto[0]	52	1		T347	2		T349	5		T354	3
all_values[5]	auto[0]	auto[1]	auto[1]	29	1		T351	2		T350	2		T355	2
all_values[5]	auto[1]	auto[0]	auto[1]	79	1		T266	3		T274	1		T351	1
all_values[5]	auto[1]	auto[1]	auto[1]	33	1		T274	1		T347	1		T349	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal