Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	317270	1		T1	2		T2	2		T3	2
all_values[1]	317270	1		T1	2		T2	2		T3	2
all_values[2]	317270	1		T1	2		T2	2		T3	2
all_values[3]	317270	1		T1	2		T2	2		T3	2
all_values[4]	317270	1		T1	2		T2	2		T3	2
all_values[5]	317270	1		T1	2		T2	2		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	640914	1		T1	12		T2	12		T3	12
auto[1]	1262706	1		T40	6168		T44	4904		T41	5592

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	931949	1		T1	7		T2	7		T3	7
auto[1]	971671	1		T1	5		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	317122	1		T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	148	1		T248	4		T249	6		T334	3
all_values[1]	auto[0]	auto[1]	317115	1		T1	2		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	155	1		T248	1		T249	2		T334	4
all_values[2]	auto[0]	auto[0]	1623	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	47	1		T248	1		T249	1		T335	1
all_values[2]	auto[1]	auto[0]	315542	1		T40	1542		T44	1226		T41	1398
all_values[2]	auto[1]	auto[1]	58	1		T249	3		T335	1		T337	3
all_values[3]	auto[0]	auto[0]	1601	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	56	1		T248	2		T334	2		T335	2
all_values[3]	auto[1]	auto[0]	70506	1		T40	1542		T44	613		T41	1398
all_values[3]	auto[1]	auto[1]	245107	1		T44	613		T45	522		T48	118
all_values[4]	auto[0]	auto[0]	1152	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	517	1		T1	1		T2	1		T3	1
all_values[4]	auto[1]	auto[0]	224402	1		T40	1		T44	613		T41	1
all_values[4]	auto[1]	auto[1]	91199	1		T40	1541		T44	613		T41	1397
all_values[5]	auto[0]	auto[0]	1590	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	91	1		T50	1		T51	1		T71	1
all_values[5]	auto[1]	auto[0]	315533	1		T40	1542		T44	1226		T41	1398
all_values[5]	auto[1]	auto[1]	56	1		T248	2		T335	2		T337	1