Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.23 93.90 98.31 92.52 97.14 97.08 98.15


Total tests in report: 1262
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.42 59.42 85.25 85.25 64.55 64.55 49.23 49.23 19.73 19.73 82.35 82.35 81.19 81.19 33.63 33.63 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3362093026
66.97 7.55 86.88 1.63 67.73 3.18 60.68 11.45 43.54 23.81 85.45 3.10 82.22 1.03 42.29 8.66 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3895873125
72.13 5.16 89.95 3.07 73.78 6.05 62.87 2.18 43.54 0.00 91.26 5.81 83.07 0.85 60.48 18.19 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.491300834
76.93 4.79 91.03 1.08 75.94 2.16 66.78 3.92 67.35 23.81 92.48 1.22 83.63 0.56 61.28 0.80 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2533723337
79.91 2.98 92.70 1.68 81.32 5.38 78.77 11.98 67.35 0.00 93.38 0.90 83.82 0.19 62.05 0.77 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.863741936
82.10 2.19 92.98 0.28 82.11 0.79 78.77 0.00 67.35 0.00 93.65 0.28 84.38 0.56 75.49 13.44 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.1227439856
84.29 2.19 93.57 0.60 82.53 0.42 82.72 3.95 76.87 9.52 94.34 0.68 84.48 0.09 75.55 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.4185982397
85.80 1.50 93.74 0.17 83.33 0.80 86.67 3.95 78.23 1.36 95.09 0.75 87.68 3.20 75.83 0.28 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.630002329
87.14 1.34 93.74 0.00 83.55 0.22 86.67 0.00 78.23 0.00 95.09 0.00 94.73 7.06 77.96 2.13 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3361719491
88.43 1.29 93.85 0.11 87.95 4.41 87.79 1.12 79.59 1.36 95.41 0.32 95.20 0.47 79.22 1.26 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2648533537
89.17 0.74 93.97 0.12 88.49 0.53 92.00 4.21 79.59 0.00 95.47 0.06 95.20 0.00 79.50 0.28 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.4245832053
89.84 0.67 93.97 0.00 88.67 0.18 92.00 0.00 79.59 0.00 95.47 0.00 95.20 0.00 84.00 4.50 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2305450158
90.34 0.50 94.07 0.11 88.92 0.25 92.31 0.31 82.31 2.72 95.56 0.09 95.20 0.00 84.03 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.409394218
90.84 0.49 94.13 0.05 89.28 0.36 92.37 0.06 82.31 0.00 95.66 0.11 95.20 0.00 86.90 2.87 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2587333040
91.26 0.42 94.13 0.00 89.29 0.01 93.24 0.87 84.35 2.04 95.66 0.00 95.20 0.00 86.93 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.175086976
91.64 0.38 94.23 0.10 89.51 0.22 95.04 1.80 84.35 0.00 95.66 0.00 95.20 0.00 87.48 0.55 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.2507992165
91.89 0.25 94.37 0.14 89.59 0.09 95.55 0.51 85.03 0.68 95.83 0.17 95.20 0.00 87.67 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2162491274
92.13 0.23 94.48 0.12 89.60 0.01 95.55 0.00 85.03 0.00 95.83 0.00 95.20 0.00 89.18 1.51 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2065355660
92.36 0.23 94.51 0.03 89.63 0.03 95.68 0.13 86.39 1.36 95.92 0.09 95.20 0.00 89.18 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3056425513
92.58 0.22 94.51 0.00 89.69 0.06 95.74 0.06 87.76 1.36 95.94 0.02 95.20 0.00 89.21 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.4253871373
92.79 0.21 94.51 0.00 89.72 0.03 95.81 0.06 87.76 0.00 95.94 0.00 96.14 0.94 89.67 0.46 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.4170086698
92.99 0.20 94.59 0.08 90.33 0.61 96.26 0.45 87.76 0.00 95.94 0.00 96.14 0.00 89.95 0.28 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.4286015556
93.19 0.19 94.59 0.00 90.33 0.00 96.26 0.00 89.12 1.36 95.94 0.00 96.14 0.00 89.95 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.3392356792
93.38 0.19 94.72 0.12 90.73 0.40 96.39 0.13 89.12 0.00 96.13 0.19 96.33 0.19 90.26 0.31 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2932207424
93.57 0.19 94.72 0.01 90.79 0.07 96.42 0.03 89.12 0.00 96.15 0.02 96.33 0.00 91.46 1.20 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1340615893
93.76 0.19 94.72 0.00 91.06 0.27 96.42 0.00 89.12 0.00 96.15 0.00 96.33 0.00 92.51 1.05 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3979719508
93.94 0.18 94.80 0.07 91.22 0.16 96.48 0.06 89.12 0.00 96.32 0.17 96.33 0.00 93.31 0.80 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.216752774
94.10 0.16 94.85 0.05 91.33 0.11 96.84 0.35 89.12 0.00 96.45 0.13 96.33 0.00 93.77 0.46 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.530120660
94.24 0.14 94.87 0.02 91.34 0.01 97.00 0.16 89.80 0.68 96.52 0.06 96.33 0.00 93.83 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2364228052
94.37 0.13 94.87 0.00 91.43 0.09 97.00 0.00 90.48 0.68 96.52 0.00 96.43 0.09 93.87 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.637119489
94.49 0.12 94.90 0.04 92.15 0.72 97.00 0.00 90.48 0.00 96.52 0.00 96.43 0.00 93.96 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3994668390
94.61 0.12 94.90 0.00 92.16 0.01 97.12 0.13 91.16 0.68 96.52 0.00 96.43 0.00 93.96 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.4032608815
94.71 0.11 94.91 0.01 92.32 0.15 97.46 0.34 91.16 0.00 96.60 0.09 96.52 0.09 94.02 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3804355994
94.81 0.10 94.91 0.00 92.32 0.00 97.46 0.00 91.84 0.68 96.60 0.00 96.52 0.00 94.05 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.3847988118
94.92 0.10 94.92 0.01 92.32 0.00 97.46 0.00 92.52 0.68 96.62 0.02 96.52 0.00 94.05 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1264861185
94.99 0.08 94.94 0.02 92.36 0.05 97.51 0.05 92.52 0.00 96.62 0.00 96.52 0.00 94.48 0.43 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.2404429411
95.06 0.07 94.94 0.00 92.53 0.17 97.51 0.00 92.52 0.00 96.62 0.00 96.52 0.00 94.79 0.31 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.3835561260
95.12 0.06 94.94 0.00 92.54 0.01 97.51 0.00 92.52 0.00 96.62 0.00 96.71 0.19 95.01 0.22 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.3125585898
95.18 0.06 94.95 0.01 92.59 0.05 97.77 0.26 92.52 0.00 96.67 0.04 96.71 0.00 95.04 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.1255377700
95.23 0.05 94.95 0.00 92.59 0.00 97.77 0.00 92.52 0.00 96.67 0.00 97.08 0.38 95.04 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1418661720
95.28 0.05 95.03 0.08 92.73 0.14 97.77 0.00 92.52 0.00 96.79 0.13 97.08 0.00 95.04 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1402244059
95.33 0.05 95.03 0.00 92.77 0.04 97.83 0.06 92.52 0.00 96.79 0.00 97.08 0.00 95.25 0.22 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.134259812
95.37 0.04 95.03 0.00 92.78 0.01 97.83 0.00 92.52 0.00 96.79 0.00 97.08 0.00 95.53 0.28 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.316248744
95.40 0.04 95.04 0.01 92.87 0.09 97.86 0.03 92.52 0.00 96.84 0.04 97.08 0.00 95.62 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.32293147
95.44 0.04 95.04 0.00 92.99 0.12 97.90 0.03 92.52 0.00 96.84 0.00 97.08 0.00 95.72 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.2450273371
95.47 0.04 95.04 0.00 92.99 0.00 97.90 0.00 92.52 0.00 96.84 0.00 97.08 0.00 95.96 0.25 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1982556426
95.50 0.03 95.05 0.01 93.05 0.06 97.90 0.00 92.52 0.00 96.86 0.02 97.08 0.00 96.09 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3720442630
95.53 0.03 95.09 0.04 93.09 0.04 97.93 0.03 92.52 0.00 96.90 0.04 97.08 0.00 96.12 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.682786543
95.56 0.03 95.09 0.00 93.09 0.00 97.93 0.00 92.52 0.00 96.90 0.00 97.08 0.00 96.30 0.18 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3598378106
95.58 0.03 95.15 0.06 93.12 0.03 97.94 0.02 92.52 0.00 96.94 0.04 97.08 0.00 96.33 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3480679517
95.61 0.02 95.15 0.00 93.13 0.01 97.94 0.00 92.52 0.00 96.94 0.00 97.08 0.00 96.49 0.15 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.2474078801
95.63 0.02 95.17 0.02 93.15 0.03 97.94 0.00 92.52 0.00 97.03 0.09 97.08 0.00 96.52 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1949928972
95.65 0.02 95.17 0.00 93.18 0.03 97.94 0.00 92.52 0.00 97.03 0.00 97.08 0.00 96.64 0.12 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.4211229620
95.67 0.02 95.21 0.04 93.18 0.00 97.99 0.05 92.52 0.00 97.03 0.00 97.08 0.00 96.67 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.3205674256
95.69 0.02 95.21 0.00 93.20 0.02 97.99 0.00 92.52 0.00 97.03 0.00 97.08 0.00 96.76 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.809211781
95.70 0.02 95.22 0.01 93.22 0.02 97.99 0.00 92.52 0.00 97.05 0.02 97.08 0.00 96.82 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.4075997388
95.72 0.02 95.22 0.00 93.30 0.08 97.99 0.00 92.52 0.00 97.05 0.00 97.08 0.00 96.86 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2659009147
95.73 0.01 95.22 0.00 93.40 0.10 97.99 0.00 92.52 0.00 97.05 0.00 97.08 0.00 96.86 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.138644884
95.75 0.01 95.23 0.01 93.42 0.02 97.99 0.00 92.52 0.00 97.09 0.04 97.08 0.00 96.89 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1252399595
95.76 0.01 95.23 0.00 93.42 0.00 97.99 0.00 92.52 0.00 97.09 0.00 97.08 0.00 96.98 0.09 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1116015565
95.77 0.01 95.23 0.00 93.44 0.02 97.99 0.00 92.52 0.00 97.09 0.00 97.08 0.00 97.04 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.1891074419
95.78 0.01 95.23 0.00 93.44 0.00 98.04 0.05 92.52 0.00 97.09 0.00 97.08 0.00 97.07 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.3821611098
95.79 0.01 95.23 0.00 93.49 0.05 98.04 0.00 92.52 0.00 97.09 0.00 97.08 0.00 97.10 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.3817337002
95.80 0.01 95.23 0.00 93.50 0.01 98.10 0.06 92.52 0.00 97.09 0.00 97.08 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1077648686
95.81 0.01 95.23 0.00 93.51 0.01 98.17 0.06 92.52 0.00 97.09 0.00 97.08 0.00 97.10 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.3435663367
95.83 0.01 95.23 0.00 93.52 0.01 98.17 0.00 92.52 0.00 97.09 0.00 97.08 0.00 97.16 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.4219179839
95.84 0.01 95.23 0.00 93.53 0.01 98.17 0.00 92.52 0.00 97.09 0.00 97.08 0.00 97.23 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2685033651
95.85 0.01 95.23 0.00 93.57 0.05 98.17 0.00 92.52 0.00 97.12 0.02 97.08 0.00 97.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1814272410
95.85 0.01 95.23 0.00 93.57 0.00 98.23 0.06 92.52 0.00 97.12 0.00 97.08 0.00 97.23 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1415210116
95.86 0.01 95.23 0.00 93.57 0.00 98.23 0.00 92.52 0.00 97.12 0.00 97.08 0.00 97.29 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.548096241
95.87 0.01 95.23 0.00 93.57 0.00 98.23 0.00 92.52 0.00 97.12 0.00 97.08 0.00 97.35 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.2634148547
95.88 0.01 95.23 0.00 93.57 0.00 98.23 0.00 92.52 0.00 97.12 0.00 97.08 0.00 97.41 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3194069758
95.89 0.01 95.23 0.00 93.57 0.00 98.23 0.00 92.52 0.00 97.12 0.00 97.08 0.00 97.47 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.343630472
95.90 0.01 95.23 0.00 93.57 0.00 98.23 0.00 92.52 0.00 97.12 0.00 97.08 0.00 97.53 0.06 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.3491298095
95.91 0.01 95.23 0.00 93.62 0.05 98.23 0.00 92.52 0.00 97.12 0.00 97.08 0.00 97.53 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2430865839
95.91 0.01 95.23 0.00 93.62 0.00 98.25 0.02 92.52 0.00 97.12 0.00 97.08 0.00 97.56 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1219546881
95.92 0.01 95.23 0.00 93.63 0.01 98.28 0.03 92.52 0.00 97.12 0.00 97.08 0.00 97.56 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.160713910
95.92 0.01 95.23 0.00 93.65 0.02 98.28 0.00 92.52 0.00 97.14 0.02 97.08 0.00 97.56 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3455453286
95.93 0.01 95.23 0.00 93.66 0.01 98.28 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.60 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.2199860745
95.94 0.01 95.23 0.00 93.67 0.01 98.28 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.63 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.4081466298
95.94 0.01 95.23 0.00 93.68 0.01 98.28 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.66 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.3127936353
95.95 0.01 95.23 0.00 93.68 0.00 98.31 0.03 92.52 0.00 97.14 0.00 97.08 0.00 97.66 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.985017790
95.95 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.69 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.113780352
95.95 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.72 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.899713353
95.96 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.75 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2590367657
95.96 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.78 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.3549474730
95.97 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.81 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.4236962439
95.97 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.84 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.2638023456
95.98 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.87 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3450675827
95.98 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.90 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2266905168
95.99 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.93 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.859773102
95.99 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 97.97 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.2299140861
95.99 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.00 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.1729157293
96.00 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.03 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.2778364161
96.00 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.06 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.1724027245
96.01 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.09 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.2632142554
96.01 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.12 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.2266619016
96.02 0.01 95.23 0.00 93.68 0.00 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.03 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.4175095031
96.02 0.01 95.23 0.00 93.71 0.03 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3077112738
96.02 0.01 95.23 0.00 93.73 0.03 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1218174269
96.03 0.01 95.23 0.00 93.76 0.03 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.2274440021
96.03 0.01 95.23 0.00 93.79 0.03 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.3905111908
96.03 0.01 95.23 0.00 93.81 0.02 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3860038174
96.04 0.01 95.23 0.00 93.82 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.39185148
96.04 0.01 95.23 0.00 93.83 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1092895315
96.04 0.01 95.23 0.00 93.84 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2519837421
96.04 0.01 95.23 0.00 93.85 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.642392304
96.04 0.01 95.23 0.00 93.86 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.787669983
96.04 0.01 95.23 0.00 93.87 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.3781485971
96.04 0.01 95.23 0.00 93.88 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2682229864
96.05 0.01 95.23 0.00 93.89 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.2417288269
96.05 0.01 95.23 0.00 93.90 0.01 98.31 0.00 92.52 0.00 97.14 0.00 97.08 0.00 98.15 0.00 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.359723464

Tests that do not contribute to grading

Name
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1304079523
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3371068114
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1204968092
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.46590317
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.389499450
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.1713893013
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.915332006
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3197972301
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2870321105
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2354227168
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2853675495
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3533939725
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2130145065
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2195842778
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3295583107
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2041517744
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.3192048414
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.2327695477
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.173832673
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2423153126
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3100476999
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.197097384
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1110383327
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3491210556
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.648117330
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.1394936726
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1362316168
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3404072719
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3579496591
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4189737833
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2514165084
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2546107588
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.2001207803
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2031874952
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2542925421
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1918366455
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.804034057
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1197052049
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.459630617
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.4057512609
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.1948702166
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1950611755
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2729456039
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3309031454
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.797844386
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.2852661661
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.2380738126
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3568794644
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.482516569
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1700683310
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.1689616567
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.4198713970
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1072640685
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2304277928
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.688043910
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.305374076
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2202624615
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3925661791
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3671354568
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.257558582
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.4194439029
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.59482063
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.1889520218
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3608711239
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2363893140
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1514026260
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1201113340
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.431695593
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1964929622
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2495704560
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.589649198
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.4007853895
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.4019694420
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.3120860467
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1497715045
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/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.1782654776
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/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.358754576
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1134793832
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1480488141
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3677163002
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/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.425983230
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.2116699759
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.4082141632
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/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.652974040
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.1061796758
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.3165450070
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.3565644114
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.768116736
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2079507650
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.3082515454
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3758492319
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.869914228
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.373611504
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.750983626
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.4148219447
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.784533504
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3527310474
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.95895117
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2571718938
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.2608411830
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3657930383
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.365428682
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2870584351
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.439308444
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.2071299833
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.1949814904
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.4214820563
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3161144689
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.3179496362
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2609158310
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3078997009
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.1052712491
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3777150823
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1714360636
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.433871737
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.3045102601
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1879029771
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.357875932
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3729602785
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3672297100
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1843864330
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.852808787
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1231280465
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3561789001
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.3529245202
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.897384082
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1048661434
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1474196056
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.2252233713
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3657724887
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.1966922382
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.1114818408
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.2208973073
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.3499086740
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3766289429
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.2177101261
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2661269279
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2546933966
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1513770976
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.417246480
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2600654740
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1881202566
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.1627848223
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.1489879345
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1109647348
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3355648384
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2220672717
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1369491648
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.4040654632
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.147568231
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1782821853
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.1920923077
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3911706750
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.3384305547
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3434509366
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1766176926
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.3430506013
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2366557825
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.506664300
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.992970446
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.959723924
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1219361876
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.321201040
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.1079783068
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.340592615



Total test records in report: 1262
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2952283265 Sep 24 05:46:51 PM UTC 24 Sep 24 05:47:10 PM UTC 24 61928800 ps
T2 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.3526670049 Sep 24 05:46:52 PM UTC 24 Sep 24 05:47:11 PM UTC 24 44839900 ps
T3 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3362093026 Sep 24 05:46:47 PM UTC 24 Sep 24 05:47:17 PM UTC 24 1800077800 ps
T4 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.286768877 Sep 24 05:46:45 PM UTC 24 Sep 24 05:47:18 PM UTC 24 45718100 ps
T16 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.2507992165 Sep 24 05:50:21 PM UTC 24 Sep 24 05:50:48 PM UTC 24 89442500 ps
T17 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2651971941 Sep 24 05:46:53 PM UTC 24 Sep 24 05:47:23 PM UTC 24 42346200 ps
T5 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.1168527572 Sep 24 05:47:06 PM UTC 24 Sep 24 05:47:23 PM UTC 24 29466100 ps
T18 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.1189309751 Sep 24 05:46:53 PM UTC 24 Sep 24 05:47:23 PM UTC 24 31072100 ps
T19 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.1415210116 Sep 24 05:47:05 PM UTC 24 Sep 24 05:47:26 PM UTC 24 24445600 ps
T10 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.152837606 Sep 24 05:46:44 PM UTC 24 Sep 24 05:47:27 PM UTC 24 19319900 ps
T22 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.666371784 Sep 24 05:47:01 PM UTC 24 Sep 24 05:47:28 PM UTC 24 20028200 ps
T11 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3804355994 Sep 24 05:47:10 PM UTC 24 Sep 24 05:47:31 PM UTC 24 14427500 ps
T6 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.2598859167 Sep 24 05:47:02 PM UTC 24 Sep 24 05:47:32 PM UTC 24 13035300 ps
T12 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.2610838892 Sep 24 05:47:09 PM UTC 24 Sep 24 05:47:34 PM UTC 24 44643000 ps
T7 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1254793278 Sep 24 05:47:14 PM UTC 24 Sep 24 05:47:34 PM UTC 24 135310000 ps
T8 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3895873125 Sep 24 05:47:06 PM UTC 24 Sep 24 05:47:35 PM UTC 24 164882500 ps
T31 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.3549474730 Sep 24 05:47:10 PM UTC 24 Sep 24 05:47:37 PM UTC 24 67525200 ps
T32 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.32293147 Sep 24 05:47:09 PM UTC 24 Sep 24 05:47:39 PM UTC 24 775466100 ps
T37 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.863741936 Sep 24 05:47:01 PM UTC 24 Sep 24 05:47:42 PM UTC 24 73087700 ps
T38 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.285605622 Sep 24 05:47:01 PM UTC 24 Sep 24 05:47:42 PM UTC 24 45460100 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1949928972 Sep 24 05:47:18 PM UTC 24 Sep 24 05:47:44 PM UTC 24 17690500 ps
T49 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.4245832053 Sep 24 05:47:05 PM UTC 24 Sep 24 05:47:47 PM UTC 24 97320300 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2748595770 Sep 24 05:47:22 PM UTC 24 Sep 24 05:47:50 PM UTC 24 42700800 ps
T26 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1219546881 Sep 24 05:47:01 PM UTC 24 Sep 24 05:47:50 PM UTC 24 154144500 ps
T55 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.601284870 Sep 24 05:46:45 PM UTC 24 Sep 24 05:47:57 PM UTC 24 1685368100 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.1276676682 Sep 24 05:47:25 PM UTC 24 Sep 24 05:48:06 PM UTC 24 86940800 ps
T33 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.3665694341 Sep 24 05:46:50 PM UTC 24 Sep 24 05:48:09 PM UTC 24 5929520400 ps
T36 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.4135092833 Sep 24 05:46:45 PM UTC 24 Sep 24 05:48:10 PM UTC 24 136038400 ps
T50 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.134259812 Sep 24 05:47:07 PM UTC 24 Sep 24 05:48:11 PM UTC 24 2354761900 ps
T43 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3194069758 Sep 24 05:47:03 PM UTC 24 Sep 24 05:48:11 PM UTC 24 326109400 ps
T57 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.1559674475 Sep 24 05:47:21 PM UTC 24 Sep 24 05:48:11 PM UTC 24 39577200 ps
T52 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.971943863 Sep 24 05:47:39 PM UTC 24 Sep 24 05:48:13 PM UTC 24 306803400 ps
T34 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2533723337 Sep 24 05:46:50 PM UTC 24 Sep 24 05:48:15 PM UTC 24 994033800 ps
T68 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.46838627 Sep 24 05:47:24 PM UTC 24 Sep 24 05:48:15 PM UTC 24 19601100 ps
T40 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1218174269 Sep 24 05:47:00 PM UTC 24 Sep 24 05:48:22 PM UTC 24 4913682700 ps
T66 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.4211760660 Sep 24 05:46:53 PM UTC 24 Sep 24 05:48:29 PM UTC 24 2493805000 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.3112501217 Sep 24 05:46:53 PM UTC 24 Sep 24 05:48:32 PM UTC 24 2546307200 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.526399833 Sep 24 05:47:19 PM UTC 24 Sep 24 05:48:32 PM UTC 24 109477800 ps
T103 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.4237788265 Sep 24 05:47:25 PM UTC 24 Sep 24 05:48:46 PM UTC 24 56602100 ps
T127 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.1264564267 Sep 24 05:48:14 PM UTC 24 Sep 24 05:48:51 PM UTC 24 32555100 ps
T70 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2815781916 Sep 24 05:46:52 PM UTC 24 Sep 24 05:48:56 PM UTC 24 592008400 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3547253859 Sep 24 05:48:10 PM UTC 24 Sep 24 05:48:59 PM UTC 24 56408700 ps
T71 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2648533537 Sep 24 05:46:53 PM UTC 24 Sep 24 05:49:05 PM UTC 24 2444930000 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2932207424 Sep 24 05:47:48 PM UTC 24 Sep 24 05:49:08 PM UTC 24 7236976700 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2519837421 Sep 24 05:46:45 PM UTC 24 Sep 24 05:49:17 PM UTC 24 107951000 ps
T202 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.245670043 Sep 24 05:48:57 PM UTC 24 Sep 24 05:49:32 PM UTC 24 821037300 ps
T39 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.3627922648 Sep 24 05:49:00 PM UTC 24 Sep 24 05:49:35 PM UTC 24 34500100 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.175086976 Sep 24 05:46:46 PM UTC 24 Sep 24 05:49:40 PM UTC 24 41331700 ps
T82 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.642392304 Sep 24 05:46:53 PM UTC 24 Sep 24 05:49:47 PM UTC 24 3627641300 ps
T44 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3575828828 Sep 24 05:47:00 PM UTC 24 Sep 24 05:49:48 PM UTC 24 2788213300 ps
T60 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.409394218 Sep 24 05:47:50 PM UTC 24 Sep 24 05:49:49 PM UTC 24 1703749500 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3450675827 Sep 24 05:49:06 PM UTC 24 Sep 24 05:49:51 PM UTC 24 80494800 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2587333040 Sep 24 05:46:59 PM UTC 24 Sep 24 05:50:30 PM UTC 24 2440773100 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.3405433477 Sep 24 05:46:50 PM UTC 24 Sep 24 05:49:53 PM UTC 24 10388801900 ps
T75 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.4236962439 Sep 24 05:49:18 PM UTC 24 Sep 24 05:49:56 PM UTC 24 26049300 ps
T154 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.3617589372 Sep 24 05:48:12 PM UTC 24 Sep 24 05:49:58 PM UTC 24 3325390200 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.2380982131 Sep 24 05:47:59 PM UTC 24 Sep 24 05:50:00 PM UTC 24 2380434300 ps
T155 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.2404429411 Sep 24 05:49:10 PM UTC 24 Sep 24 05:50:01 PM UTC 24 84910700 ps
T260 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.1965633313 Sep 24 05:48:12 PM UTC 24 Sep 24 05:50:03 PM UTC 24 3231574300 ps
T41 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.1355909589 Sep 24 05:48:33 PM UTC 24 Sep 24 05:50:10 PM UTC 24 1898112100 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.3835561260 Sep 24 05:46:53 PM UTC 24 Sep 24 05:50:11 PM UTC 24 1228097500 ps
T24 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.961601751 Sep 24 05:49:48 PM UTC 24 Sep 24 05:50:13 PM UTC 24 23906900 ps
T9 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.787669983 Sep 24 05:49:51 PM UTC 24 Sep 24 05:50:13 PM UTC 24 15242800 ps
T27 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3720442630 Sep 24 05:47:27 PM UTC 24 Sep 24 05:50:20 PM UTC 24 6611345300 ps
T20 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2805169688 Sep 24 05:49:49 PM UTC 24 Sep 24 05:50:21 PM UTC 24 111858100 ps
T193 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.4075997388 Sep 24 05:49:59 PM UTC 24 Sep 24 05:50:21 PM UTC 24 15251100 ps
T42 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.985364731 Sep 24 05:47:00 PM UTC 24 Sep 24 05:50:22 PM UTC 24 18754347900 ps
T243 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.702347493 Sep 24 05:49:49 PM UTC 24 Sep 24 05:50:29 PM UTC 24 81278100 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.2274440021 Sep 24 05:50:01 PM UTC 24 Sep 24 05:50:30 PM UTC 24 32701500 ps
T244 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.526616490 Sep 24 05:50:02 PM UTC 24 Sep 24 05:50:31 PM UTC 24 19625100 ps
T117 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.28056066 Sep 24 05:48:12 PM UTC 24 Sep 24 05:50:31 PM UTC 24 2153944800 ps
T174 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.1255377700 Sep 24 05:50:11 PM UTC 24 Sep 24 05:50:33 PM UTC 24 30732700 ps
T156 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.4226095242 Sep 24 05:49:55 PM UTC 24 Sep 24 05:50:37 PM UTC 24 327427300 ps
T173 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.2638023456 Sep 24 05:50:12 PM UTC 24 Sep 24 05:50:37 PM UTC 24 15716700 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1168033254 Sep 24 05:47:35 PM UTC 24 Sep 24 05:50:38 PM UTC 24 143820000 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.3781485971 Sep 24 05:49:58 PM UTC 24 Sep 24 05:50:40 PM UTC 24 857843900 ps
T219 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.3591817206 Sep 24 05:47:24 PM UTC 24 Sep 24 05:50:46 PM UTC 24 35306000 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.2484129477 Sep 24 05:46:44 PM UTC 24 Sep 24 05:50:46 PM UTC 24 69893100 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.3027683799 Sep 24 05:48:17 PM UTC 24 Sep 24 05:50:46 PM UTC 24 567587000 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.1277199260 Sep 24 05:50:22 PM UTC 24 Sep 24 05:50:58 PM UTC 24 16466700 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1614619594 Sep 24 05:47:18 PM UTC 24 Sep 24 05:50:48 PM UTC 24 10012213900 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.1336240752 Sep 24 05:50:13 PM UTC 24 Sep 24 05:50:57 PM UTC 24 27328700 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.3260132340 Sep 24 05:50:30 PM UTC 24 Sep 24 05:51:00 PM UTC 24 51741700 ps
T45 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2256369728 Sep 24 05:48:33 PM UTC 24 Sep 24 05:51:01 PM UTC 24 3657603400 ps
T118 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.97757740 Sep 24 05:46:53 PM UTC 24 Sep 24 05:51:04 PM UTC 24 1862623200 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.31578190 Sep 24 05:49:36 PM UTC 24 Sep 24 05:51:04 PM UTC 24 5733453500 ps
T48 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.216752774 Sep 24 05:47:00 PM UTC 24 Sep 24 05:51:08 PM UTC 24 31894121800 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.956506387 Sep 24 05:47:52 PM UTC 24 Sep 24 05:51:18 PM UTC 24 2182215900 ps
T56 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1814272410 Sep 24 05:50:47 PM UTC 24 Sep 24 05:51:20 PM UTC 24 926362300 ps
T192 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.3806384170 Sep 24 05:50:31 PM UTC 24 Sep 24 05:51:24 PM UTC 24 93735300 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1774721464 Sep 24 05:48:12 PM UTC 24 Sep 24 05:51:36 PM UTC 24 19767257900 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.1359890877 Sep 24 05:48:17 PM UTC 24 Sep 24 05:51:46 PM UTC 24 3041964600 ps
T119 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.1067783037 Sep 24 05:47:29 PM UTC 24 Sep 24 05:51:47 PM UTC 24 3077290200 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.216284972 Sep 24 05:51:09 PM UTC 24 Sep 24 05:51:47 PM UTC 24 58926600 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.2572096834 Sep 24 05:48:30 PM UTC 24 Sep 24 05:51:52 PM UTC 24 22048259400 ps
T108 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.682786543 Sep 24 05:50:13 PM UTC 24 Sep 24 05:52:03 PM UTC 24 10034920500 ps
T28 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.1227439856 Sep 24 05:46:47 PM UTC 24 Sep 24 05:52:09 PM UTC 24 27923694500 ps
T120 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.3605073807 Sep 24 05:50:32 PM UTC 24 Sep 24 05:52:13 PM UTC 24 2798715700 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3060999564 Sep 24 05:48:23 PM UTC 24 Sep 24 05:52:21 PM UTC 24 804921000 ps
T29 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1687897851 Sep 24 05:47:28 PM UTC 24 Sep 24 05:52:21 PM UTC 24 3632178200 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.137476206 Sep 24 05:48:46 PM UTC 24 Sep 24 05:52:22 PM UTC 24 6220040600 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.1986713145 Sep 24 05:51:47 PM UTC 24 Sep 24 05:52:22 PM UTC 24 18416800 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.1267335614 Sep 24 05:51:25 PM UTC 24 Sep 24 05:52:30 PM UTC 24 1127042000 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2306027351 Sep 24 05:50:59 PM UTC 24 Sep 24 05:52:30 PM UTC 24 3061122200 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.3294383121 Sep 24 05:51:04 PM UTC 24 Sep 24 05:52:59 PM UTC 24 2536990600 ps
T61 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.2597156408 Sep 24 05:51:01 PM UTC 24 Sep 24 05:53:02 PM UTC 24 2562509700 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.626996382 Sep 24 05:51:37 PM UTC 24 Sep 24 05:53:17 PM UTC 24 1785716000 ps
T35 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.591602483 Sep 24 05:50:31 PM UTC 24 Sep 24 05:53:27 PM UTC 24 2918833300 ps
T263 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.3419525404 Sep 24 05:52:32 PM UTC 24 Sep 24 05:53:30 PM UTC 24 105307600 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.1430605081 Sep 24 05:52:31 PM UTC 24 Sep 24 05:53:33 PM UTC 24 44695600 ps
T91 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.551077392 Sep 24 05:50:39 PM UTC 24 Sep 24 05:53:34 PM UTC 24 78592800 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.1721317647 Sep 24 05:52:21 PM UTC 24 Sep 24 05:53:35 PM UTC 24 8028198300 ps
T264 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2578636364 Sep 24 05:52:32 PM UTC 24 Sep 24 05:53:39 PM UTC 24 80299100 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3245722513 Sep 24 05:53:00 PM UTC 24 Sep 24 05:53:44 PM UTC 24 90844700 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.2269938862 Sep 24 05:50:21 PM UTC 24 Sep 24 05:53:48 PM UTC 24 38598500 ps
T21 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.2236677233 Sep 24 05:53:35 PM UTC 24 Sep 24 05:53:54 PM UTC 24 124770100 ps
T30 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.1009696019 Sep 24 05:47:37 PM UTC 24 Sep 24 05:53:55 PM UTC 24 15867218200 ps
T25 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.3808467968 Sep 24 05:53:30 PM UTC 24 Sep 24 05:54:00 PM UTC 24 16089200 ps
T23 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.1402244059 Sep 24 05:53:36 PM UTC 24 Sep 24 05:54:05 PM UTC 24 23801500 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.752957548 Sep 24 05:51:02 PM UTC 24 Sep 24 05:54:15 PM UTC 24 11344721900 ps
T227 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.495331339 Sep 24 05:51:19 PM UTC 24 Sep 24 05:54:17 PM UTC 24 8925102000 ps
T238 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.1704146909 Sep 24 05:51:48 PM UTC 24 Sep 24 05:54:19 PM UTC 24 1393268400 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.219612467 Sep 24 05:53:35 PM UTC 24 Sep 24 05:54:21 PM UTC 24 65993800 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.4221239487 Sep 24 05:53:55 PM UTC 24 Sep 24 05:54:21 PM UTC 24 15180900 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.138644884 Sep 24 05:53:45 PM UTC 24 Sep 24 05:54:24 PM UTC 24 765357600 ps
T218 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.979905355 Sep 24 05:53:57 PM UTC 24 Sep 24 05:54:24 PM UTC 24 93099700 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3629317574 Sep 24 05:54:06 PM UTC 24 Sep 24 05:54:24 PM UTC 24 15072800 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.514480531 Sep 24 05:46:45 PM UTC 24 Sep 24 05:54:26 PM UTC 24 1374052800 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.2188212943 Sep 24 05:53:40 PM UTC 24 Sep 24 05:54:26 PM UTC 24 477136300 ps
T85 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3569575202 Sep 24 05:54:16 PM UTC 24 Sep 24 05:54:37 PM UTC 24 26051700 ps
T62 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3916836734 Sep 24 05:47:32 PM UTC 24 Sep 24 05:54:37 PM UTC 24 1396356400 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.3444936817 Sep 24 05:54:20 PM UTC 24 Sep 24 05:54:42 PM UTC 24 414738500 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.1281148589 Sep 24 05:52:04 PM UTC 24 Sep 24 05:54:57 PM UTC 24 1450748800 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3419356635 Sep 24 05:54:25 PM UTC 24 Sep 24 05:54:58 PM UTC 24 36534300 ps
T304 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2475859283 Sep 24 05:54:19 PM UTC 24 Sep 24 05:55:03 PM UTC 24 65753200 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.3986963636 Sep 24 05:46:53 PM UTC 24 Sep 24 05:55:07 PM UTC 24 7293874500 ps
T169 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.530120660 Sep 24 05:53:17 PM UTC 24 Sep 24 05:55:11 PM UTC 24 1897757300 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.1434833700 Sep 24 05:54:23 PM UTC 24 Sep 24 05:55:11 PM UTC 24 56552100 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.3785872129 Sep 24 05:50:32 PM UTC 24 Sep 24 05:55:27 PM UTC 24 238176800 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3833657648 Sep 24 05:51:21 PM UTC 24 Sep 24 05:55:35 PM UTC 24 6461169500 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.2634148547 Sep 24 05:46:59 PM UTC 24 Sep 24 05:55:41 PM UTC 24 4152811900 ps
T63 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.4035070125 Sep 24 05:46:46 PM UTC 24 Sep 24 05:55:42 PM UTC 24 3521792900 ps
T67 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.2653692689 Sep 24 05:55:08 PM UTC 24 Sep 24 05:55:46 PM UTC 24 933725200 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.4001754285 Sep 24 05:51:48 PM UTC 24 Sep 24 05:55:55 PM UTC 24 10096348700 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.711811764 Sep 24 05:54:18 PM UTC 24 Sep 24 05:56:06 PM UTC 24 10015682100 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2452813865 Sep 24 05:52:14 PM UTC 24 Sep 24 05:56:10 PM UTC 24 7361422700 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.809211781 Sep 24 05:50:46 PM UTC 24 Sep 24 05:56:31 PM UTC 24 9909855000 ps
T295 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1487852928 Sep 24 05:52:22 PM UTC 24 Sep 24 05:56:35 PM UTC 24 27644557100 ps
T294 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1426939786 Sep 24 05:54:38 PM UTC 24 Sep 24 05:56:36 PM UTC 24 3965471300 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.1417261459 Sep 24 05:52:22 PM UTC 24 Sep 24 05:56:44 PM UTC 24 4602762700 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.496835880 Sep 24 05:56:10 PM UTC 24 Sep 24 05:56:45 PM UTC 24 76321400 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.3164607452 Sep 24 05:48:07 PM UTC 24 Sep 24 05:56:55 PM UTC 24 20689552200 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3682744448 Sep 24 05:54:21 PM UTC 24 Sep 24 05:56:56 PM UTC 24 77140400 ps
T157 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.71836350 Sep 24 05:55:42 PM UTC 24 Sep 24 05:57:03 PM UTC 24 23913697100 ps
T79 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.3392356792 Sep 24 05:55:42 PM UTC 24 Sep 24 05:57:06 PM UTC 24 1712999600 ps
T265 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.959781890 Sep 24 05:54:25 PM UTC 24 Sep 24 05:57:25 PM UTC 24 122953300 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3977577110 Sep 24 05:56:45 PM UTC 24 Sep 24 05:57:26 PM UTC 24 24022100 ps
T240 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.606927269 Sep 24 05:54:27 PM UTC 24 Sep 24 05:57:34 PM UTC 24 2921582200 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.83382820 Sep 24 05:56:37 PM UTC 24 Sep 24 05:57:39 PM UTC 24 626332700 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.446714774 Sep 24 05:54:57 PM UTC 24 Sep 24 05:58:05 PM UTC 24 149513500 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1663318011 Sep 24 05:56:44 PM UTC 24 Sep 24 05:58:06 PM UTC 24 1737582700 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.683957779 Sep 24 05:55:55 PM UTC 24 Sep 24 05:58:26 PM UTC 24 8390875400 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.442097301 Sep 24 05:58:08 PM UTC 24 Sep 24 05:58:35 PM UTC 24 62064000 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1717266197 Sep 24 05:55:47 PM UTC 24 Sep 24 05:59:00 PM UTC 24 7504271500 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.3656763318 Sep 24 05:57:35 PM UTC 24 Sep 24 05:59:17 PM UTC 24 4205491500 ps
T47 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.2450273371 Sep 24 05:57:26 PM UTC 24 Sep 24 05:59:19 PM UTC 24 456089700 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.1891074419 Sep 24 05:58:28 PM UTC 24 Sep 24 05:59:22 PM UTC 24 30781800 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.153880060 Sep 24 05:56:56 PM UTC 24 Sep 24 05:59:35 PM UTC 24 1012017300 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2563557008 Sep 24 05:58:36 PM UTC 24 Sep 24 05:59:38 PM UTC 24 40280500 ps
T302 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.2523773560 Sep 24 05:48:30 PM UTC 24 Sep 24 05:59:45 PM UTC 24 15348183900 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2168468444 Sep 24 05:56:32 PM UTC 24 Sep 24 05:59:47 PM UTC 24 738973800 ps
T158 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.2932800093 Sep 24 05:59:01 PM UTC 24 Sep 24 05:59:49 PM UTC 24 63887600 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.400315836 Sep 24 05:56:36 PM UTC 24 Sep 24 05:59:59 PM UTC 24 3667660900 ps
T76 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3480679517 Sep 24 05:59:18 PM UTC 24 Sep 24 06:00:01 PM UTC 24 61715500 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.2518393383 Sep 24 05:59:38 PM UTC 24 Sep 24 06:00:05 PM UTC 24 50657300 ps
T100 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.2417288269 Sep 24 05:59:48 PM UTC 24 Sep 24 06:00:15 PM UTC 24 814907600 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.1659998129 Sep 24 05:57:07 PM UTC 24 Sep 24 06:00:21 PM UTC 24 4689158300 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.3666410872 Sep 24 05:51:05 PM UTC 24 Sep 24 06:00:22 PM UTC 24 21242427700 ps
T65 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1270706133 Sep 24 06:00:00 PM UTC 24 Sep 24 06:00:31 PM UTC 24 24994500 ps
T88 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.637119489 Sep 24 05:50:34 PM UTC 24 Sep 24 06:00:33 PM UTC 24 11706072800 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.3212967505 Sep 24 06:00:08 PM UTC 24 Sep 24 06:00:33 PM UTC 24 46964800 ps
T268 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3257177010 Sep 24 06:00:10 PM UTC 24 Sep 24 06:00:33 PM UTC 24 15419400 ps
T159 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1047511104 Sep 24 05:54:25 PM UTC 24 Sep 24 06:07:19 PM UTC 24 141846500 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1683833794 Sep 24 05:56:57 PM UTC 24 Sep 24 06:00:34 PM UTC 24 3172310000 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.1392459281 Sep 24 06:00:02 PM UTC 24 Sep 24 06:00:35 PM UTC 24 84941900 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.2814983772 Sep 24 05:59:46 PM UTC 24 Sep 24 06:00:36 PM UTC 24 1592664300 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.4041324350 Sep 24 05:59:23 PM UTC 24 Sep 24 06:00:45 PM UTC 24 5893230500 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.3645403021 Sep 24 06:00:22 PM UTC 24 Sep 24 06:00:51 PM UTC 24 38860300 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.1089012470 Sep 24 05:53:27 PM UTC 24 Sep 24 06:01:06 PM UTC 24 111047000 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3389158229 Sep 24 06:00:35 PM UTC 24 Sep 24 06:01:18 PM UTC 24 36388000 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.2175284405 Sep 24 06:00:32 PM UTC 24 Sep 24 06:01:21 PM UTC 24 31077900 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.892091350 Sep 24 05:52:22 PM UTC 24 Sep 24 06:01:29 PM UTC 24 107098561700 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.4165118054 Sep 24 05:52:10 PM UTC 24 Sep 24 06:01:39 PM UTC 24 31145588600 ps
T140 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.2239972427 Sep 24 05:47:35 PM UTC 24 Sep 24 06:01:46 PM UTC 24 160174774700 ps
T58 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.2961573161 Sep 24 06:01:22 PM UTC 24 Sep 24 06:01:56 PM UTC 24 901650800 ps
T310 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2729617334 Sep 24 05:57:40 PM UTC 24 Sep 24 06:02:04 PM UTC 24 8532270800 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.2522806411 Sep 24 05:58:05 PM UTC 24 Sep 24 06:02:07 PM UTC 24 23954776700 ps
T261 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1752081208 Sep 24 06:00:35 PM UTC 24 Sep 24 06:02:14 PM UTC 24 33007300 ps
T241 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.1360333944 Sep 24 05:54:27 PM UTC 24 Sep 24 06:02:27 PM UTC 24 1456667400 ps
T86 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.4163315222 Sep 24 05:55:03 PM UTC 24 Sep 24 06:02:47 PM UTC 24 32700544000 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.2851490673 Sep 24 06:00:15 PM UTC 24 Sep 24 06:02:48 PM UTC 24 10012725100 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3956827159 Sep 24 05:48:52 PM UTC 24 Sep 24 06:02:53 PM UTC 24 352753354500 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.2494219199 Sep 24 06:02:05 PM UTC 24 Sep 24 06:03:00 PM UTC 24 1870215500 ps
T242 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.4205476346 Sep 24 05:54:38 PM UTC 24 Sep 24 06:03:03 PM UTC 24 1452851200 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3287898603 Sep 24 06:02:48 PM UTC 24 Sep 24 06:03:25 PM UTC 24 24359000 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2441915882 Sep 24 06:00:23 PM UTC 24 Sep 24 06:03:26 PM UTC 24 37095800 ps
T89 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.1882277932 Sep 24 06:02:07 PM UTC 24 Sep 24 06:03:27 PM UTC 24 819793700 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.1047988647 Sep 24 06:00:36 PM UTC 24 Sep 24 06:03:50 PM UTC 24 7539000900 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.1597373148 Sep 24 06:03:01 PM UTC 24 Sep 24 06:07:14 PM UTC 24 5233977100 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.4185982397 Sep 24 05:46:46 PM UTC 24 Sep 24 06:03:53 PM UTC 24 160189496200 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.810669283 Sep 24 06:00:35 PM UTC 24 Sep 24 06:04:06 PM UTC 24 2428900200 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.3803868362 Sep 24 06:03:28 PM UTC 24 Sep 24 06:04:11 PM UTC 24 18617600 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.1971944437 Sep 24 06:00:51 PM UTC 24 Sep 24 06:04:14 PM UTC 24 75869500 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.3905901641 Sep 24 06:03:03 PM UTC 24 Sep 24 06:04:48 PM UTC 24 1707486600 ps
T214 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.1425695591 Sep 24 06:02:28 PM UTC 24 Sep 24 06:04:50 PM UTC 24 1167265400 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.3930351066 Sep 24 05:56:07 PM UTC 24 Sep 24 06:04:58 PM UTC 24 5033334600 ps
T141 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.2943389973 Sep 24 05:50:38 PM UTC 24 Sep 24 06:04:58 PM UTC 24 160179352500 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.1385810907 Sep 24 06:03:26 PM UTC 24 Sep 24 06:05:05 PM UTC 24 1106560700 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.3356272360 Sep 24 05:47:44 PM UTC 24 Sep 24 06:05:11 PM UTC 24 614303200 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.3205115799 Sep 24 06:02:15 PM UTC 24 Sep 24 06:05:25 PM UTC 24 15276290800 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.179765599 Sep 24 06:04:59 PM UTC 24 Sep 24 06:05:26 PM UTC 24 18194900 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.4211229620 Sep 24 06:03:28 PM UTC 24 Sep 24 06:05:42 PM UTC 24 994471500 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.390799489 Sep 24 06:02:54 PM UTC 24 Sep 24 06:05:53 PM UTC 24 2259578100 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.551353865 Sep 24 06:05:06 PM UTC 24 Sep 24 06:06:04 PM UTC 24 227607000 ps
T101 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2162491274 Sep 24 05:47:12 PM UTC 24 Sep 24 06:06:07 PM UTC 24 81941877600 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1406552365 Sep 24 06:05:11 PM UTC 24 Sep 24 06:06:07 PM UTC 24 191719500 ps
T121 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.277363803 Sep 24 06:05:27 PM UTC 24 Sep 24 06:06:08 PM UTC 24 12410400 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.962515986 Sep 24 06:05:26 PM UTC 24 Sep 24 06:06:13 PM UTC 24 83442200 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.1429575300 Sep 24 06:00:33 PM UTC 24 Sep 24 06:06:15 PM UTC 24 173901300 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.1518206202 Sep 24 06:04:49 PM UTC 24 Sep 24 06:06:19 PM UTC 24 3683311300 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.2430865839 Sep 24 06:06:09 PM UTC 24 Sep 24 06:06:37 PM UTC 24 866324500 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.510555023 Sep 24 06:06:20 PM UTC 24 Sep 24 06:06:38 PM UTC 24 71753100 ps
T105 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.3205674256 Sep 24 06:06:08 PM UTC 24 Sep 24 06:06:39 PM UTC 24 83045300 ps
T196 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3143309305 Sep 24 06:06:16 PM UTC 24 Sep 24 06:06:42 PM UTC 24 15153200 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3045499222 Sep 24 06:06:35 PM UTC 24 Sep 24 06:06:54 PM UTC 24 16046700 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2818201198 Sep 24 06:06:38 PM UTC 24 Sep 24 06:06:56 PM UTC 24 15924300 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.2266619016 Sep 24 06:01:18 PM UTC 24 Sep 24 06:07:00 PM UTC 24 11233327000 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.3268274336 Sep 24 06:06:39 PM UTC 24 Sep 24 06:07:03 PM UTC 24 30802200 ps
T279 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1077648686 Sep 24 05:46:49 PM UTC 24 Sep 24 06:07:09 PM UTC 24 1306385200 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.1541534920 Sep 24 06:03:51 PM UTC 24 Sep 24 06:07:10 PM UTC 24 2881496500 ps
T262 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.3927519243 Sep 24 06:06:08 PM UTC 24 Sep 24 06:07:10 PM UTC 24 325119700 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.851971270 Sep 24 06:04:51 PM UTC 24 Sep 24 06:07:10 PM UTC 24 15318181600 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2412760385 Sep 24 06:00:37 PM UTC 24 Sep 24 06:07:12 PM UTC 24 223276000 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.4222343087 Sep 24 06:04:07 PM UTC 24 Sep 24 06:07:24 PM UTC 24 6596862400 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.3834027701 Sep 24 05:57:26 PM UTC 24 Sep 24 06:07:26 PM UTC 24 4067909400 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1693782937 Sep 24 06:04:15 PM UTC 24 Sep 24 06:07:26 PM UTC 24 2712982100 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.3884545570 Sep 24 05:50:24 PM UTC 24 Sep 24 06:07:37 PM UTC 24 829723500 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2110299957 Sep 24 06:05:54 PM UTC 24 Sep 24 06:07:45 PM UTC 24 1864535700 ps
T59 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.628605288 Sep 24 06:07:11 PM UTC 24 Sep 24 06:07:47 PM UTC 24 3753480400 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2364228052 Sep 24 06:06:38 PM UTC 24 Sep 24 06:08:42 PM UTC 24 10034974600 ps
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