Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

---

Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	0	16	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	0	16	100.00	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	222499	1		T1	14		T3	47		T4	4
auto[FlashEraseBank]	253437	1		T2	20		T3	12		T5	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	240547	1		T2	20		T3	59		T4	2
auto[FlashOpProgram]	216337	1		T1	14		T4	1		T5	4
auto[FlashOpErase]	15052	1		T4	1		T5	1		T6	1
auto[FlashOpInvalid]	4000	1		T33	200		T83	200		T87	200

---

Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	240547	1		T2	20		T3	59		T4	2
op[FlashOpProgram]	216337	1		T1	14		T4	1		T5	4
op[FlashOpErase]	15052	1		T4	1		T5	1		T6	1
read_erase_read	554	1		T26	11		T43	1		T201	2
read_prog_read	792	1		T5	1		T38	3		T36	3

---

Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	329908	1		T1	14		T2	20		T3	59
auto[FlashPartInfo]	138172	1		T11	3		T6	1		T12	1
auto[FlashPartInfo1]	2102	1		T33	80		T66	2		T70	1
auto[FlashPartInfo2]	5754	1		T8	1		T38	5		T26	2

---

Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for op_part_cross

Bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	165102	1		T2	20		T3	59		T4	2
auto[FlashPartData]	auto[FlashOpProgram]	160294	1		T1	14		T4	1		T5	4
auto[FlashPartData]	auto[FlashOpErase]	2542	1		T4	1		T5	1		T6	1
auto[FlashPartData]	auto[FlashOpInvalid]	1970	1		T33	90		T83	98		T87	96
auto[FlashPartInfo]	auto[FlashOpRead]	71268	1		T11	3		T12	1		T37	6
auto[FlashPartInfo]	auto[FlashOpProgram]	54139	1		T6	1		T8	1		T32	1
auto[FlashPartInfo]	auto[FlashOpErase]	12111	1		T26	7		T55	118		T33	15
auto[FlashPartInfo]	auto[FlashOpInvalid]	654	1		T33	30		T83	40		T87	24
auto[FlashPartInfo1]	auto[FlashOpRead]	1274	1		T33	40		T66	2		T70	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	163	1		T147	1		T277	1		T443	32
auto[FlashPartInfo1]	auto[FlashOpErase]	1	1		T144	1		-	-		-	-
auto[FlashPartInfo1]	auto[FlashOpInvalid]	664	1		T33	40		T83	30		T87	40
auto[FlashPartInfo2]	auto[FlashOpRead]	2903	1		T38	3		T26	2		T33	40
auto[FlashPartInfo2]	auto[FlashOpProgram]	1741	1		T8	1		T38	2		T33	20
auto[FlashPartInfo2]	auto[FlashOpErase]	398	1		T33	20		T83	16		T155	2
auto[FlashPartInfo2]	auto[FlashOpInvalid]	712	1		T33	40		T83	32		T87	40