Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.62	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	1	31	96.88

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	1	31	96.88	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29230	1		T4	4		T26	3		T55	228
auto[1]	50	1		T50	4		T116	1		T155	2
auto[2]	56	1		T116	1		T155	8		T62	4
auto[3]	250	1		T37	1		T39	1		T155	15

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7397	1		T4	1		T26	2		T55	57
evic_idx[1]	7399	1		T4	1		T37	1		T55	57
evic_idx[2]	7394	1		T4	1		T55	57		T53	1
evic_idx[3]	7396	1		T4	1		T26	1		T55	57

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28764	1		T4	4		T26	3		T55	228
evic_op[2]	286	1		T37	1		T36	16		T50	4

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	1	31	96.88	1

Automatically Generated Cross Bins for evic_all_cross

Uncovered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST	NUMBER
[evic_idx[0]]	[evic_op[2]]	[auto[2]]	0	1	1

Covered bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7123	1		T4	1		T26	2		T55	57
evic_idx[0]	evic_op[1]	auto[1]	10	1		T155	1		T354	1		T355	3
evic_idx[0]	evic_op[1]	auto[2]	9	1		T155	3		T356	2		T355	2
evic_idx[0]	evic_op[1]	auto[3]	49	1		T155	4		T264	1		T158	4
evic_idx[0]	evic_op[2]	auto[0]	59	1		T36	4		T103	3		T201	4
evic_idx[0]	evic_op[2]	auto[1]	4	1		T50	1		T357	1		T358	1
evic_idx[0]	evic_op[2]	auto[3]	9	1		T359	1		T360	1		T361	1
evic_idx[1]	evic_op[1]	auto[0]	7119	1		T4	1		T55	57		T53	1
evic_idx[1]	evic_op[1]	auto[1]	6	1		T264	1		T355	2		T362	1
evic_idx[1]	evic_op[1]	auto[2]	10	1		T155	2		T356	3		T355	2
evic_idx[1]	evic_op[1]	auto[3]	54	1		T155	4		T264	2		T158	2
evic_idx[1]	evic_op[2]	auto[0]	56	1		T36	4		T103	3		T201	4
evic_idx[1]	evic_op[2]	auto[1]	5	1		T50	1		T363	1		T364	2
evic_idx[1]	evic_op[2]	auto[2]	3	1		T365	1		T366	1		T367	1
evic_idx[1]	evic_op[2]	auto[3]	12	1		T37	1		T39	1		T296	1
evic_idx[2]	evic_op[1]	auto[0]	7122	1		T4	1		T55	57		T53	1
evic_idx[2]	evic_op[1]	auto[1]	6	1		T355	2		T368	1		T362	1
evic_idx[2]	evic_op[1]	auto[2]	7	1		T155	1		T356	2		T355	1
evic_idx[2]	evic_op[1]	auto[3]	58	1		T155	3		T264	1		T158	4
evic_idx[2]	evic_op[2]	auto[0]	55	1		T36	4		T103	3		T201	4
evic_idx[2]	evic_op[2]	auto[1]	5	1		T50	1		T299	1		T369	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T116	1		T370	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	5	1		T371	1		T372	1		T373	1
evic_idx[3]	evic_op[1]	auto[0]	7124	1		T4	1		T26	1		T55	57
evic_idx[3]	evic_op[1]	auto[1]	8	1		T155	1		T355	3		T368	1
evic_idx[3]	evic_op[1]	auto[2]	6	1		T155	2		T356	1		T355	1
evic_idx[3]	evic_op[1]	auto[3]	53	1		T155	4		T158	3		T356	5
evic_idx[3]	evic_op[2]	auto[0]	52	1		T36	4		T103	3		T201	4
evic_idx[3]	evic_op[2]	auto[1]	6	1		T50	1		T116	1		T299	1
evic_idx[3]	evic_op[2]	auto[2]	3	1		T374	1		T367	1		T375	1
evic_idx[3]	evic_op[2]	auto[3]	10	1		T263	1		T365	1		T376	1