Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	39585	1		T80	1144		T343	13061		T344	2515
rd_lvl[2]	42283	1		T80	330		T343	9019		T344	1792
rd_lvl[3]	15441	1		T344	951		T345	1058		T346	733
rd_lvl[4]	29873	1		T347	1375		T344	863		T345	833
rd_lvl[5]	9861	1		T347	497		T344	741		T345	51
rd_lvl[6]	7138	1		T48	87		T308	590		T347	1
rd_lvl[7]	12293	1		T48	24		T308	1383		T347	46
rd_lvl[8]	20442	1		T47	449		T308	1036		T347	4
rd_lvl[9]	6901	1		T48	4		T80	1		T47	34
rd_lvl[10]	6827	1		T48	3		T347	1		T348	227
rd_lvl[11]	4616	1		T44	298		T47	76		T347	1
rd_lvl[12]	5924	1		T44	131		T349	1212		T347	44
rd_lvl[13]	3109	1		T45	255		T80	1		T349	465
rd_lvl[14]	4032	1		T44	184		T45	133		T350	1137
rd_lvl[15]	1017	1		T310	300		T351	112		T352	3