Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	317270	1		T1	2		T2	2		T3	2
all_pins[1]	317270	1		T1	2		T2	2		T3	2
all_pins[2]	317270	1		T1	2		T2	2		T3	2
all_pins[3]	317270	1		T1	2		T2	2		T3	2
all_pins[4]	317270	1		T1	2		T2	2		T3	2
all_pins[5]	317270	1		T1	2		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1590337	1		T1	12		T2	12		T3	12
values[0x1]	313283	1		T40	1541		T44	1226		T41	1397
transitions[0x0=>0x1]	282345	1		T40	1541		T44	1226		T41	1397
transitions[0x1=>0x0]	282324	1		T40	1541		T44	1226		T41	1397

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	317122	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	148	1		T248	4		T249	6		T334	3
all_pins[0]	transitions[0x0=>0x1]	67	1		T248	4		T249	6		T335	2
all_pins[0]	transitions[0x1=>0x0]	74	1		T248	1		T249	2		T334	1
all_pins[1]	values[0x0]	317115	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	155	1		T248	1		T249	2		T334	4
all_pins[1]	transitions[0x0=>0x1]	127	1		T248	1		T334	4		T335	3
all_pins[1]	transitions[0x1=>0x0]	1972	1		T310	500		T351	220		T377	1205
all_pins[2]	values[0x0]	315270	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	2000	1		T310	500		T351	220		T377	1205
all_pins[2]	transitions[0x0=>0x1]	44	1		T249	2		T335	1		T337	1
all_pins[2]	transitions[0x1=>0x0]	209523	1		T44	613		T45	522		T48	118
all_pins[3]	values[0x0]	105791	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	211479	1		T44	613		T45	522		T48	118
all_pins[3]	transitions[0x0=>0x1]	182646	1		T44	613		T45	522		T48	115
all_pins[3]	transitions[0x1=>0x0]	70612	1		T40	1541		T44	613		T41	1397
all_pins[4]	values[0x0]	217825	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	99445	1		T40	1541		T44	613		T41	1397
all_pins[4]	transitions[0x0=>0x1]	99433	1		T40	1541		T44	613		T41	1397
all_pins[4]	transitions[0x1=>0x0]	44	1		T335	2		T337	1		T342	2
all_pins[5]	values[0x0]	317214	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	56	1		T248	2		T335	2		T337	1
all_pins[5]	transitions[0x0=>0x1]	28	1		T248	1		T335	1		T342	2
all_pins[5]	transitions[0x1=>0x0]	99	1		T248	2		T249	5		T334	2