Unified Coverage Report :: Group :: tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

Group : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_cov_0/flash_ctrl_phy_cov_if.sv

---

Summary for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	99	0	99	100.00

Variables for Group tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_phy_cov_if::b2b_read_interval_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
read_interval	99	0	99	100.00	100	1	1	0

Summary for Variable read_interval

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	99	0	99	100.00

User Defined Bins for read_interval

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5337079	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
duration[1]	393398	1		T3	16		T11	1		T12	12
duration[2]	761113	1		T2	44		T3	246		T4	10
duration[3]	107745	1		T3	18		T11	1		T12	1
duration[4]	1059943	1		T2	80		T3	380		T4	16
duration[5]	60878	1		T3	23		T32	7		T52	5
duration[6]	440021	1		T3	21		T32	5		T37	48
duration[7]	48152	1		T3	14		T32	3		T43	402
duration[8]	20916	1		T3	19		T32	4		T37	3
duration[9]	28473	1		T3	25		T32	2		T52	12
duration[10]	15741	1		T3	16		T49	35		T52	11
duration[11]	17101	1		T3	14		T52	6		T69	1
duration[12]	16165	1		T3	10		T10	1		T52	7
duration[13]	12818	1		T3	6		T52	12		T70	12
duration[14]	13704	1		T3	5		T10	1		T52	9
duration[15]	11119	1		T3	5		T10	2		T32	1
duration[16]	10953	1		T3	4		T32	1		T52	7
duration[17]	12041	1		T2	2		T3	1		T18	4
duration[18]	9275	1		T3	1		T50	1		T52	5
duration[19]	11674	1		T2	4		T18	8		T10	2
duration[20]	9873	1		T38	1		T26	1		T50	3
duration[21]	9716	1		T2	2		T18	2		T38	1
duration[22]	9494	1		T10	1		T26	1		T66	15
duration[23]	7228	1		T2	3		T18	2		T37	1
duration[24]	7484	1		T18	1		T37	1		T38	2
duration[25]	7211	1		T2	3		T18	4		T26	1
duration[26]	7138	1		T3	2		T10	1		T38	1
duration[27]	3477	1		T2	2		T18	1		T38	1
duration[28]	3171	1		T37	1		T38	1		T26	1
duration[29]	3134	1		T2	2		T3	6		T18	2
duration[30]	2830	1		T3	2		T18	1		T37	1
duration[31]	2865	1		T2	3		T3	1		T18	4
duration[32]	2373	1		T2	1		T3	2		T36	1
duration[33]	3796	1		T2	3		T18	1		T10	1
duration[34]	4757	1		T3	5		T36	2		T50	1
duration[35]	1842	1		T2	2		T3	3		T18	2
duration[36]	1922	1		T2	1		T18	1		T38	1
duration[37]	2016	1		T2	3		T18	4		T82	1
duration[38]	517	1		T2	1		T53	1		T50	3
duration[39]	1271	1		T2	4		T18	1		T26	1
duration[40]	1955	1		T55	1		T197	31		T155	1
duration[41]	1316	1		T2	5		T26	1		T50	1
duration[42]	9835	1		T2	1		T18	1		T38	1
duration[43]	624	1		T26	2		T50	1		T82	1
duration[44]	264	1		T38	1		T71	1		T212	1
duration[45]	288	1		T50	1		T155	2		T203	2
duration[46]	1207	1		T38	2		T50	1		T71	1
duration[47]	198	1		T2	1		T54	1		T155	1
duration[48]	548	1		T203	2		T120	1		T150	1
duration[49]	244	1		T2	1		T55	1		T50	1
duration[50]	162764	1		T32	1		T55	1		T50	1
duration[51]	247595	1		T2	1		T71	1		T83	1
duration[52]	21320	1		T38	1		T55	1		T50	3
duration[53]	184089	1		T2	1		T54	7		T197	1
duration[54]	11001	1		T55	1		T50	3		T83	1
duration[55]	7824	1		T2	2		T55	1		T54	17
duration[56]	1310	1		T26	1		T54	1		T198	3
duration[57]	5791	1		T50	1		T83	3		T54	90
duration[58]	3093	1		T50	1		T54	7		T198	15
duration[59]	1189	1		T2	1		T55	1		T50	1
duration[60]	2282	1		T55	1		T51	1		T54	45
duration[61]	2095	1		T2	1		T32	1		T55	1
duration[62]	1192	1		T38	1		T50	1		T54	3
duration[63]	2706	1		T2	1		T32	1		T54	13
duration[64]	3040	1		T32	3		T55	2		T50	1
duration[65]	1532	1		T2	1		T55	1		T54	6
duration[66]	4478	1		T32	2		T55	1		T50	1
duration[67]	1341	1		T2	1		T32	2		T55	3
duration[68]	3388	1		T32	1		T55	1		T50	1
duration[69]	1030	1		T2	1		T32	2		T54	6
duration[70]	2630	1		T54	4		T198	10		T156	1
duration[71]	679	1		T2	3		T32	2		T55	1
duration[72]	3711	1		T32	1		T54	5		T198	3
duration[73]	478	1		T2	1		T55	3		T50	1
duration[74]	2288	1		T32	1		T54	2		T198	4
duration[75]	287	1		T2	1		T54	3		T118	6
duration[76]	2004	1		T32	1		T55	1		T54	3
duration[77]	233	1		T2	1		T32	1		T54	1
duration[78]	441	1		T50	2		T54	2		T198	1
duration[79]	178	1		T2	1		T39	1		T54	1
duration[80]	1867	1		T54	1		T198	3		T118	5
duration[81]	161	1		T2	1		T55	1		T50	1
duration[82]	146	1		T198	3		T118	4		T212	1
duration[83]	112	1		T2	1		T54	1		T198	2
duration[84]	175	1		T55	2		T82	1		T54	6
duration[85]	105	1		T2	1		T55	1		T39	1
duration[86]	87	1		T55	1		T50	1		T54	2
duration[87]	85	1		T2	2		T50	1		T54	1
duration[88]	88	1		T55	1		T54	2		T118	1
duration[89]	79	1		T50	1		T198	1		T212	1
duration[90]	108	1		T38	1		T55	1		T54	1
duration[91]	56	1		T50	2		T54	1		T212	1
duration[92]	83	1		T2	1		T18	1		T127	1
duration[93]	87	1		T69	1		T70	1		T71	1
duration[94]	132	1		T11	1		T32	1		T37	1
duration[95]	63	1		T50	1		T54	1		T120	3
duration[96]	75	1		T55	2		T54	1		T219	1
duration[97]	59	1		T12	1		T37	1		T55	1
duration[98]	57	1		T3	2		T120	2		T421	1
duration[99]	62	1		T3	1		T55	1		T150	1