Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T248	4		T249	7		T334	4
all_values[1]	275	1		T248	4		T249	7		T334	4
all_values[2]	275	1		T248	4		T249	7		T334	4
all_values[3]	275	1		T248	4		T249	7		T334	4
all_values[4]	275	1		T248	4		T249	7		T334	4
all_values[5]	275	1		T248	4		T249	7		T334	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	907	1		T248	17		T249	21		T334	15
auto[1]	743	1		T248	7		T249	21		T334	9

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	573	1		T248	7		T249	14		T334	10
auto[1]	1077	1		T248	17		T249	28		T334	14

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	992	1		T248	14		T249	27		T334	17
auto[1]	658	1		T248	10		T249	15		T334	7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	91	1		T248	1		T249	2		T334	1
all_values[0]	auto[0]	auto[1]	auto[1]	79	1		T248	1		T249	4		T334	2
all_values[0]	auto[1]	auto[0]	auto[1]	64	1		T248	2		T334	1		T335	1
all_values[0]	auto[1]	auto[1]	auto[1]	41	1		T249	1		T335	2		T336	2
all_values[1]	auto[0]	auto[0]	auto[1]	82	1		T248	2		T249	2		T335	2
all_values[1]	auto[0]	auto[1]	auto[1]	80	1		T248	1		T249	2		T334	2
all_values[1]	auto[1]	auto[0]	auto[1]	70	1		T249	3		T334	1		T335	1
all_values[1]	auto[1]	auto[1]	auto[1]	43	1		T248	1		T334	1		T336	1
all_values[2]	auto[0]	auto[0]	auto[0]	88	1		T248	2		T249	3		T334	2
all_values[2]	auto[0]	auto[1]	auto[0]	82	1		T248	1		T334	2		T335	1
all_values[2]	auto[1]	auto[0]	auto[1]	58	1		T249	1		T335	1		T337	1
all_values[2]	auto[1]	auto[1]	auto[1]	47	1		T248	1		T249	3		T335	1
all_values[3]	auto[0]	auto[0]	auto[0]	77	1		T248	2		T249	1		T335	2
all_values[3]	auto[0]	auto[1]	auto[0]	81	1		T249	3		T334	2		T335	2
all_values[3]	auto[1]	auto[0]	auto[1]	61	1		T248	2		T334	2		T335	3
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T249	3		T337	3		T336	1
all_values[4]	auto[0]	auto[0]	auto[0]	70	1		T249	2		T334	4		T335	3
all_values[4]	auto[0]	auto[0]	auto[1]	21	1		T249	1		T335	2		T337	1
all_values[4]	auto[0]	auto[1]	auto[0]	60	1		T249	2		T337	1		T336	4
all_values[4]	auto[0]	auto[1]	auto[1]	19	1		T248	1		T338	1		T339	1
all_values[4]	auto[1]	auto[0]	auto[1]	63	1		T248	3		T249	1		T335	2
all_values[4]	auto[1]	auto[1]	auto[1]	42	1		T249	1		T340	2		T341	2
all_values[5]	auto[0]	auto[0]	auto[0]	70	1		T248	2		T249	2		T337	1
all_values[5]	auto[0]	auto[0]	auto[1]	23	1		T249	1		T334	2		T337	2
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T249	1		T335	4		T336	1
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T248	1		T249	1		T342	1
all_values[5]	auto[1]	auto[0]	auto[1]	69	1		T248	1		T249	2		T334	2
all_values[5]	auto[1]	auto[1]	auto[1]	44	1		T335	2		T337	1		T340	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal