Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]	100.00	1	100	1	64	64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	25025041	1		T1	304		T2	58		T3	305
full_word	7691316	1		T1	69		T2	3		T3	59

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	32716027	1		T1	373		T2	61		T3	364
auto[TlIntgErrCmd]	122	1		T243	6		T244	4		T356	4
auto[TlIntgErrData]	114	1		T242	4		T243	2		T244	3
auto[TlIntgErrBoth]	94	1		T242	6		T243	2		T244	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	28359715	1		T1	299		T2	57		T3	323
auto[1]	4356642	1		T1	74		T2	4		T3	41

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	24330512	1		T1	296		T2	56		T3	299
auto[TlIntgErrNone]	partial	auto[1]	694229	1		T1	8		T2	2		T3	6
auto[TlIntgErrNone]	full_word	auto[0]	4029051	1		T1	3		T2	1		T3	24
auto[TlIntgErrNone]	full_word	auto[1]	3662235	1		T1	66		T2	2		T3	35
auto[TlIntgErrCmd]	partial	auto[0]	46	1		T243	1		T244	2		T356	2
auto[TlIntgErrCmd]	partial	auto[1]	70	1		T243	5		T244	2		T356	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T358	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T350	1		T353	1		T352	1
auto[TlIntgErrData]	partial	auto[0]	55	1		T242	1		T243	2		T244	2
auto[TlIntgErrData]	partial	auto[1]	45	1		T242	3		T244	1		T350	3
auto[TlIntgErrData]	full_word	auto[0]	6	1		T350	1		T351	1		T354	2
auto[TlIntgErrData]	full_word	auto[1]	8	1		T356	1		T357	1		T353	1
auto[TlIntgErrBoth]	partial	auto[0]	38	1		T242	1		T244	3		T356	1
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T242	3		T243	1		T356	1
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T242	2		T243	1		T353	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T356	1		T350	1		T355	1

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	18172	1		T129	527		T76	282		T132	559
full_word	3736741	1		T2	10		T10	138		T12	338

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	3754611	1		T2	10		T10	138		T12	338
auto[TlIntgErrCmd]	104	1		T242	4		T243	5		T244	1
auto[TlIntgErrData]	91	1		T242	2		T243	1		T244	3
auto[TlIntgErrBoth]	107	1		T242	4		T243	3		T244	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3730697	1		T2	10		T10	138		T12	338
auto[1]	24216	1		T129	633		T76	400		T132	826

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	1066	1		T129	44		T76	18		T132	10
auto[TlIntgErrNone]	partial	auto[1]	16824	1		T129	483		T76	264		T132	549
auto[TlIntgErrNone]	full_word	auto[0]	3729502	1		T2	10		T10	138		T12	338
auto[TlIntgErrNone]	full_word	auto[1]	7219	1		T129	150		T76	136		T132	277
auto[TlIntgErrCmd]	partial	auto[0]	41	1		T242	3		T356	1		T350	1
auto[TlIntgErrCmd]	partial	auto[1]	56	1		T243	4		T244	1		T356	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T359	2		T360	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T242	1		T243	1		T352	1
auto[TlIntgErrData]	partial	auto[0]	41	1		T242	2		T244	2		T356	2
auto[TlIntgErrData]	partial	auto[1]	43	1		T243	1		T244	1		T356	3
auto[TlIntgErrData]	full_word	auto[0]	2	1		T353	1		T261	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1		T359	1		T360	2		T358	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1		T242	2		T243	1		T244	2
auto[TlIntgErrBoth]	partial	auto[1]	62	1		T242	2		T243	2		T244	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T358	1		T361	2		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1		T353	1		T261	1		T355	1