Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
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Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 97.92 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block] 95.83 1 100 1 64 64
tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block] 100.00 1 100 1 64 64



Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
95.83 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 1 15 93.75


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_eflash_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 1 15 93.75 100 1 1 0


Group Instance : tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64



Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 8 0 8 100.00
Crosses 16 0 16 100.00


Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_num_num_enable_bytes 2 0 2 100.00 100 1 1 0
cp_tl_intg_err_type 4 0 4 100.00 100 1 1 0
cp_write 2 0 2 100.00 100 1 1 2


Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[flash_ctrl_core_reg_block]
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 16 0 16 100.00 100 1 1 0


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 20501 1 T77 1120 T79 70 T134 788
full_word 3719700 1 T1 10 T3 417 T10 232


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 3739887 1 T1 10 T3 417 T10 232
auto[TlIntgErrCmd] 99 1 T259 2 T260 4 T261 1
auto[TlIntgErrData] 114 1 T259 3 T260 3 T261 3
auto[TlIntgErrBoth] 101 1 T259 3 T260 3 T261 3


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3714865 1 T1 10 T3 417 T10 232
auto[1] 25336 1 T77 1365 T79 127 T134 886


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 1 15 93.75 1


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTNUMBER
[auto[TlIntgErrBoth]] [full_word] [auto[0]] 0 1 1


Covered bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 1234 1 T77 40 T134 65 T132 5
auto[TlIntgErrNone] partial auto[1] 18980 1 T77 1080 T79 70 T134 723
auto[TlIntgErrNone] full_word auto[0] 3713502 1 T1 10 T3 417 T10 232
auto[TlIntgErrNone] full_word auto[1] 6171 1 T77 285 T79 57 T134 163
auto[TlIntgErrCmd] partial auto[0] 32 1 T382 4 T277 1 T279 3
auto[TlIntgErrCmd] partial auto[1] 60 1 T259 2 T260 4 T261 1
auto[TlIntgErrCmd] full_word auto[0] 3 1 T379 2 T275 1 - -
auto[TlIntgErrCmd] full_word auto[1] 4 1 T375 1 T279 1 T275 1
auto[TlIntgErrData] partial auto[0] 60 1 T259 1 T260 3 T261 3
auto[TlIntgErrData] partial auto[1] 41 1 T259 1 T375 2 T377 2
auto[TlIntgErrData] full_word auto[0] 6 1 T377 1 T277 1 T278 1
auto[TlIntgErrData] full_word auto[1] 7 1 T259 1 T382 1 T279 2
auto[TlIntgErrBoth] partial auto[0] 28 1 T259 1 T377 2 T382 2
auto[TlIntgErrBoth] partial auto[1] 66 1 T259 2 T260 3 T261 2
auto[TlIntgErrBoth] full_word auto[1] 7 1 T261 1 T378 1 T374 2


Summary for Variable cp_num_num_enable_bytes

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_num_enable_bytes

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
partial 23897327 1 T1 15 T2 307 T3 957
full_word 7488374 1 T1 4 T2 57 T3 2967


Summary for Variable cp_tl_intg_err_type

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 4 0 4 100.00


Automatically Generated Bins for cp_tl_intg_err_type

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] 31385361 1 T1 19 T2 364 T3 3924
auto[TlIntgErrCmd] 93 1 T259 2 T260 2 T261 4
auto[TlIntgErrData] 107 1 T259 5 T260 3 T261 1
auto[TlIntgErrBoth] 140 1 T259 3 T260 5 T261 5


Summary for Variable cp_write

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_write

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 27020761 1 T1 15 T2 323 T3 1423
auto[1] 4364940 1 T1 4 T2 41 T3 2501


Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 16 0 16 100.00


Automatically Generated Cross Bins for cr_all

Bins
cp_tl_intg_err_typecp_num_num_enable_bytescp_writeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
auto[TlIntgErrNone] partial auto[0] 23210922 1 T1 15 T2 297 T3 751
auto[TlIntgErrNone] partial auto[1] 686095 1 T2 10 T3 206 T15 9
auto[TlIntgErrNone] full_word auto[0] 3809678 1 T2 26 T3 672 T15 6
auto[TlIntgErrNone] full_word auto[1] 3678666 1 T1 4 T2 31 T3 2295
auto[TlIntgErrCmd] partial auto[0] 47 1 T260 1 T261 3 T375 4
auto[TlIntgErrCmd] partial auto[1] 37 1 T259 2 T260 1 T261 1
auto[TlIntgErrCmd] full_word auto[0] 5 1 T278 1 T376 1 T381 1
auto[TlIntgErrCmd] full_word auto[1] 4 1 T377 1 T275 1 T376 1
auto[TlIntgErrData] partial auto[0] 55 1 T259 3 T260 3 T375 1
auto[TlIntgErrData] partial auto[1] 44 1 T259 2 T382 4 T279 1
auto[TlIntgErrData] full_word auto[0] 4 1 T377 1 T279 1 T275 1
auto[TlIntgErrData] full_word auto[1] 4 1 T261 1 T377 1 T374 1
auto[TlIntgErrBoth] partial auto[0] 45 1 T260 2 T261 3 T377 2
auto[TlIntgErrBoth] partial auto[1] 82 1 T259 3 T260 2 T261 1
auto[TlIntgErrBoth] full_word auto[0] 5 1 T261 1 T382 2 T378 1
auto[TlIntgErrBoth] full_word auto[1] 8 1 T260 1 T278 1 T378 1

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