Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb	96.88	87.50	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
76.67	90.00	40.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	87.50	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	90.00	100.00			100.00		u_host_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T9 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T67,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T67,T59
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	1447637068	1444190040	0	0
CheckNGreaterZero_A	4192	4192	0	0
GntImpliesReady_A	1447637068	374912100	0	0
GntImpliesValid_A	1447637068	374912100	0	0
GrantKnown_A	1447637068	1444190040	0	0
IdxKnown_A	1447637068	1444190040	0	0
IndexIsCorrect_A	1447637068	374912100	0	0
NoReadyValidNoGrant_A	1447637068	165353562	0	0
Priority_A	1447637068	398536694	0	0
ReadyAndValidImplyGrant_A	1447637068	374912100	0	0
ReqAndReadyImplyGrant_A	1447637068	374912100	0	0
ReqImpliesValid_A	1447637068	398536694	0	0
ValidKnown_A	1447637068	1444190040	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	1444190040	0	0
T1	6308	6056	0	0
T2	7664	7288	0	0
T3	132400	132156	0	0
T4	16872	14048	0	0
T9	16140	15904	0	0
T10	25108	24824	0	0
T15	5820	5524	0	0
T16	8124	7900	0	0
T17	7476	7100	0	0
T18	782076	781820	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	4192	4192	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T4	4	4	0	0
T9	4	4	0	0
T10	4	4	0	0
T15	4	4	0	0
T16	4	4	0	0
T17	4	4	0	0
T18	4	4	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	374912100	0	0
T1	3154	84	0	0
T2	3832	1178	0	0
T3	132400	2134	0	0
T4	16872	376	0	0
T9	16140	4444	0	0
T10	25108	7232	0	0
T11	0	15738	0	0
T15	5820	74	0	0
T16	8124	356	0	0
T17	7476	356	0	0
T18	782076	75550	0	0
T20	275572	0	0	0
T26	189630	17754	0	0
T37	0	163638	0	0
T76	0	19104	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	374912100	0	0
T1	3154	84	0	0
T2	3832	1178	0	0
T3	132400	2134	0	0
T4	16872	376	0	0
T9	16140	4444	0	0
T10	25108	7232	0	0
T11	0	15738	0	0
T15	5820	74	0	0
T16	8124	356	0	0
T17	7476	356	0	0
T18	782076	75550	0	0
T20	275572	0	0	0
T26	189630	17754	0	0
T37	0	163638	0	0
T76	0	19104	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	1444190040	0	0
T1	6308	6056	0	0
T2	7664	7288	0	0
T3	132400	132156	0	0
T4	16872	14048	0	0
T9	16140	15904	0	0
T10	25108	24824	0	0
T15	5820	5524	0	0
T16	8124	7900	0	0
T17	7476	7100	0	0
T18	782076	781820	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	1444190040	0	0
T1	6308	6056	0	0
T2	7664	7288	0	0
T3	132400	132156	0	0
T4	16872	14048	0	0
T9	16140	15904	0	0
T10	25108	24824	0	0
T15	5820	5524	0	0
T16	8124	7900	0	0
T17	7476	7100	0	0
T18	782076	781820	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	374912100	0	0
T1	3154	84	0	0
T2	3832	1178	0	0
T3	132400	2134	0	0
T4	16872	376	0	0
T9	16140	4444	0	0
T10	25108	7232	0	0
T11	0	15738	0	0
T15	5820	74	0	0
T16	8124	356	0	0
T17	7476	356	0	0
T18	782076	75550	0	0
T20	275572	0	0	0
T26	189630	17754	0	0
T37	0	163638	0	0
T76	0	19104	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	165353562	0	0
T1	3154	286	0	0
T2	3832	316	0	0
T3	132400	3364	0	0
T4	16872	1472	0	0
T9	16140	256	0	0
T10	25108	870	0	0
T11	0	814	0	0
T15	5820	272	0	0
T16	8124	694	0	0
T17	7476	986	0	0
T18	782076	7420	0	0
T20	275572	0	0	0
T26	189630	92	0	0
T37	0	12602	0	0
T67	0	26672	0	0
T76	0	1284	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	398536694	0	0
T1	3154	84	0	0
T2	3832	1178	0	0
T3	132400	2134	0	0
T4	16872	376	0	0
T9	16140	4444	0	0
T10	25108	7232	0	0
T11	0	15748	0	0
T15	5820	74	0	0
T16	8124	356	0	0
T17	7476	356	0	0
T18	782076	75550	0	0
T20	275572	0	0	0
T26	189630	17754	0	0
T37	0	163638	0	0
T76	0	19104	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	374912100	0	0
T1	3154	84	0	0
T2	3832	1178	0	0
T3	132400	2134	0	0
T4	16872	376	0	0
T9	16140	4444	0	0
T10	25108	7232	0	0
T11	0	15738	0	0
T15	5820	74	0	0
T16	8124	356	0	0
T17	7476	356	0	0
T18	782076	75550	0	0
T20	275572	0	0	0
T26	189630	17754	0	0
T37	0	163638	0	0
T76	0	19104	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	374912100	0	0
T1	3154	84	0	0
T2	3832	1178	0	0
T3	132400	2134	0	0
T4	16872	376	0	0
T9	16140	4444	0	0
T10	25108	7232	0	0
T11	0	15738	0	0
T15	5820	74	0	0
T16	8124	356	0	0
T17	7476	356	0	0
T18	782076	75550	0	0
T20	275572	0	0	0
T26	189630	17754	0	0
T37	0	163638	0	0
T76	0	19104	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	398536694	0	0
T1	3154	84	0	0
T2	3832	1178	0	0
T3	132400	2134	0	0
T4	16872	376	0	0
T9	16140	4444	0	0
T10	25108	7232	0	0
T11	0	15748	0	0
T15	5820	74	0	0
T16	8124	356	0	0
T17	7476	356	0	0
T18	782076	75550	0	0
T20	275572	0	0	0
T26	189630	17754	0	0
T37	0	163638	0	0
T76	0	19104	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1447637068	1444190040	0	0
T1	6308	6056	0	0
T2	7664	7288	0	0
T3	132400	132156	0	0
T4	16872	14048	0	0
T9	16140	15904	0	0
T10	25108	24824	0	0
T15	5820	5524	0	0
T16	8124	7900	0	0
T17	7476	7100	0	0
T18	782076	781820	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T9 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T67,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T67,T59
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361909267	361047510	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	361909267	92828396	0	0
GntImpliesValid_A	361909267	92828396	0	0
GrantKnown_A	361909267	361047510	0	0
IdxKnown_A	361909267	361047510	0	0
IndexIsCorrect_A	361909267	92828396	0	0
NoReadyValidNoGrant_A	361909267	42010529	0	0
Priority_A	361909267	98693629	0	0
ReadyAndValidImplyGrant_A	361909267	92828396	0	0
ReqAndReadyImplyGrant_A	361909267	92828396	0	0
ReqImpliesValid_A	361909267	98693629	0	0
ValidKnown_A	361909267	361047510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	42010529	0	0
T1	1577	143	0	0
T2	1916	158	0	0
T3	33100	1104	0	0
T4	4218	736	0	0
T9	4035	128	0	0
T10	6277	221	0	0
T15	1455	136	0	0
T16	2031	128	0	0
T17	1869	128	0	0
T18	195519	1562	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	98693629	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	98693629	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T9 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T1,T3,T10
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T67,T59
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T67,T59
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T3,T10

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361909267	361047510	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	361909267	92828396	0	0
GntImpliesValid_A	361909267	92828396	0	0
GrantKnown_A	361909267	361047510	0	0
IdxKnown_A	361909267	361047510	0	0
IndexIsCorrect_A	361909267	92828396	0	0
NoReadyValidNoGrant_A	361909267	42010529	0	0
Priority_A	361909267	98693629	0	0
ReadyAndValidImplyGrant_A	361909267	92828396	0	0
ReqAndReadyImplyGrant_A	361909267	92828396	0	0
ReqImpliesValid_A	361909267	98693629	0	0
ValidKnown_A	361909267	361047510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	42010529	0	0
T1	1577	143	0	0
T2	1916	158	0	0
T3	33100	1104	0	0
T4	4218	736	0	0
T9	4035	128	0	0
T10	6277	221	0	0
T15	1455	136	0	0
T16	2031	128	0	0
T17	1869	128	0	0
T18	195519	1562	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	98693629	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	92828396	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	98693629	0	0
T1	1577	42	0	0
T2	1916	589	0	0
T3	33100	685	0	0
T4	4218	188	0	0
T9	4035	32	0	0
T10	6277	1124	0	0
T15	1455	37	0	0
T16	2031	32	0	0
T17	1869	32	0	0
T18	195519	13865	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T9 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T16
1	0	Covered	T3,T10,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T67,T59
1	0	Covered	T3,T9,T16
1	1	Covered	T3,T10,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T9,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T67,T59
1	1	Covered	T3,T9,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361909267	361047510	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	361909267	94627683	0	0
GntImpliesValid_A	361909267	94627683	0	0
GrantKnown_A	361909267	361047510	0	0
IdxKnown_A	361909267	361047510	0	0
IndexIsCorrect_A	361909267	94627683	0	0
NoReadyValidNoGrant_A	361909267	40666251	0	0
Priority_A	361909267	100574748	0	0
ReadyAndValidImplyGrant_A	361909267	94627683	0	0
ReqAndReadyImplyGrant_A	361909267	94627683	0	0
ReqImpliesValid_A	361909267	100574748	0	0
ValidKnown_A	361909267	361047510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627683	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627683	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627683	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	40666251	0	0
T3	33100	578	0	0
T4	4218	0	0	0
T9	4035	0	0	0
T10	6277	214	0	0
T11	0	407	0	0
T15	1455	0	0	0
T16	2031	219	0	0
T17	1869	365	0	0
T18	195519	2148	0	0
T20	137786	0	0	0
T26	94815	46	0	0
T37	0	6301	0	0
T67	0	13336	0	0
T76	0	642	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	100574748	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7874	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627683	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627683	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	100574748	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7874	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
TOTAL		16	14	87.50
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	87	1	0	0.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	124	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

84                                  // forward path
85         2/2                      assign req_tree[Pa]      = req_i[offset];
           Tests:       T1 T2 T3  | T1 T2 T3 
86                                  assign idx_tree[Pa]      = offset;
87         0/2     ==>              assign data_tree[Pa]     = data_i[offset];
88                                  // backward (grant) path
89         2/2                      assign gnt_o[offset]     = gnt_tree[Pa];
           Tests:       T1 T2 T3  | T1 T2 T3 
90                      
91                                end else begin : gen_tie_off
92                                  // forward path
93                                  assign req_tree[Pa]  = '0;
94                                  assign idx_tree[Pa]  = '0;
95                                  assign data_tree[Pa] = '0;
96                                  logic unused_sigs;
97                                  assign unused_sigs = gnt_tree[Pa];
98                                end
99                              // this creates the node assignments
100                             end else begin : gen_nodes
101                               // forward path
102                               logic sel; // local helper variable
103                               always_comb begin : p_node
104                                 // this always gives priority to the left child
105        1/1                      sel = ~req_tree[C0];
           Tests:       T1 T2 T3 
106                                 // propagate requests
107        1/1                      req_tree[Pa]  = req_tree[C0] | req_tree[C1];
           Tests:       T1 T2 T3 
108                                 // data and index muxes
109        1/1                      idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
           Tests:       T1 T2 T3 
110        1/1                      data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
           Tests:       T1 T2 T3 
111                                 // propagate the grants back to the input
112        1/1                      gnt_tree[C0] = gnt_tree[Pa] & ~sel;
           Tests:       T1 T2 T3 
113        1/1                      gnt_tree[C1] = gnt_tree[Pa] &  sel;
           Tests:       T1 T2 T3 
114                               end
115                             end
116                           end : gen_level
117                         end : gen_tree
118                     
119                         // the results can be found at the tree root
120                         if (EnDataPort) begin : gen_data_port
121                           assign data_o      = data_tree[0];
122                         end else begin : gen_no_dataport
123                           logic [DW-1:0] unused_data;
124        1/1                assign unused_data = data_tree[0];
           Tests:       T1 T2 T9 
125                           assign data_o = '1;
126                         end
127                     
128        1/1              assign idx_o       = idx_tree[0];
           Tests:       T1 T2 T3 
129        1/1              assign valid_o     = req_tree[0];
           Tests:       T1 T2 T3 
130                     
131                         // this propagates a grant back to the input
132        1/1              assign gnt_tree[0] = valid_o & ready_i;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Covered	Percent
Conditions	16	16	100.00
Logical	16	16	100.00
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T16
1	0	Covered	T3,T10,T11

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T3,T10,T11
1	Covered	T1,T2,T3

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Covered	T11,T67,T59
1	0	Covered	T3,T9,T16
1	1	Covered	T3,T10,T11

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T10,T11
1	1	Covered	T3,T9,T16

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T11,T67,T59
1	1	Covered	T3,T9,T16

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

109                    idx_tree[Pa]  = (sel) ? idx_tree[C1]  : idx_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

110                    data_tree[Pa] = (sel) ? data_tree[C1] : data_tree[C0];
                                             -1-  
                                             ==>  
                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T10,T11

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	13	13	100.00	13	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	13	13	100.00	13	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	361909267	361047510	0	0
CheckNGreaterZero_A	1048	1048	0	0
GntImpliesReady_A	361909267	94627625	0	0
GntImpliesValid_A	361909267	94627625	0	0
GrantKnown_A	361909267	361047510	0	0
IdxKnown_A	361909267	361047510	0	0
IndexIsCorrect_A	361909267	94627625	0	0
NoReadyValidNoGrant_A	361909267	40666253	0	0
Priority_A	361909267	100574688	0	0
ReadyAndValidImplyGrant_A	361909267	94627625	0	0
ReqAndReadyImplyGrant_A	361909267	94627625	0	0
ReqImpliesValid_A	361909267	100574688	0	0
ValidKnown_A	361909267	361047510	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1048	1048	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627625	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627625	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627625	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	40666253	0	0
T3	33100	578	0	0
T4	4218	0	0	0
T9	4035	0	0	0
T10	6277	214	0	0
T11	0	407	0	0
T15	1455	0	0	0
T16	2031	219	0	0
T17	1869	365	0	0
T18	195519	2148	0	0
T20	137786	0	0	0
T26	94815	46	0	0
T37	0	6301	0	0
T67	0	13336	0	0
T76	0	642	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	100574688	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7874	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627625	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	94627625	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7869	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	100574688	0	0
T3	33100	382	0	0
T4	4218	0	0	0
T9	4035	2190	0	0
T10	6277	2492	0	0
T11	0	7874	0	0
T15	1455	0	0	0
T16	2031	146	0	0
T17	1869	146	0	0
T18	195519	23910	0	0
T20	137786	0	0	0
T26	94815	8877	0	0
T37	0	81819	0	0
T76	0	9552	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	361909267	361047510	0	0
T1	1577	1514	0	0
T2	1916	1822	0	0
T3	33100	33039	0	0
T4	4218	3512	0	0
T9	4035	3976	0	0
T10	6277	6206	0	0
T15	1455	1381	0	0
T16	2031	1975	0	0
T17	1869	1775	0	0
T18	195519	195455	0	0