| T1083 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.27554988 |
|
|
Oct 15 09:36:06 AM UTC 24 |
Oct 15 09:36:24 AM UTC 24 |
28755500 ps |
| T1084 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.501341440 |
|
|
Oct 15 09:36:03 AM UTC 24 |
Oct 15 09:36:26 AM UTC 24 |
28777200 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.870888361 |
|
|
Oct 15 09:33:54 AM UTC 24 |
Oct 15 09:36:29 AM UTC 24 |
126288400 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.1388208887 |
|
|
Oct 15 09:34:19 AM UTC 24 |
Oct 15 09:36:44 AM UTC 24 |
76329900 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.3701996124 |
|
|
Oct 15 09:34:07 AM UTC 24 |
Oct 15 09:36:57 AM UTC 24 |
40565700 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1611186553 |
|
|
Oct 15 09:34:44 AM UTC 24 |
Oct 15 09:36:59 AM UTC 24 |
37260600 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.1811453653 |
|
|
Oct 15 09:34:01 AM UTC 24 |
Oct 15 09:37:04 AM UTC 24 |
20367500 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.2381613420 |
|
|
Oct 15 09:34:12 AM UTC 24 |
Oct 15 09:37:10 AM UTC 24 |
53448300 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3378204591 |
|
|
Oct 15 09:34:58 AM UTC 24 |
Oct 15 09:37:11 AM UTC 24 |
42654000 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.479377530 |
|
|
Oct 15 09:34:33 AM UTC 24 |
Oct 15 09:37:18 AM UTC 24 |
76108000 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.266999525 |
|
|
Oct 15 09:34:33 AM UTC 24 |
Oct 15 09:37:23 AM UTC 24 |
30923600 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.640235102 |
|
|
Oct 15 09:34:50 AM UTC 24 |
Oct 15 09:37:32 AM UTC 24 |
354579400 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.57287488 |
|
|
Oct 15 09:35:13 AM UTC 24 |
Oct 15 09:37:32 AM UTC 24 |
69080100 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.2577302383 |
|
|
Oct 15 09:34:51 AM UTC 24 |
Oct 15 09:37:39 AM UTC 24 |
86162500 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3016973668 |
|
|
Oct 15 09:35:03 AM UTC 24 |
Oct 15 09:37:39 AM UTC 24 |
98394100 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1085016156 |
|
|
Oct 15 09:35:19 AM UTC 24 |
Oct 15 09:37:39 AM UTC 24 |
43578700 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1430703870 |
|
|
Oct 15 09:34:56 AM UTC 24 |
Oct 15 09:37:48 AM UTC 24 |
78460000 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2602289007 |
|
|
Oct 15 09:35:15 AM UTC 24 |
Oct 15 09:37:51 AM UTC 24 |
36327800 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3437255686 |
|
|
Oct 15 09:35:10 AM UTC 24 |
Oct 15 09:37:51 AM UTC 24 |
168818300 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.1583069575 |
|
|
Oct 15 09:35:26 AM UTC 24 |
Oct 15 09:37:56 AM UTC 24 |
423444300 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.964903831 |
|
|
Oct 15 09:35:40 AM UTC 24 |
Oct 15 09:37:57 AM UTC 24 |
114171500 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.2867571214 |
|
|
Oct 15 09:35:00 AM UTC 24 |
Oct 15 09:37:59 AM UTC 24 |
141094100 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1502436570 |
|
|
Oct 15 09:35:04 AM UTC 24 |
Oct 15 09:37:59 AM UTC 24 |
71790000 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1993259847 |
|
|
Oct 15 09:35:27 AM UTC 24 |
Oct 15 09:38:07 AM UTC 24 |
134308100 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.4172419149 |
|
|
Oct 15 09:35:11 AM UTC 24 |
Oct 15 09:38:08 AM UTC 24 |
42126900 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.208650195 |
|
|
Oct 15 09:35:52 AM UTC 24 |
Oct 15 09:38:08 AM UTC 24 |
43076200 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1083380770 |
|
|
Oct 15 09:35:26 AM UTC 24 |
Oct 15 09:38:13 AM UTC 24 |
42906100 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.881283078 |
|
|
Oct 15 09:35:06 AM UTC 24 |
Oct 15 09:38:24 AM UTC 24 |
220051900 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1403110285 |
|
|
Oct 15 09:35:37 AM UTC 24 |
Oct 15 09:38:25 AM UTC 24 |
147317900 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1465095196 |
|
|
Oct 15 09:35:57 AM UTC 24 |
Oct 15 09:38:27 AM UTC 24 |
137236200 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3522482065 |
|
|
Oct 15 09:35:38 AM UTC 24 |
Oct 15 09:38:27 AM UTC 24 |
144009800 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.3799632653 |
|
|
Oct 15 09:35:32 AM UTC 24 |
Oct 15 09:38:28 AM UTC 24 |
56775300 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.961052216 |
|
|
Oct 15 09:35:50 AM UTC 24 |
Oct 15 09:38:37 AM UTC 24 |
81625200 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3240218276 |
|
|
Oct 15 09:35:42 AM UTC 24 |
Oct 15 09:38:38 AM UTC 24 |
38736500 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.3405672635 |
|
|
Oct 15 09:35:47 AM UTC 24 |
Oct 15 09:38:41 AM UTC 24 |
37238300 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.1914642007 |
|
|
Oct 15 09:36:01 AM UTC 24 |
Oct 15 09:38:43 AM UTC 24 |
40812100 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.2306309266 |
|
|
Oct 15 09:36:05 AM UTC 24 |
Oct 15 09:38:47 AM UTC 24 |
38447800 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.3304011486 |
|
|
Oct 15 09:33:29 AM UTC 24 |
Oct 15 09:38:50 AM UTC 24 |
48038600 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.1562104548 |
|
|
Oct 15 09:35:53 AM UTC 24 |
Oct 15 09:38:59 AM UTC 24 |
39075700 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2385588326 |
|
|
Oct 15 09:35:58 AM UTC 24 |
Oct 15 09:39:16 AM UTC 24 |
143321300 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.3685897122 |
|
|
Oct 15 08:45:31 AM UTC 24 |
Oct 15 09:39:56 AM UTC 24 |
3667018500 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3170081152 |
|
|
Oct 15 08:54:35 AM UTC 24 |
Oct 15 09:41:50 AM UTC 24 |
8733882900 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1768927651 |
|
|
Oct 15 08:58:06 AM UTC 24 |
Oct 15 09:47:04 AM UTC 24 |
2797532900 ps |
| T12 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.847055784 |
|
|
Oct 15 08:21:23 AM UTC 24 |
Oct 15 10:08:16 AM UTC 24 |
1044946000 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3749099413 |
|
|
Oct 15 08:26:07 AM UTC 24 |
Oct 15 10:11:47 AM UTC 24 |
8521785100 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.2727094603 |
|
|
Oct 15 08:30:24 AM UTC 24 |
Oct 15 10:20:51 AM UTC 24 |
19350731000 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.3185718600 |
|
|
Oct 15 08:35:35 AM UTC 24 |
Oct 15 10:30:44 AM UTC 24 |
6462979300 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.42111439 |
|
|
Oct 15 08:40:52 AM UTC 24 |
Oct 15 10:34:14 AM UTC 24 |
3260135600 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.2263356874 |
|
|
Oct 15 07:53:55 AM UTC 24 |
Oct 15 07:54:28 AM UTC 24 |
51008100 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3357406911 |
|
|
Oct 15 07:54:14 AM UTC 24 |
Oct 15 07:54:44 AM UTC 24 |
13921300 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.255040886 |
|
|
Oct 15 07:54:28 AM UTC 24 |
Oct 15 07:54:54 AM UTC 24 |
76013000 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.231659504 |
|
|
Oct 15 07:54:29 AM UTC 24 |
Oct 15 07:54:56 AM UTC 24 |
15987700 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.170986980 |
|
|
Oct 15 07:54:33 AM UTC 24 |
Oct 15 07:54:59 AM UTC 24 |
16084000 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1467189275 |
|
|
Oct 15 07:54:45 AM UTC 24 |
Oct 15 07:55:12 AM UTC 24 |
16225300 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.994787013 |
|
|
Oct 15 07:54:56 AM UTC 24 |
Oct 15 07:55:18 AM UTC 24 |
61374200 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3538866094 |
|
|
Oct 15 07:55:13 AM UTC 24 |
Oct 15 07:55:34 AM UTC 24 |
51711200 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1150565596 |
|
|
Oct 15 07:55:19 AM UTC 24 |
Oct 15 07:55:50 AM UTC 24 |
73175300 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2075630480 |
|
|
Oct 15 07:55:42 AM UTC 24 |
Oct 15 07:56:02 AM UTC 24 |
49858300 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2579553180 |
|
|
Oct 15 07:55:01 AM UTC 24 |
Oct 15 07:56:04 AM UTC 24 |
338172400 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3457586235 |
|
|
Oct 15 07:54:55 AM UTC 24 |
Oct 15 07:56:06 AM UTC 24 |
48729800 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1719218364 |
|
|
Oct 15 07:55:06 AM UTC 24 |
Oct 15 07:56:07 AM UTC 24 |
670448500 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1289571700 |
|
|
Oct 15 07:55:12 AM UTC 24 |
Oct 15 07:56:11 AM UTC 24 |
337852800 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2450280573 |
|
|
Oct 15 07:55:52 AM UTC 24 |
Oct 15 07:56:19 AM UTC 24 |
15013500 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1498695495 |
|
|
Oct 15 07:55:52 AM UTC 24 |
Oct 15 07:56:23 AM UTC 24 |
43386500 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3720672122 |
|
|
Oct 15 07:56:02 AM UTC 24 |
Oct 15 07:56:29 AM UTC 24 |
21563000 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2774930147 |
|
|
Oct 15 07:56:05 AM UTC 24 |
Oct 15 07:56:30 AM UTC 24 |
30219200 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1881845561 |
|
|
Oct 15 07:56:08 AM UTC 24 |
Oct 15 07:56:39 AM UTC 24 |
67580400 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3385367330 |
|
|
Oct 15 07:56:24 AM UTC 24 |
Oct 15 07:56:51 AM UTC 24 |
440672700 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.558313020 |
|
|
Oct 15 07:56:12 AM UTC 24 |
Oct 15 07:57:04 AM UTC 24 |
2798249600 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.3812869772 |
|
|
Oct 15 07:56:29 AM UTC 24 |
Oct 15 07:57:04 AM UTC 24 |
374755600 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3791465910 |
|
|
Oct 15 07:56:31 AM UTC 24 |
Oct 15 07:57:05 AM UTC 24 |
240751100 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2537402340 |
|
|
Oct 15 07:56:39 AM UTC 24 |
Oct 15 07:57:08 AM UTC 24 |
23868200 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2325159867 |
|
|
Oct 15 07:56:51 AM UTC 24 |
Oct 15 07:57:17 AM UTC 24 |
45488400 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3278613681 |
|
|
Oct 15 07:56:08 AM UTC 24 |
Oct 15 07:57:20 AM UTC 24 |
45417500 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3854678765 |
|
|
Oct 15 07:57:06 AM UTC 24 |
Oct 15 07:57:23 AM UTC 24 |
57393400 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.3018832662 |
|
|
Oct 15 07:57:00 AM UTC 24 |
Oct 15 07:57:26 AM UTC 24 |
25303000 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3280141830 |
|
|
Oct 15 07:57:06 AM UTC 24 |
Oct 15 07:57:28 AM UTC 24 |
48734500 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.3327584124 |
|
|
Oct 15 07:56:19 AM UTC 24 |
Oct 15 07:57:31 AM UTC 24 |
6350098800 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2752802140 |
|
|
Oct 15 07:57:10 AM UTC 24 |
Oct 15 07:57:38 AM UTC 24 |
43801900 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3253964456 |
|
|
Oct 15 07:57:07 AM UTC 24 |
Oct 15 07:57:52 AM UTC 24 |
34929900 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3441651524 |
|
|
Oct 15 07:57:23 AM UTC 24 |
Oct 15 07:57:56 AM UTC 24 |
103771300 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2050693226 |
|
|
Oct 15 07:57:29 AM UTC 24 |
Oct 15 07:57:59 AM UTC 24 |
584352300 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1026390200 |
|
|
Oct 15 07:57:27 AM UTC 24 |
Oct 15 07:58:01 AM UTC 24 |
169216900 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1446582602 |
|
|
Oct 15 07:57:42 AM UTC 24 |
Oct 15 07:58:02 AM UTC 24 |
15274200 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2767705264 |
|
|
Oct 15 07:57:38 AM UTC 24 |
Oct 15 07:58:09 AM UTC 24 |
14567000 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1922151960 |
|
|
Oct 15 07:57:18 AM UTC 24 |
Oct 15 07:58:09 AM UTC 24 |
2259696700 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4191813456 |
|
|
Oct 15 07:57:55 AM UTC 24 |
Oct 15 07:58:13 AM UTC 24 |
18026800 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.667041576 |
|
|
Oct 15 07:57:53 AM UTC 24 |
Oct 15 07:58:13 AM UTC 24 |
30208400 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1355428502 |
|
|
Oct 15 07:58:02 AM UTC 24 |
Oct 15 07:58:23 AM UTC 24 |
189794000 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1019176486 |
|
|
Oct 15 07:57:57 AM UTC 24 |
Oct 15 07:58:23 AM UTC 24 |
33042100 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.2367854691 |
|
|
Oct 15 07:58:14 AM UTC 24 |
Oct 15 07:58:37 AM UTC 24 |
114267600 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1390457973 |
|
|
Oct 15 07:57:21 AM UTC 24 |
Oct 15 07:58:41 AM UTC 24 |
1992537700 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.337297821 |
|
|
Oct 15 07:58:13 AM UTC 24 |
Oct 15 07:58:42 AM UTC 24 |
93390100 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.725487113 |
|
|
Oct 15 07:58:23 AM UTC 24 |
Oct 15 07:58:49 AM UTC 24 |
20497500 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1274001464 |
|
|
Oct 15 07:58:24 AM UTC 24 |
Oct 15 07:58:50 AM UTC 24 |
16115700 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.745769907 |
|
|
Oct 15 07:58:10 AM UTC 24 |
Oct 15 07:58:58 AM UTC 24 |
777185800 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1425431727 |
|
|
Oct 15 07:58:10 AM UTC 24 |
Oct 15 07:58:59 AM UTC 24 |
2628750500 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3809503638 |
|
|
Oct 15 07:58:00 AM UTC 24 |
Oct 15 07:59:01 AM UTC 24 |
50716800 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.4160407810 |
|
|
Oct 15 07:58:38 AM UTC 24 |
Oct 15 07:59:03 AM UTC 24 |
39461900 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1175601887 |
|
|
Oct 15 07:59:38 AM UTC 24 |
Oct 15 08:00:08 AM UTC 24 |
98872900 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.188114236 |
|
|
Oct 15 07:58:41 AM UTC 24 |
Oct 15 07:59:06 AM UTC 24 |
45695700 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3106310443 |
|
|
Oct 15 07:58:43 AM UTC 24 |
Oct 15 07:59:09 AM UTC 24 |
18430100 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.4230554284 |
|
|
Oct 15 07:58:50 AM UTC 24 |
Oct 15 07:59:12 AM UTC 24 |
57030200 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2528416524 |
|
|
Oct 15 07:58:03 AM UTC 24 |
Oct 15 07:59:30 AM UTC 24 |
660484500 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1229629533 |
|
|
Oct 15 07:59:04 AM UTC 24 |
Oct 15 07:59:34 AM UTC 24 |
55956200 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.919331328 |
|
|
Oct 15 07:59:10 AM UTC 24 |
Oct 15 07:59:36 AM UTC 24 |
13100900 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1919100206 |
|
|
Oct 15 07:59:04 AM UTC 24 |
Oct 15 07:59:37 AM UTC 24 |
57717300 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1800963594 |
|
|
Oct 15 07:59:02 AM UTC 24 |
Oct 15 07:59:42 AM UTC 24 |
223908100 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1599841892 |
|
|
Oct 15 07:59:13 AM UTC 24 |
Oct 15 07:59:44 AM UTC 24 |
86529800 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.2597709987 |
|
|
Oct 15 07:59:26 AM UTC 24 |
Oct 15 07:59:52 AM UTC 24 |
14952900 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4268617381 |
|
|
Oct 15 07:59:37 AM UTC 24 |
Oct 15 07:59:59 AM UTC 24 |
62058400 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.163082657 |
|
|
Oct 15 07:59:31 AM UTC 24 |
Oct 15 08:00:01 AM UTC 24 |
347381600 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3250769011 |
|
|
Oct 15 07:58:49 AM UTC 24 |
Oct 15 08:00:11 AM UTC 24 |
140829900 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.794358227 |
|
|
Oct 15 07:59:45 AM UTC 24 |
Oct 15 08:00:11 AM UTC 24 |
138094200 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.1988770573 |
|
|
Oct 15 07:59:43 AM UTC 24 |
Oct 15 08:00:12 AM UTC 24 |
19810300 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2614470887 |
|
|
Oct 15 07:59:53 AM UTC 24 |
Oct 15 08:00:19 AM UTC 24 |
53582200 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1880526596 |
|
|
Oct 15 07:59:00 AM UTC 24 |
Oct 15 08:00:23 AM UTC 24 |
415905800 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.621281972 |
|
|
Oct 15 08:00:00 AM UTC 24 |
Oct 15 08:00:26 AM UTC 24 |
38602500 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1211773036 |
|
|
Oct 15 08:00:02 AM UTC 24 |
Oct 15 08:00:27 AM UTC 24 |
181276200 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3564055594 |
|
|
Oct 15 07:58:59 AM UTC 24 |
Oct 15 08:00:30 AM UTC 24 |
2197112400 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.2962915614 |
|
|
Oct 15 07:59:36 AM UTC 24 |
Oct 15 08:00:32 AM UTC 24 |
544918300 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.2755260249 |
|
|
Oct 15 08:00:12 AM UTC 24 |
Oct 15 08:00:42 AM UTC 24 |
38805000 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.66189362 |
|
|
Oct 15 08:00:19 AM UTC 24 |
Oct 15 08:00:43 AM UTC 24 |
36133400 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3034857487 |
|
|
Oct 15 08:00:13 AM UTC 24 |
Oct 15 08:00:43 AM UTC 24 |
37184600 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2456701905 |
|
|
Oct 15 08:00:20 AM UTC 24 |
Oct 15 08:00:44 AM UTC 24 |
15433300 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.142689126 |
|
|
Oct 15 08:00:09 AM UTC 24 |
Oct 15 08:00:44 AM UTC 24 |
428245200 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4108598099 |
|
|
Oct 15 08:00:24 AM UTC 24 |
Oct 15 08:00:47 AM UTC 24 |
39872200 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.613680846 |
|
|
Oct 15 08:00:28 AM UTC 24 |
Oct 15 08:00:57 AM UTC 24 |
120592200 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.547584529 |
|
|
Oct 15 08:00:44 AM UTC 24 |
Oct 15 08:01:01 AM UTC 24 |
31442600 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1486376768 |
|
|
Oct 15 08:00:27 AM UTC 24 |
Oct 15 08:01:02 AM UTC 24 |
395228000 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2279456184 |
|
|
Oct 15 08:00:33 AM UTC 24 |
Oct 15 08:01:02 AM UTC 24 |
13638200 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.238866307 |
|
|
Oct 15 08:00:32 AM UTC 24 |
Oct 15 08:01:04 AM UTC 24 |
58519200 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3310680166 |
|
|
Oct 15 08:00:45 AM UTC 24 |
Oct 15 08:01:06 AM UTC 24 |
826867000 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2248530785 |
|
|
Oct 15 08:00:44 AM UTC 24 |
Oct 15 08:01:08 AM UTC 24 |
85020600 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1621233533 |
|
|
Oct 15 08:00:43 AM UTC 24 |
Oct 15 08:01:09 AM UTC 24 |
34726800 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2089429932 |
|
|
Oct 15 08:00:45 AM UTC 24 |
Oct 15 08:01:20 AM UTC 24 |
311778300 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.229209655 |
|
|
Oct 15 08:01:02 AM UTC 24 |
Oct 15 08:01:22 AM UTC 24 |
25204500 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.2963432804 |
|
|
Oct 15 08:01:05 AM UTC 24 |
Oct 15 08:01:22 AM UTC 24 |
15729300 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3169262402 |
|
|
Oct 15 08:00:48 AM UTC 24 |
Oct 15 08:01:24 AM UTC 24 |
62709700 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.2141483318 |
|
|
Oct 15 08:01:02 AM UTC 24 |
Oct 15 08:01:32 AM UTC 24 |
26197700 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3096683838 |
|
|
Oct 15 08:01:08 AM UTC 24 |
Oct 15 08:01:34 AM UTC 24 |
35054500 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.4066302104 |
|
|
Oct 15 08:01:05 AM UTC 24 |
Oct 15 08:01:35 AM UTC 24 |
62593700 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.191039471 |
|
|
Oct 15 08:01:06 AM UTC 24 |
Oct 15 08:01:37 AM UTC 24 |
107208200 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.643819681 |
|
|
Oct 15 08:01:25 AM UTC 24 |
Oct 15 08:01:45 AM UTC 24 |
21426200 ps |
| T338 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.622192047 |
|
|
Oct 15 08:01:23 AM UTC 24 |
Oct 15 08:01:48 AM UTC 24 |
47868800 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1231200367 |
|
|
Oct 15 08:01:21 AM UTC 24 |
Oct 15 08:01:49 AM UTC 24 |
82800500 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.191114619 |
|
|
Oct 15 08:01:23 AM UTC 24 |
Oct 15 08:01:51 AM UTC 24 |
76007700 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1181560223 |
|
|
Oct 15 08:01:05 AM UTC 24 |
Oct 15 08:01:52 AM UTC 24 |
166280900 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1526635713 |
|
|
Oct 15 08:01:33 AM UTC 24 |
Oct 15 08:02:02 AM UTC 24 |
351006900 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2598350794 |
|
|
Oct 15 08:01:36 AM UTC 24 |
Oct 15 08:02:03 AM UTC 24 |
346393200 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3279989923 |
|
|
Oct 15 08:01:35 AM UTC 24 |
Oct 15 08:02:08 AM UTC 24 |
352310700 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.390095843 |
|
|
Oct 15 08:01:45 AM UTC 24 |
Oct 15 08:02:10 AM UTC 24 |
37477700 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.216928041 |
|
|
Oct 15 08:01:51 AM UTC 24 |
Oct 15 08:02:16 AM UTC 24 |
200391800 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4228520673 |
|
|
Oct 15 08:01:49 AM UTC 24 |
Oct 15 08:02:16 AM UTC 24 |
24656300 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.607351294 |
|
|
Oct 15 08:01:50 AM UTC 24 |
Oct 15 08:02:17 AM UTC 24 |
47669100 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2879464944 |
|
|
Oct 15 08:02:02 AM UTC 24 |
Oct 15 08:02:25 AM UTC 24 |
53632300 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2003569296 |
|
|
Oct 15 08:01:53 AM UTC 24 |
Oct 15 08:02:28 AM UTC 24 |
354616500 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2506942303 |
|
|
Oct 15 08:02:09 AM UTC 24 |
Oct 15 08:02:36 AM UTC 24 |
13916600 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2761639151 |
|
|
Oct 15 08:02:03 AM UTC 24 |
Oct 15 08:02:40 AM UTC 24 |
61775900 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2971667415 |
|
|
Oct 15 08:02:11 AM UTC 24 |
Oct 15 08:02:41 AM UTC 24 |
40682600 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3725540512 |
|
|
Oct 15 08:02:16 AM UTC 24 |
Oct 15 08:02:42 AM UTC 24 |
260027000 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2092941346 |
|
|
Oct 15 08:02:16 AM UTC 24 |
Oct 15 08:02:50 AM UTC 24 |
710437100 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4111988585 |
|
|
Oct 15 08:02:18 AM UTC 24 |
Oct 15 08:02:51 AM UTC 24 |
56684600 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1569919296 |
|
|
Oct 15 08:02:25 AM UTC 24 |
Oct 15 08:02:59 AM UTC 24 |
314151900 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1523931065 |
|
|
Oct 15 08:02:41 AM UTC 24 |
Oct 15 08:03:00 AM UTC 24 |
102825600 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.155661186 |
|
|
Oct 15 08:02:43 AM UTC 24 |
Oct 15 08:03:05 AM UTC 24 |
37512600 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1665012965 |
|
|
Oct 15 08:02:42 AM UTC 24 |
Oct 15 08:03:06 AM UTC 24 |
42826800 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.843573696 |
|
|
Oct 15 08:02:36 AM UTC 24 |
Oct 15 08:03:06 AM UTC 24 |
14385100 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.145615368 |
|
|
Oct 15 08:02:17 AM UTC 24 |
Oct 15 08:03:12 AM UTC 24 |
121444400 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3730140269 |
|
|
Oct 15 08:02:52 AM UTC 24 |
Oct 15 08:03:19 AM UTC 24 |
81585300 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2257222017 |
|
|
Oct 15 08:02:51 AM UTC 24 |
Oct 15 08:03:22 AM UTC 24 |
164660400 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.586021886 |
|
|
Oct 15 08:03:07 AM UTC 24 |
Oct 15 08:03:24 AM UTC 24 |
30771700 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.288593872 |
|
|
Oct 15 08:03:00 AM UTC 24 |
Oct 15 08:03:26 AM UTC 24 |
76334400 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1159586549 |
|
|
Oct 15 08:03:06 AM UTC 24 |
Oct 15 08:03:32 AM UTC 24 |
23351000 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.770670329 |
|
|
Oct 15 08:03:06 AM UTC 24 |
Oct 15 08:03:36 AM UTC 24 |
14587700 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.791315455 |
|
|
Oct 15 08:03:12 AM UTC 24 |
Oct 15 08:03:41 AM UTC 24 |
61550700 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2438663761 |
|
|
Oct 15 08:03:23 AM UTC 24 |
Oct 15 08:03:53 AM UTC 24 |
492715100 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1393238137 |
|
|
Oct 15 08:03:25 AM UTC 24 |
Oct 15 08:03:59 AM UTC 24 |
62104900 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.46537343 |
|
|
Oct 15 08:03:19 AM UTC 24 |
Oct 15 08:04:01 AM UTC 24 |
61724200 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2788649973 |
|
|
Oct 15 08:03:33 AM UTC 24 |
Oct 15 08:04:03 AM UTC 24 |
18800100 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.387763507 |
|
|
Oct 15 08:03:37 AM UTC 24 |
Oct 15 08:04:05 AM UTC 24 |
83586100 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3461890324 |
|
|
Oct 15 08:03:41 AM UTC 24 |
Oct 15 08:04:05 AM UTC 24 |
44516100 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.440225730 |
|
|
Oct 15 08:03:54 AM UTC 24 |
Oct 15 08:04:20 AM UTC 24 |
20819400 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3722396888 |
|
|
Oct 15 08:04:02 AM UTC 24 |
Oct 15 08:04:27 AM UTC 24 |
24606100 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.54119600 |
|
|
Oct 15 08:04:00 AM UTC 24 |
Oct 15 08:04:29 AM UTC 24 |
184774900 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2159832662 |
|
|
Oct 15 08:04:04 AM UTC 24 |
Oct 15 08:04:33 AM UTC 24 |
48828700 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1088102686 |
|
|
Oct 15 08:04:06 AM UTC 24 |
Oct 15 08:04:35 AM UTC 24 |
13710400 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.170839675 |
|
|
Oct 15 08:04:05 AM UTC 24 |
Oct 15 08:04:35 AM UTC 24 |
94826800 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2270779016 |
|
|
Oct 15 08:04:13 AM UTC 24 |
Oct 15 08:04:40 AM UTC 24 |
17324000 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3906060242 |
|
|
Oct 15 08:04:22 AM UTC 24 |
Oct 15 08:04:50 AM UTC 24 |
67722800 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.893436568 |
|
|
Oct 15 08:04:27 AM UTC 24 |
Oct 15 08:04:51 AM UTC 24 |
64357700 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.8286275 |
|
|
Oct 15 08:04:35 AM UTC 24 |
Oct 15 08:04:52 AM UTC 24 |
91852100 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.230001932 |
|
|
Oct 15 08:04:25 AM UTC 24 |
Oct 15 08:04:54 AM UTC 24 |
37123200 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1757989556 |
|
|
Oct 15 08:04:30 AM UTC 24 |
Oct 15 08:05:01 AM UTC 24 |
42829100 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2519290805 |
|
|
Oct 15 08:04:35 AM UTC 24 |
Oct 15 08:05:01 AM UTC 24 |
31232600 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2399508678 |
|
|
Oct 15 08:04:36 AM UTC 24 |
Oct 15 08:05:03 AM UTC 24 |
17628700 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2185351053 |
|
|
Oct 15 08:04:40 AM UTC 24 |
Oct 15 08:05:08 AM UTC 24 |
137116000 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2881802349 |
|
|
Oct 15 08:04:53 AM UTC 24 |
Oct 15 08:05:13 AM UTC 24 |
45960100 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3508449545 |
|
|
Oct 15 08:04:57 AM UTC 24 |
Oct 15 08:05:15 AM UTC 24 |
22818600 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.773003334 |
|
|
Oct 15 08:04:51 AM UTC 24 |
Oct 15 08:05:18 AM UTC 24 |
42326600 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2220276555 |
|
|
Oct 15 08:05:02 AM UTC 24 |
Oct 15 08:05:20 AM UTC 24 |
33638400 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2673826311 |
|
|
Oct 15 08:05:03 AM UTC 24 |
Oct 15 08:05:25 AM UTC 24 |
120749100 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1885604557 |
|
|
Oct 15 08:04:52 AM UTC 24 |
Oct 15 08:05:28 AM UTC 24 |
45620300 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.23968450 |
|
|
Oct 15 08:05:02 AM UTC 24 |
Oct 15 08:05:32 AM UTC 24 |
11592500 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3359988864 |
|
|
Oct 15 08:05:14 AM UTC 24 |
Oct 15 08:05:36 AM UTC 24 |
151686700 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.929159876 |
|
|
Oct 15 08:05:16 AM UTC 24 |
Oct 15 08:05:39 AM UTC 24 |
67829400 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3539822673 |
|
|
Oct 15 08:05:08 AM UTC 24 |
Oct 15 08:05:46 AM UTC 24 |
739763400 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2451995335 |
|
|
Oct 15 08:05:21 AM UTC 24 |
Oct 15 08:05:47 AM UTC 24 |
26761400 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4052207120 |
|
|
Oct 15 08:05:25 AM UTC 24 |
Oct 15 08:05:48 AM UTC 24 |
40801000 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.449049015 |
|
|
Oct 15 08:05:30 AM UTC 24 |
Oct 15 08:05:53 AM UTC 24 |
32507200 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3953689681 |
|
|
Oct 15 08:05:36 AM UTC 24 |
Oct 15 08:05:59 AM UTC 24 |
237621700 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3335965518 |
|
|
Oct 15 08:05:33 AM UTC 24 |
Oct 15 08:06:00 AM UTC 24 |
98214300 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1188833987 |
|
|
Oct 15 08:05:41 AM UTC 24 |
Oct 15 08:06:01 AM UTC 24 |
17812200 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1973770684 |
|
|
Oct 15 08:05:36 AM UTC 24 |
Oct 15 08:06:02 AM UTC 24 |
37331200 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.3175573290 |
|
|
Oct 15 08:05:41 AM UTC 24 |
Oct 15 08:06:06 AM UTC 24 |
34924900 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3477615607 |
|
|
Oct 15 08:05:48 AM UTC 24 |
Oct 15 08:06:07 AM UTC 24 |
27717500 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2418090511 |
|
|
Oct 15 08:05:46 AM UTC 24 |
Oct 15 08:06:10 AM UTC 24 |
56670400 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1553992452 |
|
|
Oct 15 08:05:47 AM UTC 24 |
Oct 15 08:06:10 AM UTC 24 |
15757000 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.1358821423 |
|
|
Oct 15 08:05:53 AM UTC 24 |
Oct 15 08:06:12 AM UTC 24 |
48359900 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3907476485 |
|
|
Oct 15 08:05:46 AM UTC 24 |
Oct 15 08:06:13 AM UTC 24 |
86845800 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.277383860 |
|
|
Oct 15 08:06:01 AM UTC 24 |
Oct 15 08:06:21 AM UTC 24 |
18064000 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2313652865 |
|
|
Oct 15 08:06:02 AM UTC 24 |
Oct 15 08:06:22 AM UTC 24 |
80492700 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.627448197 |
|
|
Oct 15 08:06:04 AM UTC 24 |
Oct 15 08:06:23 AM UTC 24 |
15625100 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.658874871 |
|
|
Oct 15 08:06:00 AM UTC 24 |
Oct 15 08:06:24 AM UTC 24 |
84181900 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2758375927 |
|
|
Oct 15 08:06:07 AM UTC 24 |
Oct 15 08:06:26 AM UTC 24 |
53499100 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1419115129 |
|
|
Oct 15 08:06:08 AM UTC 24 |
Oct 15 08:06:26 AM UTC 24 |
27428900 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.435631460 |
|
|
Oct 15 08:06:12 AM UTC 24 |
Oct 15 08:06:30 AM UTC 24 |
25220000 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.983884865 |
|
|
Oct 15 08:06:14 AM UTC 24 |
Oct 15 08:06:31 AM UTC 24 |
40609500 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.179459435 |
|
|
Oct 15 08:06:14 AM UTC 24 |
Oct 15 08:06:37 AM UTC 24 |
59758800 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.620464639 |
|
|
Oct 15 08:06:13 AM UTC 24 |
Oct 15 08:06:38 AM UTC 24 |
44806100 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.946086193 |
|
|
Oct 15 08:06:13 AM UTC 24 |
Oct 15 08:06:40 AM UTC 24 |
15794900 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.4170374599 |
|
|
Oct 15 08:06:25 AM UTC 24 |
Oct 15 08:06:42 AM UTC 24 |
30370900 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.405940950 |
|
|
Oct 15 08:06:24 AM UTC 24 |
Oct 15 08:06:42 AM UTC 24 |
26339100 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.748733741 |
|
|
Oct 15 08:06:27 AM UTC 24 |
Oct 15 08:06:44 AM UTC 24 |
21528300 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3338225520 |
|
|
Oct 15 07:57:32 AM UTC 24 |
Oct 15 08:06:45 AM UTC 24 |
414706600 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.2513757932 |
|
|
Oct 15 08:06:23 AM UTC 24 |
Oct 15 08:06:45 AM UTC 24 |
28958400 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.1894029306 |
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|
Oct 15 08:06:25 AM UTC 24 |
Oct 15 08:06:46 AM UTC 24 |
63925500 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.3220505835 |
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|
Oct 15 08:06:23 AM UTC 24 |
Oct 15 08:06:47 AM UTC 24 |
17358000 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2959511601 |
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|
Oct 15 08:06:27 AM UTC 24 |
Oct 15 08:06:53 AM UTC 24 |
129211900 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.735512836 |
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|
Oct 15 08:06:31 AM UTC 24 |
Oct 15 08:06:55 AM UTC 24 |
15559500 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.1178976886 |
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|
Oct 15 08:06:38 AM UTC 24 |
Oct 15 08:06:57 AM UTC 24 |
55208500 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.3276461086 |
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|
Oct 15 08:06:38 AM UTC 24 |
Oct 15 08:06:59 AM UTC 24 |
17323000 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2259335663 |
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|
Oct 15 08:06:32 AM UTC 24 |
Oct 15 08:06:59 AM UTC 24 |
32029800 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.3940472166 |
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|
Oct 15 08:06:40 AM UTC 24 |
Oct 15 08:07:05 AM UTC 24 |
62150800 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.486410241 |
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|
Oct 15 08:00:12 AM UTC 24 |
Oct 15 08:08:24 AM UTC 24 |
4194368100 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.902709912 |
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|
Oct 15 07:59:42 AM UTC 24 |
Oct 15 08:08:26 AM UTC 24 |
1608462000 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.64232652 |
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|
Oct 15 07:58:16 AM UTC 24 |
Oct 15 08:10:14 AM UTC 24 |
239039900 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1984266487 |
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Oct 15 08:04:04 AM UTC 24 |
Oct 15 08:12:08 AM UTC 24 |
718630300 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.220750983 |
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|
Oct 15 07:54:02 AM UTC 24 |
Oct 15 08:13:07 AM UTC 24 |
1680505300 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.2194359236 |
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Oct 15 08:05:18 AM UTC 24 |
Oct 15 08:14:43 AM UTC 24 |
491143300 ps |