Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	412121	1		T1	1		T2	2		T3	2
all_values[1]	412121	1		T1	1		T2	2		T3	2
all_values[2]	412121	1		T1	1		T2	2		T3	2
all_values[3]	412121	1		T1	1		T2	2		T3	2
all_values[4]	412121	1		T1	1		T2	2		T3	2
all_values[5]	412121	1		T1	1		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	830655	1		T1	6		T2	12		T3	12
auto[1]	1642071	1		T33	6204		T44	25064		T45	960

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1213624	1		T1	4		T2	7		T3	7
auto[1]	1259102	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	411964	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	157	1		T269	5		T270	3		T277	3
all_values[1]	auto[0]	auto[1]	411962	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	159	1		T269	3		T270	2		T337	6
all_values[2]	auto[0]	auto[0]	1620	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	66	1		T269	3		T270	1		T338	1
all_values[2]	auto[1]	auto[0]	410381	1		T33	1551		T44	6266		T45	240
all_values[2]	auto[1]	auto[1]	54	1		T269	3		T270	2		T337	3
all_values[3]	auto[0]	auto[0]	1616	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	55	1		T270	1		T277	1		T337	2
all_values[3]	auto[1]	auto[0]	87772	1		T33	1551		T44	17		T45	80
all_values[3]	auto[1]	auto[1]	322678	1		T44	6249		T45	160		T47	1076
all_values[4]	auto[0]	auto[0]	1140	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	544	1		T2	1		T3	1		T16	1
all_values[4]	auto[1]	auto[0]	299153	1		T33	1		T44	5691		T45	160
all_values[4]	auto[1]	auto[1]	111284	1		T33	1550		T44	575		T45	80
all_values[5]	auto[0]	auto[0]	1578	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	110	1		T48	1		T50	1		T72	1
all_values[5]	auto[1]	auto[0]	410364	1		T33	1551		T44	6266		T45	240
all_values[5]	auto[1]	auto[1]	69	1		T269	2		T337	3		T338	2