Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	321026	1		T1	1		T2	2		T3	2
all_values[1]	321026	1		T1	1		T2	2		T3	2
all_values[2]	321026	1		T1	1		T2	2		T3	2
all_values[3]	321026	1		T1	1		T2	2		T3	2
all_values[4]	321026	1		T1	1		T2	2		T3	2
all_values[5]	321026	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	648409	1		T1	6		T2	12		T3	12
auto[1]	1277747	1		T44	6500		T52	12896		T45	6044

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	938531	1		T1	4		T2	7		T3	7
auto[1]	987625	1		T1	2		T2	5		T3	5

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Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	320870	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	156	1		T262	1		T269	1		T331	6
all_values[1]	auto[0]	auto[1]	320858	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	168	1		T262	4		T269	1		T331	2
all_values[2]	auto[0]	auto[0]	1610	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	56	1		T262	2		T269	1		T331	3
all_values[2]	auto[1]	auto[0]	319296	1		T44	1625		T52	3224		T45	1511
all_values[2]	auto[1]	auto[1]	64	1		T262	1		T269	1		T331	2
all_values[3]	auto[0]	auto[0]	1626	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	58	1		T262	1		T269	1		T332	3
all_values[3]	auto[1]	auto[0]	74392	1		T44	1625		T52	1612		T45	1511
all_values[3]	auto[1]	auto[1]	244950	1		T52	1612		T53	3389		T54	39402
all_values[4]	auto[0]	auto[0]	1134	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	547	1		T2	1		T3	1		T15	1
all_values[4]	auto[1]	auto[0]	219643	1		T44	1		T52	1612		T45	1
all_values[4]	auto[1]	auto[1]	99702	1		T44	1624		T52	1612		T45	1510
all_values[5]	auto[0]	auto[0]	1552	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	98	1		T11	1		T55	1		T110	1
all_values[5]	auto[1]	auto[0]	319278	1		T44	1625		T52	3224		T45	1511
all_values[5]	auto[1]	auto[1]	98	1		T262	3		T269	3		T331	2