Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
88.24	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	4	20	83.33

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	24	4	20	83.33	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	311323	1		T1	1		T2	2		T3	2
all_values[1]	311323	1		T1	1		T2	2		T3	2
all_values[2]	311323	1		T1	1		T2	2		T3	2
all_values[3]	311323	1		T1	1		T2	2		T3	2
all_values[4]	311323	1		T1	1		T2	2		T3	2
all_values[5]	311323	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	628989	1		T1	6		T2	12		T3	12
auto[1]	1238949	1		T33	6412		T46	8452		T38	5308

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Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	915583	1		T1	4		T2	7		T3	7
auto[1]	952355	1		T1	2		T2	5		T3	5

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	4	20	83.33	4

Automatically Generated Cross Bins for intr_cg_cc

Element holes

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	*	[auto[0]]	--	--	4

Covered bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[1]	311179	1		T1	1		T2	2		T3	2
all_values[0]	auto[1]	auto[1]	144	1		T339	2		T340	2		T341	5
all_values[1]	auto[0]	auto[1]	311201	1		T1	1		T2	2		T3	2
all_values[1]	auto[1]	auto[1]	122	1		T250	1		T257	2		T340	2
all_values[2]	auto[0]	auto[0]	1592	1		T1	1		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	47	1		T250	2		T257	1		T340	1
all_values[2]	auto[1]	auto[0]	309630	1		T33	1603		T46	2113		T38	1327
all_values[2]	auto[1]	auto[1]	54	1		T257	1		T340	1		T341	1
all_values[3]	auto[0]	auto[0]	1613	1		T1	1		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	44	1		T250	1		T339	2		T340	1
all_values[3]	auto[1]	auto[0]	78588	1		T33	1603		T46	455		T38	1327
all_values[3]	auto[1]	auto[1]	231078	1		T46	1658		T48	1813		T49	40891
all_values[4]	auto[0]	auto[0]	1125	1		T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	529	1		T2	1		T3	1		T8	1
all_values[4]	auto[1]	auto[0]	211846	1		T33	1		T46	1537		T38	1
all_values[4]	auto[1]	auto[1]	97823	1		T33	1602		T46	576		T38	1326
all_values[5]	auto[0]	auto[0]	1583	1		T1	1		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	76	1		T50	1		T51	1		T52	1
all_values[5]	auto[1]	auto[0]	309606	1		T33	1603		T46	2113		T38	1327
all_values[5]	auto[1]	auto[1]	58	1		T250	1		T341	3		T342	2