| Name |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3457586235 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3538866094 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.994787013 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.231659504 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.170986980 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.1289571700 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3357406911 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.255040886 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.220750983 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.3278613681 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1881845561 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.2450280573 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.2774930147 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.3720672122 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3385367330 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2075630480 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1498695495 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.1040635435 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3279989923 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.643819681 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.622192047 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.1526635713 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1231200367 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.191114619 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.3096683838 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.842554659 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2879464944 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.216928041 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.607351294 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.2003569296 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.390095843 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.4228520673 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.2598350794 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2350634317 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.4111988585 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2092941346 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.3725540512 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.145615368 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2506942303 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.2971667415 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2761639151 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3787835457 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.3730140269 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.155661186 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1665012965 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.2257222017 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.843573696 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1523931065 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1569919296 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1122087714 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2438663761 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.791315455 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.586021886 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.46537343 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1159586549 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.770670329 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.288593872 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3722396888 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.440225730 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3461890324 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.54119600 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2788649973 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.387763507 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1393238137 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1920094987 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.893436568 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3906060242 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2270779016 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.230001932 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.170839675 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1088102686 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2159832662 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1984266487 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1885604557 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.2185351053 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.2399508678 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.773003334 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2519290805 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.8286275 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1757989556 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3359988864 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2673826311 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2220276555 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.3539822673 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3508449545 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.23968450 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2881802349 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.1461097402 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.1973770684 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.3335965518 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.449049015 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.3953689681 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2451995335 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.4052207120 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.929159876 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.1390457973 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1922151960 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.3253964456 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1026390200 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2752802140 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3280141830 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3854678765 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3441651524 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2537402340 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2325159867 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3791465910 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.3175573290 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1188833987 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3907476485 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2418090511 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.1553992452 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3477615607 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.1358821423 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.658874871 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.277383860 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2313652865 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.1425431727 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.3809503638 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.337297821 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1355428502 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.667041576 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1019176486 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4191813456 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.745769907 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2767705264 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1446582602 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2050693226 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.3338225520 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.627448197 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.2758375927 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.1419115129 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.435631460 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.620464639 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.946086193 |
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| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.1862383671 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.57287488 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.524034959 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2602289007 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.2841936515 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1085016156 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.431744652 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1083380770 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.1076760195 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.1583069575 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.1097796240 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1993259847 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.3872173810 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.3799632653 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.612562704 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1403110285 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.9601461 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.3522482065 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.554862375 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.3212435933 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.3045588780 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.118925310 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.210685388 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.867428943 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.605239369 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3028104582 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3844058114 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.3366018906 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1538481227 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.1352967797 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.3469031966 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.1270356747 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1426656518 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1549949488 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.647552596 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.3906945350 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.932590746 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.2809098156 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.827605392 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.303073883 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1696328967 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3002347780 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.2420698567 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.3874653086 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.3696061122 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.1865494123 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.4135668436 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.2109362207 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.964903831 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.1838547359 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3240218276 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.2911716119 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.3405672635 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.610290311 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.961052216 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3533823604 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.208650195 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.1946973535 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.1562104548 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.1467916258 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.1465095196 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.3084513489 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2385588326 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.501341440 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.1914642007 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.27554988 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.2306309266 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3504035362 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.1437846764 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.1680750492 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3170081152 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.2478148321 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3459880435 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2264037874 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.284309867 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2561125865 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.44303185 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1003852915 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.887971465 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.496255540 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.4019327394 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.946553202 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1732597384 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3658770172 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.2078564359 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.4083739410 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.2861229984 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.3448930709 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1562743040 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.2730863485 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.2420520638 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.4189842455 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.3049269361 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1459561543 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3255206464 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.2998282870 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.3242559832 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.1832129734 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.3635633397 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.4008298094 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.943204756 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.1495221078 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.1768927651 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.302943240 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1249068295 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.1694395977 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3164915259 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.242465569 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.1705201180 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3820869838 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1359761470 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2771864526 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.114693126 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2476218835 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2811520155 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.3356281500 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.753947342 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.788722403 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.4100512431 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.129303641 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3407505349 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1336131464 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.1827376721 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.1844905712 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.672388769 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.397048670 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.629916761 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1145345108 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.2881463619 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3312578253 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.4260815087 |
| /workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1751949482 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.333387439 |
|
|
Oct 15 08:17:00 AM UTC 24 |
Oct 15 08:17:33 AM UTC 24 |
15802300 ps |
| T2 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.4142222960 |
|
|
Oct 15 08:17:03 AM UTC 24 |
Oct 15 08:17:54 AM UTC 24 |
39889800 ps |
| T3 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1720338520 |
|
|
Oct 15 08:17:33 AM UTC 24 |
Oct 15 08:18:19 AM UTC 24 |
1376998600 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.861381239 |
|
|
Oct 15 08:16:59 AM UTC 24 |
Oct 15 08:18:27 AM UTC 24 |
121498100 ps |
| T9 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.4203720627 |
|
|
Oct 15 08:18:28 AM UTC 24 |
Oct 15 08:18:56 AM UTC 24 |
45221700 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.2564533186 |
|
|
Oct 15 08:18:31 AM UTC 24 |
Oct 15 08:18:58 AM UTC 24 |
41455200 ps |
| T10 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.3008128612 |
|
|
Oct 15 08:17:03 AM UTC 24 |
Oct 15 08:19:52 AM UTC 24 |
261194100 ps |
| T17 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.3767536671 |
|
|
Oct 15 08:19:09 AM UTC 24 |
Oct 15 08:19:52 AM UTC 24 |
133520200 ps |
| T18 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.2676791039 |
|
|
Oct 15 08:18:16 AM UTC 24 |
Oct 15 08:19:55 AM UTC 24 |
4888018900 ps |
| T4 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.44687840 |
|
|
Oct 15 08:17:18 AM UTC 24 |
Oct 15 08:20:09 AM UTC 24 |
43043400 ps |
| T20 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.57533282 |
|
|
Oct 15 08:17:03 AM UTC 24 |
Oct 15 08:20:12 AM UTC 24 |
5511492000 ps |
| T26 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2874501101 |
|
|
Oct 15 08:18:20 AM UTC 24 |
Oct 15 08:20:20 AM UTC 24 |
3944362600 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.210061485 |
|
|
Oct 15 08:19:56 AM UTC 24 |
Oct 15 08:20:37 AM UTC 24 |
30554300 ps |
| T11 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2191723950 |
|
|
Oct 15 08:19:53 AM UTC 24 |
Oct 15 08:20:47 AM UTC 24 |
463444400 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.782205732 |
|
|
Oct 15 08:17:30 AM UTC 24 |
Oct 15 08:20:54 AM UTC 24 |
37706631800 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.1144065921 |
|
|
Oct 15 08:19:53 AM UTC 24 |
Oct 15 08:21:00 AM UTC 24 |
731283700 ps |
| T27 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.1221017022 |
|
|
Oct 15 08:17:07 AM UTC 24 |
Oct 15 08:21:21 AM UTC 24 |
14227875800 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.500085504 |
|
|
Oct 15 08:20:58 AM UTC 24 |
Oct 15 08:21:21 AM UTC 24 |
146210300 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.2084835346 |
|
|
Oct 15 08:18:57 AM UTC 24 |
Oct 15 08:21:36 AM UTC 24 |
525028200 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.287700211 |
|
|
Oct 15 08:17:03 AM UTC 24 |
Oct 15 08:21:50 AM UTC 24 |
114450600 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.232336290 |
|
|
Oct 15 08:21:18 AM UTC 24 |
Oct 15 08:21:54 AM UTC 24 |
42779100 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.999305101 |
|
|
Oct 15 08:21:00 AM UTC 24 |
Oct 15 08:21:56 AM UTC 24 |
28001200 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.1103510052 |
|
|
Oct 15 08:18:27 AM UTC 24 |
Oct 15 08:21:58 AM UTC 24 |
29261769600 ps |
| T5 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.354191537 |
|
|
Oct 15 08:21:22 AM UTC 24 |
Oct 15 08:22:02 AM UTC 24 |
29170200 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.894806430 |
|
|
Oct 15 08:19:21 AM UTC 24 |
Oct 15 08:22:06 AM UTC 24 |
737846200 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.232664969 |
|
|
Oct 15 08:21:20 AM UTC 24 |
Oct 15 08:22:08 AM UTC 24 |
274153000 ps |
| T23 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3457436874 |
|
|
Oct 15 08:21:53 AM UTC 24 |
Oct 15 08:22:14 AM UTC 24 |
32252400 ps |
| T6 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.3268672156 |
|
|
Oct 15 08:21:54 AM UTC 24 |
Oct 15 08:22:20 AM UTC 24 |
148898100 ps |
| T7 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.3823663193 |
|
|
Oct 15 08:21:56 AM UTC 24 |
Oct 15 08:22:21 AM UTC 24 |
12059500 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.2064668589 |
|
|
Oct 15 08:22:03 AM UTC 24 |
Oct 15 08:22:25 AM UTC 24 |
844067200 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.3425043236 |
|
|
Oct 15 08:20:48 AM UTC 24 |
Oct 15 08:22:33 AM UTC 24 |
9945345400 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2314338414 |
|
|
Oct 15 08:22:08 AM UTC 24 |
Oct 15 08:22:35 AM UTC 24 |
194593800 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.1158029578 |
|
|
Oct 15 08:22:08 AM UTC 24 |
Oct 15 08:22:37 AM UTC 24 |
52769500 ps |
| T63 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1690049227 |
|
|
Oct 15 08:20:07 AM UTC 24 |
Oct 15 08:22:42 AM UTC 24 |
2907805100 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.3976914117 |
|
|
Oct 15 08:22:20 AM UTC 24 |
Oct 15 08:22:42 AM UTC 24 |
46988300 ps |
| T56 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2845828481 |
|
|
Oct 15 08:21:53 AM UTC 24 |
Oct 15 08:22:45 AM UTC 24 |
154363100 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.4080624369 |
|
|
Oct 15 08:22:22 AM UTC 24 |
Oct 15 08:22:47 AM UTC 24 |
45737000 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.875433068 |
|
|
Oct 15 08:21:58 AM UTC 24 |
Oct 15 08:22:52 AM UTC 24 |
994582500 ps |
| T47 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.4052659267 |
|
|
Oct 15 08:21:37 AM UTC 24 |
Oct 15 08:22:57 AM UTC 24 |
4359471800 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.963000254 |
|
|
Oct 15 08:22:36 AM UTC 24 |
Oct 15 08:23:02 AM UTC 24 |
138686700 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.2125275459 |
|
|
Oct 15 08:22:42 AM UTC 24 |
Oct 15 08:23:10 AM UTC 24 |
14117500 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.3859409645 |
|
|
Oct 15 08:22:44 AM UTC 24 |
Oct 15 08:23:15 AM UTC 24 |
26205200 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.4246164988 |
|
|
Oct 15 08:19:42 AM UTC 24 |
Oct 15 08:23:24 AM UTC 24 |
1561575300 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.2761391273 |
|
|
Oct 15 08:22:34 AM UTC 24 |
Oct 15 08:23:27 AM UTC 24 |
27561600 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.965400185 |
|
|
Oct 15 08:22:27 AM UTC 24 |
Oct 15 08:23:34 AM UTC 24 |
146484900 ps |
| T31 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.1736421188 |
|
|
Oct 15 08:22:27 AM UTC 24 |
Oct 15 08:23:37 AM UTC 24 |
10031486300 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3105928101 |
|
|
Oct 15 08:20:13 AM UTC 24 |
Oct 15 08:23:39 AM UTC 24 |
1521918800 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.1808803186 |
|
|
Oct 15 08:20:21 AM UTC 24 |
Oct 15 08:23:50 AM UTC 24 |
1539634900 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.2154801575 |
|
|
Oct 15 08:23:15 AM UTC 24 |
Oct 15 08:23:55 AM UTC 24 |
1441306800 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.3827740763 |
|
|
Oct 15 08:23:56 AM UTC 24 |
Oct 15 08:24:27 AM UTC 24 |
84627600 ps |
| T52 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3259722748 |
|
|
Oct 15 08:20:38 AM UTC 24 |
Oct 15 08:24:28 AM UTC 24 |
1738286400 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.4030871073 |
|
|
Oct 15 08:20:55 AM UTC 24 |
Oct 15 08:24:31 AM UTC 24 |
78764491800 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.42854273 |
|
|
Oct 15 08:23:39 AM UTC 24 |
Oct 15 08:24:45 AM UTC 24 |
7700503900 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2344860441 |
|
|
Oct 15 08:20:49 AM UTC 24 |
Oct 15 08:24:47 AM UTC 24 |
19600796400 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.3462121055 |
|
|
Oct 15 08:20:10 AM UTC 24 |
Oct 15 08:24:50 AM UTC 24 |
1780608100 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.834350489 |
|
|
Oct 15 08:22:44 AM UTC 24 |
Oct 15 08:24:54 AM UTC 24 |
82743600 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.769052628 |
|
|
Oct 15 08:24:31 AM UTC 24 |
Oct 15 08:25:08 AM UTC 24 |
89853700 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.2724033046 |
|
|
Oct 15 08:23:39 AM UTC 24 |
Oct 15 08:25:16 AM UTC 24 |
19032493400 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3727950207 |
|
|
Oct 15 08:22:47 AM UTC 24 |
Oct 15 08:25:37 AM UTC 24 |
6019633800 ps |
| T34 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.3011563006 |
|
|
Oct 15 08:17:09 AM UTC 24 |
Oct 15 08:25:40 AM UTC 24 |
1424636800 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1765569963 |
|
|
Oct 15 08:24:29 AM UTC 24 |
Oct 15 08:26:04 AM UTC 24 |
1899826500 ps |
| T35 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.3241475214 |
|
|
Oct 15 08:22:47 AM UTC 24 |
Oct 15 08:26:06 AM UTC 24 |
2708274700 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.53335729 |
|
|
Oct 15 08:25:41 AM UTC 24 |
Oct 15 08:26:07 AM UTC 24 |
37224300 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3394552506 |
|
|
Oct 15 08:24:28 AM UTC 24 |
Oct 15 08:26:07 AM UTC 24 |
3389172200 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.2650814771 |
|
|
Oct 15 08:23:47 AM UTC 24 |
Oct 15 08:26:08 AM UTC 24 |
2160567400 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2222322968 |
|
|
Oct 15 08:22:47 AM UTC 24 |
Oct 15 08:26:09 AM UTC 24 |
122871600 ps |
| T24 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.1584675317 |
|
|
Oct 15 08:26:09 AM UTC 24 |
Oct 15 08:26:31 AM UTC 24 |
109468400 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.670419801 |
|
|
Oct 15 08:25:50 AM UTC 24 |
Oct 15 08:26:33 AM UTC 24 |
30763700 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.3524415157 |
|
|
Oct 15 08:22:38 AM UTC 24 |
Oct 15 08:26:37 AM UTC 24 |
41732900 ps |
| T33 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.2761251585 |
|
|
Oct 15 08:22:58 AM UTC 24 |
Oct 15 08:26:39 AM UTC 24 |
43171400 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.4282151548 |
|
|
Oct 15 08:25:08 AM UTC 24 |
Oct 15 08:26:41 AM UTC 24 |
2418402200 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.1029700891 |
|
|
Oct 15 08:23:40 AM UTC 24 |
Oct 15 08:26:42 AM UTC 24 |
2332620300 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.2166981893 |
|
|
Oct 15 08:26:07 AM UTC 24 |
Oct 15 08:26:46 AM UTC 24 |
10819400 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.1020271763 |
|
|
Oct 15 08:26:02 AM UTC 24 |
Oct 15 08:26:53 AM UTC 24 |
55975300 ps |
| T8 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2165207476 |
|
|
Oct 15 08:26:26 AM UTC 24 |
Oct 15 08:26:54 AM UTC 24 |
355677400 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.2345998992 |
|
|
Oct 15 08:26:05 AM UTC 24 |
Oct 15 08:26:54 AM UTC 24 |
82417900 ps |
| T21 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.2498734867 |
|
|
Oct 15 08:26:32 AM UTC 24 |
Oct 15 08:26:57 AM UTC 24 |
23584600 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1756943856 |
|
|
Oct 15 08:26:10 AM UTC 24 |
Oct 15 08:26:58 AM UTC 24 |
548018000 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.424899973 |
|
|
Oct 15 08:26:42 AM UTC 24 |
Oct 15 08:27:04 AM UTC 24 |
15738600 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.713843433 |
|
|
Oct 15 08:24:08 AM UTC 24 |
Oct 15 08:27:06 AM UTC 24 |
747498400 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.1361777513 |
|
|
Oct 15 08:26:40 AM UTC 24 |
Oct 15 08:27:06 AM UTC 24 |
26593600 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.2923429864 |
|
|
Oct 15 08:26:42 AM UTC 24 |
Oct 15 08:27:09 AM UTC 24 |
36072400 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.818100782 |
|
|
Oct 15 08:26:38 AM UTC 24 |
Oct 15 08:27:09 AM UTC 24 |
737209400 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.991208881 |
|
|
Oct 15 08:26:48 AM UTC 24 |
Oct 15 08:27:13 AM UTC 24 |
25355500 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.2628967647 |
|
|
Oct 15 08:26:53 AM UTC 24 |
Oct 15 08:27:17 AM UTC 24 |
25724600 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.2884821376 |
|
|
Oct 15 08:26:55 AM UTC 24 |
Oct 15 08:27:18 AM UTC 24 |
194394700 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.1067219357 |
|
|
Oct 15 08:24:46 AM UTC 24 |
Oct 15 08:27:19 AM UTC 24 |
2388442100 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.3990722539 |
|
|
Oct 15 08:26:34 AM UTC 24 |
Oct 15 08:27:19 AM UTC 24 |
340320300 ps |
| T48 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.2150635340 |
|
|
Oct 15 08:26:08 AM UTC 24 |
Oct 15 08:27:27 AM UTC 24 |
1440753300 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.227529267 |
|
|
Oct 15 08:26:55 AM UTC 24 |
Oct 15 08:27:29 AM UTC 24 |
36235000 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.3144360654 |
|
|
Oct 15 08:27:06 AM UTC 24 |
Oct 15 08:27:38 AM UTC 24 |
23761600 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.208977193 |
|
|
Oct 15 08:26:59 AM UTC 24 |
Oct 15 08:27:45 AM UTC 24 |
29550000 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.3672204562 |
|
|
Oct 15 08:25:05 AM UTC 24 |
Oct 15 08:27:46 AM UTC 24 |
675084500 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.1643878432 |
|
|
Oct 15 08:24:54 AM UTC 24 |
Oct 15 08:27:51 AM UTC 24 |
1987915500 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.3560924890 |
|
|
Oct 15 08:18:59 AM UTC 24 |
Oct 15 08:27:54 AM UTC 24 |
13641515500 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.4152108760 |
|
|
Oct 15 08:22:49 AM UTC 24 |
Oct 15 08:27:54 AM UTC 24 |
358207900 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.545565677 |
|
|
Oct 15 08:27:29 AM UTC 24 |
Oct 15 08:27:55 AM UTC 24 |
869607200 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.3524037638 |
|
|
Oct 15 08:24:23 AM UTC 24 |
Oct 15 08:28:01 AM UTC 24 |
1808609300 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.4023645952 |
|
|
Oct 15 08:27:13 AM UTC 24 |
Oct 15 08:28:08 AM UTC 24 |
1043281000 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.1391455636 |
|
|
Oct 15 08:27:10 AM UTC 24 |
Oct 15 08:28:29 AM UTC 24 |
64199300 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.3171465843 |
|
|
Oct 15 08:28:01 AM UTC 24 |
Oct 15 08:28:30 AM UTC 24 |
85287700 ps |
| T89 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.628954197 |
|
|
Oct 15 08:24:51 AM UTC 24 |
Oct 15 08:28:43 AM UTC 24 |
3485881300 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.1844266443 |
|
|
Oct 15 08:24:48 AM UTC 24 |
Oct 15 08:28:50 AM UTC 24 |
3319012700 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3834904758 |
|
|
Oct 15 08:26:54 AM UTC 24 |
Oct 15 08:29:14 AM UTC 24 |
10012289200 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.641764515 |
|
|
Oct 15 08:28:35 AM UTC 24 |
Oct 15 08:29:17 AM UTC 24 |
75260400 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.3962137822 |
|
|
Oct 15 08:27:52 AM UTC 24 |
Oct 15 08:29:18 AM UTC 24 |
5577391000 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.3574277056 |
|
|
Oct 15 08:25:38 AM UTC 24 |
Oct 15 08:29:41 AM UTC 24 |
19394913100 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.2769326569 |
|
|
Oct 15 08:28:29 AM UTC 24 |
Oct 15 08:29:48 AM UTC 24 |
607056400 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.485044068 |
|
|
Oct 15 08:28:30 AM UTC 24 |
Oct 15 08:29:54 AM UTC 24 |
2176076200 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3213835480 |
|
|
Oct 15 08:20:32 AM UTC 24 |
Oct 15 08:29:59 AM UTC 24 |
2849228300 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2469848355 |
|
|
Oct 15 08:27:55 AM UTC 24 |
Oct 15 08:29:59 AM UTC 24 |
580358700 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.1575490996 |
|
|
Oct 15 08:27:47 AM UTC 24 |
Oct 15 08:30:05 AM UTC 24 |
16922153500 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.1225366070 |
|
|
Oct 15 08:29:55 AM UTC 24 |
Oct 15 08:30:21 AM UTC 24 |
19080800 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.3645045203 |
|
|
Oct 15 08:27:21 AM UTC 24 |
Oct 15 08:30:23 AM UTC 24 |
72273900 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.3197901751 |
|
|
Oct 15 08:27:55 AM UTC 24 |
Oct 15 08:30:24 AM UTC 24 |
2002349800 ps |
| T36 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.2359189798 |
|
|
Oct 15 08:27:09 AM UTC 24 |
Oct 15 08:30:30 AM UTC 24 |
1456074100 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.39423101 |
|
|
Oct 15 08:27:07 AM UTC 24 |
Oct 15 08:30:34 AM UTC 24 |
63403900 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3640768403 |
|
|
Oct 15 08:28:09 AM UTC 24 |
Oct 15 08:30:38 AM UTC 24 |
1125624700 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.3738855170 |
|
|
Oct 15 08:30:00 AM UTC 24 |
Oct 15 08:30:44 AM UTC 24 |
78213600 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.2403068376 |
|
|
Oct 15 08:28:43 AM UTC 24 |
Oct 15 08:30:57 AM UTC 24 |
575265900 ps |
| T25 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.989445754 |
|
|
Oct 15 08:30:35 AM UTC 24 |
Oct 15 08:30:58 AM UTC 24 |
15843600 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.543812689 |
|
|
Oct 15 08:30:21 AM UTC 24 |
Oct 15 08:30:59 AM UTC 24 |
24858300 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2237463833 |
|
|
Oct 15 08:30:05 AM UTC 24 |
Oct 15 08:31:07 AM UTC 24 |
284433500 ps |
| T19 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.935382354 |
|
|
Oct 15 08:30:39 AM UTC 24 |
Oct 15 08:31:08 AM UTC 24 |
156492700 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.4019825507 |
|
|
Oct 15 08:29:42 AM UTC 24 |
Oct 15 08:31:10 AM UTC 24 |
4888331600 ps |
| T22 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.299711686 |
|
|
Oct 15 08:30:45 AM UTC 24 |
Oct 15 08:31:12 AM UTC 24 |
40352200 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.3172378319 |
|
|
Oct 15 08:27:28 AM UTC 24 |
Oct 15 08:31:12 AM UTC 24 |
8175197100 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2552151404 |
|
|
Oct 15 08:31:00 AM UTC 24 |
Oct 15 08:31:21 AM UTC 24 |
16327700 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2344017635 |
|
|
Oct 15 08:30:37 AM UTC 24 |
Oct 15 08:31:21 AM UTC 24 |
216631500 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.231293404 |
|
|
Oct 15 08:30:59 AM UTC 24 |
Oct 15 08:31:23 AM UTC 24 |
38633100 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.797470133 |
|
|
Oct 15 08:30:58 AM UTC 24 |
Oct 15 08:31:27 AM UTC 24 |
710385800 ps |
| T39 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3129897898 |
|
|
Oct 15 08:26:58 AM UTC 24 |
Oct 15 08:31:29 AM UTC 24 |
6693486200 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3823714527 |
|
|
Oct 15 08:31:10 AM UTC 24 |
Oct 15 08:31:36 AM UTC 24 |
69911700 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.1359442904 |
|
|
Oct 15 08:31:07 AM UTC 24 |
Oct 15 08:31:37 AM UTC 24 |
20082000 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.3400447804 |
|
|
Oct 15 08:31:13 AM UTC 24 |
Oct 15 08:31:40 AM UTC 24 |
46705100 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.1055693761 |
|
|
Oct 15 08:30:54 AM UTC 24 |
Oct 15 08:31:45 AM UTC 24 |
314937600 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.2031104385 |
|
|
Oct 15 08:31:22 AM UTC 24 |
Oct 15 08:31:47 AM UTC 24 |
62617600 ps |
| T28 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.3130485095 |
|
|
Oct 15 08:17:10 AM UTC 24 |
Oct 15 08:31:51 AM UTC 24 |
170183466800 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.3760860322 |
|
|
Oct 15 08:31:17 AM UTC 24 |
Oct 15 08:31:56 AM UTC 24 |
40721500 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.1020600151 |
|
|
Oct 15 08:30:25 AM UTC 24 |
Oct 15 08:32:03 AM UTC 24 |
1654348200 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.1746836843 |
|
|
Oct 15 08:28:15 AM UTC 24 |
Oct 15 08:32:07 AM UTC 24 |
5810594300 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.30639629 |
|
|
Oct 15 08:23:11 AM UTC 24 |
Oct 15 08:32:09 AM UTC 24 |
5624658700 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.2151325336 |
|
|
Oct 15 08:31:25 AM UTC 24 |
Oct 15 08:32:15 AM UTC 24 |
54598800 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.1098018351 |
|
|
Oct 15 08:31:28 AM UTC 24 |
Oct 15 08:32:18 AM UTC 24 |
87499200 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.1149135419 |
|
|
Oct 15 08:29:18 AM UTC 24 |
Oct 15 08:32:22 AM UTC 24 |
1939957300 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.2482498951 |
|
|
Oct 15 08:23:51 AM UTC 24 |
Oct 15 08:32:30 AM UTC 24 |
14314671800 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.574636835 |
|
|
Oct 15 08:32:08 AM UTC 24 |
Oct 15 08:32:45 AM UTC 24 |
327538900 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.2506457379 |
|
|
Oct 15 08:31:41 AM UTC 24 |
Oct 15 08:32:48 AM UTC 24 |
2657183900 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.3846270211 |
|
|
Oct 15 08:29:49 AM UTC 24 |
Oct 15 08:32:58 AM UTC 24 |
70071512900 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.2255405202 |
|
|
Oct 15 08:29:53 AM UTC 24 |
Oct 15 08:33:05 AM UTC 24 |
65802363000 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.386661365 |
|
|
Oct 15 08:29:16 AM UTC 24 |
Oct 15 08:33:22 AM UTC 24 |
2831271700 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3355839162 |
|
|
Oct 15 08:31:13 AM UTC 24 |
Oct 15 08:33:23 AM UTC 24 |
10019994800 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.636276878 |
|
|
Oct 15 08:31:22 AM UTC 24 |
Oct 15 08:33:27 AM UTC 24 |
99959200 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.711312566 |
|
|
Oct 15 08:28:51 AM UTC 24 |
Oct 15 08:33:37 AM UTC 24 |
4460731700 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.4071577300 |
|
|
Oct 15 08:33:23 AM UTC 24 |
Oct 15 08:33:49 AM UTC 24 |
23020100 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.3953762033 |
|
|
Oct 15 08:32:30 AM UTC 24 |
Oct 15 08:33:51 AM UTC 24 |
3384139700 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.270697888 |
|
|
Oct 15 08:31:29 AM UTC 24 |
Oct 15 08:33:59 AM UTC 24 |
92504900 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3265113646 |
|
|
Oct 15 08:25:17 AM UTC 24 |
Oct 15 08:34:03 AM UTC 24 |
48882295600 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.1295567389 |
|
|
Oct 15 08:31:52 AM UTC 24 |
Oct 15 08:34:07 AM UTC 24 |
37404600 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2074760951 |
|
|
Oct 15 08:29:37 AM UTC 24 |
Oct 15 08:34:13 AM UTC 24 |
9220514700 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.3373997907 |
|
|
Oct 15 08:32:46 AM UTC 24 |
Oct 15 08:34:32 AM UTC 24 |
842348900 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3548673444 |
|
|
Oct 15 08:33:52 AM UTC 24 |
Oct 15 08:34:33 AM UTC 24 |
31855100 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.3521536660 |
|
|
Oct 15 08:33:49 AM UTC 24 |
Oct 15 08:34:54 AM UTC 24 |
1002233400 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.3758438699 |
|
|
Oct 15 08:17:01 AM UTC 24 |
Oct 15 08:34:55 AM UTC 24 |
173863100 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.3851751253 |
|
|
Oct 15 08:24:58 AM UTC 24 |
Oct 15 08:34:59 AM UTC 24 |
3064061700 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.3591437066 |
|
|
Oct 15 08:33:38 AM UTC 24 |
Oct 15 08:35:00 AM UTC 24 |
455050400 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.1348106713 |
|
|
Oct 15 08:31:37 AM UTC 24 |
Oct 15 08:35:15 AM UTC 24 |
102660100 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.1236577062 |
|
|
Oct 15 08:35:00 AM UTC 24 |
Oct 15 08:35:21 AM UTC 24 |
103376700 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.2946844426 |
|
|
Oct 15 08:32:59 AM UTC 24 |
Oct 15 08:35:29 AM UTC 24 |
457081100 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.678338858 |
|
|
Oct 15 08:33:24 AM UTC 24 |
Oct 15 08:35:33 AM UTC 24 |
1253710200 ps |
| T57 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.3640080779 |
|
|
Oct 15 08:35:00 AM UTC 24 |
Oct 15 08:35:42 AM UTC 24 |
27133000 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4239560478 |
|
|
Oct 15 08:27:56 AM UTC 24 |
Oct 15 08:36:02 AM UTC 24 |
54295031800 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.494856843 |
|
|
Oct 15 08:34:35 AM UTC 24 |
Oct 15 08:36:05 AM UTC 24 |
11073610700 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3330490115 |
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|
Oct 15 08:32:49 AM UTC 24 |
Oct 15 08:36:05 AM UTC 24 |
5299198100 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.2632558480 |
|
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Oct 15 08:35:15 AM UTC 24 |
Oct 15 08:36:06 AM UTC 24 |
75875900 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2575820529 |
|
|
Oct 15 08:35:29 AM UTC 24 |
Oct 15 08:36:06 AM UTC 24 |
52777500 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.4275722549 |
|
|
Oct 15 08:35:22 AM UTC 24 |
Oct 15 08:36:07 AM UTC 24 |
135616000 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.593874247 |
|
|
Oct 15 08:33:28 AM UTC 24 |
Oct 15 08:36:12 AM UTC 24 |
3428247000 ps |
| T29 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.1567377383 |
|
|
Oct 15 08:22:53 AM UTC 24 |
Oct 15 08:36:15 AM UTC 24 |
40121644700 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.1472063984 |
|
|
Oct 15 08:36:06 AM UTC 24 |
Oct 15 08:36:32 AM UTC 24 |
28303100 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.3328981706 |
|
|
Oct 15 08:36:07 AM UTC 24 |
Oct 15 08:36:35 AM UTC 24 |
17141700 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.3942072691 |
|
|
Oct 15 08:34:00 AM UTC 24 |
Oct 15 08:36:35 AM UTC 24 |
2532106400 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.3124882767 |
|
|
Oct 15 08:36:13 AM UTC 24 |
Oct 15 08:36:37 AM UTC 24 |
35740200 ps |
| T30 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.2400088996 |
|
|
Oct 15 08:22:15 AM UTC 24 |
Oct 15 08:36:37 AM UTC 24 |
40211578400 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1900809362 |
|
|
Oct 15 08:36:08 AM UTC 24 |
Oct 15 08:36:38 AM UTC 24 |
17692700 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.4051780891 |
|
|
Oct 15 08:36:15 AM UTC 24 |
Oct 15 08:36:40 AM UTC 24 |
15746500 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.410890900 |
|
|
Oct 15 08:36:07 AM UTC 24 |
Oct 15 08:36:46 AM UTC 24 |
776567400 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.1791243810 |
|
|
Oct 15 08:36:06 AM UTC 24 |
Oct 15 08:36:47 AM UTC 24 |
798916500 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3335831019 |
|
|
Oct 15 08:36:27 AM UTC 24 |
Oct 15 08:36:49 AM UTC 24 |
15657600 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.2653950669 |
|
|
Oct 15 08:34:03 AM UTC 24 |
Oct 15 08:36:55 AM UTC 24 |
951819700 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.4272752486 |
|
|
Oct 15 08:27:18 AM UTC 24 |
Oct 15 08:36:59 AM UTC 24 |
4749284100 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.2408120215 |
|
|
Oct 15 08:36:35 AM UTC 24 |
Oct 15 08:37:00 AM UTC 24 |
33107100 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1899600728 |
|
|
Oct 15 08:35:44 AM UTC 24 |
Oct 15 08:37:08 AM UTC 24 |
385861300 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.3511928198 |
|
|
Oct 15 08:36:39 AM UTC 24 |
Oct 15 08:37:13 AM UTC 24 |
56158400 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.839395972 |
|
|
Oct 15 08:34:33 AM UTC 24 |
Oct 15 08:37:13 AM UTC 24 |
1209887600 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.4249331478 |
|
|
Oct 15 08:36:39 AM UTC 24 |
Oct 15 08:37:15 AM UTC 24 |
88608300 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.3664324737 |
|
|
Oct 15 08:29:19 AM UTC 24 |
Oct 15 08:37:20 AM UTC 24 |
32811895600 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.3406650408 |
|
|
Oct 15 08:17:55 AM UTC 24 |
Oct 15 08:37:25 AM UTC 24 |
635643900 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.2068694883 |
|
|
Oct 15 08:27:05 AM UTC 24 |
Oct 15 08:37:26 AM UTC 24 |
10821810800 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2404858845 |
|
|
Oct 15 08:22:44 AM UTC 24 |
Oct 15 08:37:35 AM UTC 24 |
90782100 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1859724210 |
|
|
Oct 15 08:36:32 AM UTC 24 |
Oct 15 08:37:39 AM UTC 24 |
10039582300 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.1622873400 |
|
|
Oct 15 08:34:08 AM UTC 24 |
Oct 15 08:37:46 AM UTC 24 |
670374400 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.2433604477 |
|
|
Oct 15 08:37:14 AM UTC 24 |
Oct 15 08:37:47 AM UTC 24 |
790839900 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1133862751 |
|
|
Oct 15 08:31:26 AM UTC 24 |
Oct 15 08:38:15 AM UTC 24 |
3169561800 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.3138630798 |
|
|
Oct 15 08:36:41 AM UTC 24 |
Oct 15 08:38:20 AM UTC 24 |
221419400 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.1292902926 |
|
|
Oct 15 08:34:14 AM UTC 24 |
Oct 15 08:38:48 AM UTC 24 |
12342581600 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.3468369184 |
|
|
Oct 15 08:36:50 AM UTC 24 |
Oct 15 08:38:56 AM UTC 24 |
3309035200 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1459983071 |
|
|
Oct 15 08:36:47 AM UTC 24 |
Oct 15 08:38:57 AM UTC 24 |
87519500 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.3498415593 |
|
|
Oct 15 08:37:32 AM UTC 24 |
Oct 15 08:38:58 AM UTC 24 |
5594343700 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.1352285006 |
|
|
Oct 15 08:38:16 AM UTC 24 |
Oct 15 08:38:59 AM UTC 24 |
80051000 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.3773404581 |
|
|
Oct 15 08:37:47 AM UTC 24 |
Oct 15 08:39:22 AM UTC 24 |
427089600 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.1406765014 |
|
|
Oct 15 08:38:59 AM UTC 24 |
Oct 15 08:39:25 AM UTC 24 |
32260400 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.497752751 |
|
|
Oct 15 08:37:36 AM UTC 24 |
Oct 15 08:39:46 AM UTC 24 |
1656836200 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.1215987877 |
|
|
Oct 15 08:23:32 AM UTC 24 |
Oct 15 08:39:52 AM UTC 24 |
567080400 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1379167353 |
|
|
Oct 15 08:36:48 AM UTC 24 |
Oct 15 08:39:54 AM UTC 24 |
2838350000 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.3026449759 |
|
|
Oct 15 08:37:01 AM UTC 24 |
Oct 15 08:39:55 AM UTC 24 |
147358300 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.3827688830 |
|
|
Oct 15 08:31:46 AM UTC 24 |
Oct 15 08:40:04 AM UTC 24 |
8505198900 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.1948557352 |
|
|
Oct 15 08:38:58 AM UTC 24 |
Oct 15 08:40:09 AM UTC 24 |
480274400 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.819033496 |
|
|
Oct 15 08:33:06 AM UTC 24 |
Oct 15 08:40:09 AM UTC 24 |
7790960300 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.548321579 |
|
|
Oct 15 08:38:58 AM UTC 24 |
Oct 15 08:40:22 AM UTC 24 |
1019420000 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.504229253 |
|
|
Oct 15 08:37:40 AM UTC 24 |
Oct 15 08:40:23 AM UTC 24 |
4393365200 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.1201783467 |
|
|
Oct 15 08:38:20 AM UTC 24 |
Oct 15 08:40:29 AM UTC 24 |
629277800 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.765632522 |
|
|
Oct 15 08:40:10 AM UTC 24 |
Oct 15 08:40:31 AM UTC 24 |
54710200 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1800571344 |
|
|
Oct 15 08:34:56 AM UTC 24 |
Oct 15 08:40:51 AM UTC 24 |
25408975800 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.2883161828 |
|
|
Oct 15 08:40:24 AM UTC 24 |
Oct 15 08:41:04 AM UTC 24 |
29528400 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2017804443 |
|
|
Oct 15 08:40:32 AM UTC 24 |
Oct 15 08:41:06 AM UTC 24 |
20477700 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1161671925 |
|
|
Oct 15 08:40:24 AM UTC 24 |
Oct 15 08:41:09 AM UTC 24 |
46074400 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.647323858 |
|
|
Oct 15 08:37:13 AM UTC 24 |
Oct 15 08:41:09 AM UTC 24 |
36291463100 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.2144879748 |
|
|
Oct 15 08:39:56 AM UTC 24 |
Oct 15 08:41:10 AM UTC 24 |
9836136400 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.3004147004 |
|
|
Oct 15 08:39:00 AM UTC 24 |
Oct 15 08:41:20 AM UTC 24 |
2962622500 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.2385836054 |
|
|
Oct 15 08:40:30 AM UTC 24 |
Oct 15 08:41:23 AM UTC 24 |
61266200 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.3650331592 |
|
|
Oct 15 08:41:07 AM UTC 24 |
Oct 15 08:41:28 AM UTC 24 |
14414900 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.3714969454 |
|
|
Oct 15 08:41:11 AM UTC 24 |
Oct 15 08:41:33 AM UTC 24 |
879828600 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.1970953349 |
|
|
Oct 15 08:34:55 AM UTC 24 |
Oct 15 08:41:41 AM UTC 24 |
12322905900 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.2682927578 |
|
|
Oct 15 08:27:21 AM UTC 24 |
Oct 15 08:41:44 AM UTC 24 |
80141736000 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.2884216458 |
|
|
Oct 15 08:41:21 AM UTC 24 |
Oct 15 08:41:46 AM UTC 24 |
44822700 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3693939414 |
|
|
Oct 15 08:41:24 AM UTC 24 |
Oct 15 08:41:48 AM UTC 24 |
26284400 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.3861772242 |
|
|
Oct 15 08:38:50 AM UTC 24 |
Oct 15 08:41:50 AM UTC 24 |
7588440400 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.2122752215 |
|
|
Oct 15 08:41:29 AM UTC 24 |
Oct 15 08:41:58 AM UTC 24 |
15477100 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.3378182406 |
|
|
Oct 15 08:41:34 AM UTC 24 |
Oct 15 08:41:59 AM UTC 24 |
47318700 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.2256838390 |
|
|
Oct 15 08:36:36 AM UTC 24 |
Oct 15 08:42:00 AM UTC 24 |
35583900 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.2463173708 |
|
|
Oct 15 08:31:38 AM UTC 24 |
Oct 15 08:42:02 AM UTC 24 |
300779200 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1423962442 |
|
|
Oct 15 08:41:11 AM UTC 24 |
Oct 15 08:42:02 AM UTC 24 |
660832900 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.2450027763 |
|
|
Oct 15 08:36:39 AM UTC 24 |
Oct 15 08:42:11 AM UTC 24 |
386581400 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.515666209 |
|
|
Oct 15 08:41:42 AM UTC 24 |
Oct 15 08:42:13 AM UTC 24 |
177549200 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.1401348823 |
|
|
Oct 15 08:39:46 AM UTC 24 |
Oct 15 08:42:22 AM UTC 24 |
4387415100 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2783833468 |
|
|
Oct 15 08:41:05 AM UTC 24 |
Oct 15 08:42:38 AM UTC 24 |
1149090000 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2739630603 |
|
|
Oct 15 08:42:03 AM UTC 24 |
Oct 15 08:42:38 AM UTC 24 |
161432600 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.2808212312 |
|
|
Oct 15 08:21:51 AM UTC 24 |
Oct 15 08:42:41 AM UTC 24 |
203317800 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_10_14/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.1175469012 |
|
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Oct 15 08:39:23 AM UTC 24 |
Oct 15 08:42:46 AM UTC 24 |
5564328700 ps |