Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T103 |
1 |
|
T125 |
1 |
|
T60 |
1 |
| others[1] |
251 |
1 |
|
T22 |
1 |
|
T367 |
2 |
|
T223 |
1 |
| others[2] |
232 |
1 |
|
T25 |
1 |
|
T22 |
1 |
|
T67 |
1 |
| others[3] |
389 |
1 |
|
T31 |
1 |
|
T22 |
4 |
|
T104 |
1 |
| false |
120 |
1 |
|
T259 |
1 |
|
T28 |
5 |
|
T201 |
1 |
| true |
12650 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
224 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T90 |
1 |
| others[1] |
233 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T103 |
1 |
| others[2] |
227 |
1 |
|
T4 |
1 |
|
T72 |
1 |
|
T40 |
1 |
| others[3] |
378 |
1 |
|
T67 |
1 |
|
T68 |
1 |
|
T234 |
1 |
| false |
126 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T28 |
3 |
| true |
12679 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8193 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
4 |
| others[1] |
1194 |
1 |
|
T8 |
10 |
|
T32 |
18 |
|
T33 |
13 |
| others[2] |
1273 |
1 |
|
T8 |
13 |
|
T31 |
1 |
|
T32 |
18 |
| others[3] |
2038 |
1 |
|
T8 |
15 |
|
T48 |
1 |
|
T32 |
40 |
| false |
676 |
1 |
|
T8 |
7 |
|
T120 |
1 |
|
T32 |
7 |
| true |
493 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8138 |
1 |
|
T8 |
10 |
|
T120 |
1 |
|
T55 |
108 |
| others[1] |
1274 |
1 |
|
T8 |
17 |
|
T32 |
19 |
|
T33 |
10 |
| others[2] |
1226 |
1 |
|
T8 |
8 |
|
T20 |
1 |
|
T32 |
18 |
| others[3] |
2102 |
1 |
|
T8 |
9 |
|
T22 |
1 |
|
T32 |
35 |
| false |
650 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
5 |
| true |
477 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
107 |
1 |
|
T56 |
1 |
|
T235 |
1 |
|
T28 |
5 |
| others[1] |
115 |
1 |
|
T67 |
1 |
|
T103 |
1 |
|
T28 |
2 |
| others[2] |
105 |
1 |
|
T125 |
1 |
|
T235 |
1 |
|
T261 |
1 |
| others[3] |
164 |
1 |
|
T56 |
1 |
|
T90 |
1 |
|
T28 |
4 |
| false |
56 |
1 |
|
T241 |
1 |
|
T90 |
1 |
|
T28 |
2 |
| true |
13320 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[1] |
218 |
1 |
|
T22 |
1 |
|
T67 |
1 |
|
T235 |
1 |
| others[2] |
251 |
1 |
|
T22 |
2 |
|
T28 |
12 |
|
T45 |
1 |
| others[3] |
431 |
1 |
|
T25 |
1 |
|
T22 |
1 |
|
T132 |
2 |
| false |
115 |
1 |
|
T22 |
1 |
|
T234 |
1 |
|
T18 |
1 |
| true |
12608 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
7921 |
1 |
|
T2 |
1 |
|
T8 |
11 |
|
T55 |
108 |
| others[1] |
1073 |
1 |
|
T8 |
13 |
|
T12 |
1 |
|
T61 |
1 |
| others[2] |
1050 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T8 |
10 |
| others[3] |
1863 |
1 |
|
T4 |
1 |
|
T8 |
12 |
|
T31 |
1 |
| false |
536 |
1 |
|
T1 |
1 |
|
T8 |
3 |
|
T32 |
5 |
| true |
1424 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T37 |
1 |
|
T234 |
1 |
|
T40 |
1 |
| others[1] |
223 |
1 |
|
T22 |
1 |
|
T235 |
1 |
|
T259 |
1 |
| others[2] |
241 |
1 |
|
T25 |
1 |
|
T22 |
3 |
|
T132 |
1 |
| others[3] |
406 |
1 |
|
T22 |
2 |
|
T30 |
1 |
|
T132 |
1 |
| false |
107 |
1 |
|
T241 |
1 |
|
T90 |
1 |
|
T28 |
5 |
| true |
12634 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
226 |
1 |
|
T54 |
1 |
|
T28 |
7 |
|
T123 |
2 |
| others[1] |
222 |
1 |
|
T234 |
1 |
|
T133 |
1 |
|
T60 |
1 |
| others[2] |
216 |
1 |
|
T37 |
1 |
|
T28 |
6 |
|
T201 |
2 |
| others[3] |
365 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T30 |
1 |
| false |
119 |
1 |
|
T4 |
1 |
|
T90 |
1 |
|
T28 |
10 |
| true |
12719 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
8154 |
1 |
|
T1 |
1 |
|
T8 |
13 |
|
T55 |
108 |
| others[1] |
1295 |
1 |
|
T8 |
8 |
|
T30 |
1 |
|
T32 |
18 |
| others[2] |
1292 |
1 |
|
T8 |
8 |
|
T120 |
1 |
|
T32 |
22 |
| others[3] |
2004 |
1 |
|
T8 |
15 |
|
T31 |
1 |
|
T48 |
1 |
| false |
646 |
1 |
|
T2 |
1 |
|
T8 |
5 |
|
T48 |
1 |
| true |
476 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T8 |
6 |
|
T120 |
1 |
|
T32 |
23 |
| others[1] |
1256 |
1 |
|
T8 |
7 |
|
T32 |
20 |
|
T132 |
1 |
| others[2] |
1258 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
10 |
| others[3] |
2030 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T8 |
20 |
| false |
663 |
1 |
|
T8 |
6 |
|
T32 |
6 |
|
T33 |
1 |
| true |
481 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
99 |
1 |
|
T103 |
1 |
|
T54 |
1 |
|
T28 |
2 |
| others[1] |
97 |
1 |
|
T28 |
2 |
|
T410 |
2 |
|
T78 |
5 |
| others[2] |
100 |
1 |
|
T133 |
1 |
|
T240 |
1 |
|
T56 |
1 |
| others[3] |
148 |
1 |
|
T56 |
1 |
|
T235 |
1 |
|
T40 |
1 |
| false |
51 |
1 |
|
T28 |
3 |
|
T315 |
1 |
|
T78 |
2 |
| true |
6427 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
233 |
1 |
|
T25 |
1 |
|
T54 |
1 |
|
T90 |
1 |
| others[1] |
248 |
1 |
|
T4 |
1 |
|
T31 |
1 |
|
T22 |
2 |
| others[2] |
228 |
1 |
|
T22 |
2 |
|
T234 |
1 |
|
T72 |
1 |
| others[3] |
388 |
1 |
|
T4 |
2 |
|
T22 |
1 |
|
T282 |
1 |
| false |
102 |
1 |
|
T22 |
1 |
|
T37 |
1 |
|
T159 |
1 |
| true |
5723 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1009 |
1 |
|
T4 |
1 |
|
T8 |
11 |
|
T6 |
1 |
| others[1] |
1025 |
1 |
|
T2 |
1 |
|
T8 |
9 |
|
T120 |
1 |
| others[2] |
1083 |
1 |
|
T4 |
2 |
|
T8 |
10 |
|
T31 |
1 |
| others[3] |
1788 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
| false |
598 |
1 |
|
T8 |
4 |
|
T32 |
7 |
|
T33 |
7 |
| true |
1419 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
225 |
1 |
|
T68 |
1 |
|
T234 |
1 |
|
T133 |
1 |
| others[1] |
222 |
1 |
|
T60 |
1 |
|
T240 |
1 |
|
T367 |
1 |
| others[2] |
217 |
1 |
|
T37 |
1 |
|
T54 |
1 |
|
T367 |
1 |
| others[3] |
408 |
1 |
|
T30 |
1 |
|
T59 |
1 |
|
T56 |
1 |
| false |
115 |
1 |
|
T367 |
2 |
|
T28 |
4 |
|
T91 |
1 |
| true |
5735 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T16 |
1 |
|
T60 |
1 |
|
T18 |
1 |
| others[1] |
216 |
1 |
|
T4 |
1 |
|
T282 |
1 |
|
T28 |
13 |
| others[2] |
218 |
1 |
|
T56 |
1 |
|
T18 |
1 |
|
T28 |
6 |
| others[3] |
378 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T67 |
1 |
| false |
129 |
1 |
|
T80 |
1 |
|
T81 |
1 |
|
T90 |
2 |
| true |
5759 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1214 |
1 |
|
T8 |
12 |
|
T48 |
1 |
|
T32 |
13 |
| others[1] |
1180 |
1 |
|
T8 |
12 |
|
T32 |
14 |
|
T33 |
15 |
| others[2] |
1325 |
1 |
|
T8 |
11 |
|
T32 |
29 |
|
T132 |
1 |
| others[3] |
2054 |
1 |
|
T8 |
11 |
|
T32 |
33 |
|
T33 |
16 |
| false |
670 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
3 |
| true |
479 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T8 |
9 |
|
T32 |
17 |
|
T33 |
9 |
| others[1] |
1246 |
1 |
|
T8 |
9 |
|
T32 |
24 |
|
T33 |
14 |
| others[2] |
1246 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
10 |
| others[3] |
2051 |
1 |
|
T8 |
19 |
|
T120 |
1 |
|
T32 |
29 |
| false |
632 |
1 |
|
T8 |
2 |
|
T32 |
14 |
|
T33 |
8 |
| true |
478 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
102 |
1 |
|
T56 |
1 |
|
T235 |
1 |
|
T40 |
1 |
| others[1] |
114 |
1 |
|
T241 |
1 |
|
T235 |
1 |
|
T28 |
2 |
| others[2] |
91 |
1 |
|
T28 |
3 |
|
T202 |
1 |
|
T410 |
1 |
| others[3] |
151 |
1 |
|
T104 |
1 |
|
T68 |
1 |
|
T56 |
1 |
| false |
52 |
1 |
|
T28 |
1 |
|
T411 |
1 |
|
T78 |
3 |
| true |
6412 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
265 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T132 |
1 |
| others[1] |
242 |
1 |
|
T22 |
2 |
|
T241 |
1 |
|
T133 |
1 |
| others[2] |
222 |
1 |
|
T132 |
1 |
|
T60 |
1 |
|
T18 |
1 |
| others[3] |
412 |
1 |
|
T25 |
1 |
|
T22 |
2 |
|
T103 |
1 |
| false |
130 |
1 |
|
T22 |
1 |
|
T30 |
1 |
|
T56 |
1 |
| true |
5651 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1057 |
1 |
|
T4 |
2 |
|
T8 |
8 |
|
T16 |
1 |
| others[1] |
1046 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T8 |
7 |
| others[2] |
1125 |
1 |
|
T5 |
1 |
|
T8 |
13 |
|
T22 |
3 |
| others[3] |
1688 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
15 |
| false |
577 |
1 |
|
T1 |
1 |
|
T8 |
6 |
|
T22 |
1 |
| true |
1429 |
1 |
|
T4 |
1 |
|
T31 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T22 |
2 |
|
T104 |
1 |
|
T234 |
1 |
| others[1] |
237 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T25 |
1 |
| others[2] |
243 |
1 |
|
T22 |
1 |
|
T30 |
1 |
|
T43 |
1 |
| others[3] |
422 |
1 |
|
T22 |
3 |
|
T282 |
1 |
|
T235 |
1 |
| false |
108 |
1 |
|
T60 |
1 |
|
T28 |
7 |
|
T45 |
1 |
| true |
5669 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T67 |
1 |
|
T18 |
1 |
|
T90 |
1 |
| others[1] |
197 |
1 |
|
T4 |
1 |
|
T125 |
1 |
|
T90 |
2 |
| others[2] |
256 |
1 |
|
T4 |
1 |
|
T133 |
1 |
|
T56 |
1 |
| others[3] |
403 |
1 |
|
T4 |
1 |
|
T104 |
1 |
|
T241 |
1 |
| false |
109 |
1 |
|
T28 |
3 |
|
T123 |
1 |
|
T91 |
1 |
| true |
5726 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T2 |
1 |
|
T8 |
4 |
|
T32 |
24 |
| others[1] |
1300 |
1 |
|
T1 |
1 |
|
T8 |
10 |
|
T32 |
17 |
| others[2] |
1223 |
1 |
|
T4 |
1 |
|
T8 |
8 |
|
T32 |
21 |
| others[3] |
2035 |
1 |
|
T4 |
1 |
|
T8 |
23 |
|
T120 |
1 |
| false |
642 |
1 |
|
T8 |
4 |
|
T22 |
1 |
|
T32 |
7 |
| true |
468 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1208 |
1 |
|
T2 |
1 |
|
T8 |
6 |
|
T32 |
14 |
| others[1] |
1303 |
1 |
|
T8 |
9 |
|
T120 |
1 |
|
T32 |
22 |
| others[2] |
1240 |
1 |
|
T8 |
10 |
|
T20 |
1 |
|
T32 |
24 |
| others[3] |
2046 |
1 |
|
T1 |
1 |
|
T8 |
18 |
|
T31 |
1 |
| false |
655 |
1 |
|
T8 |
6 |
|
T32 |
7 |
|
T33 |
7 |
| true |
470 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T16 |
1 |
|
T241 |
1 |
|
T56 |
1 |
| others[1] |
107 |
1 |
|
T104 |
1 |
|
T56 |
1 |
|
T235 |
1 |
| others[2] |
122 |
1 |
|
T68 |
1 |
|
T28 |
8 |
|
T157 |
1 |
| others[3] |
178 |
1 |
|
T125 |
1 |
|
T235 |
1 |
|
T223 |
1 |
| false |
59 |
1 |
|
T412 |
1 |
|
T78 |
2 |
|
T79 |
3 |
| true |
6342 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T22 |
1 |
|
T37 |
1 |
|
T60 |
1 |
| others[1] |
245 |
1 |
|
T4 |
1 |
|
T159 |
1 |
|
T18 |
1 |
| others[2] |
255 |
1 |
|
T4 |
1 |
|
T31 |
1 |
|
T22 |
2 |
| others[3] |
392 |
1 |
|
T22 |
2 |
|
T30 |
1 |
|
T67 |
1 |
| false |
117 |
1 |
|
T3 |
1 |
|
T25 |
1 |
|
T22 |
1 |
| true |
5662 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
4 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |