Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1122 |
1 |
|
T4 |
1 |
|
T8 |
10 |
|
T22 |
2 |
| others[1] |
1108 |
1 |
|
T8 |
11 |
|
T22 |
1 |
|
T120 |
1 |
| others[2] |
1030 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T8 |
7 |
| others[3] |
1737 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
19 |
| false |
515 |
1 |
|
T4 |
1 |
|
T8 |
2 |
|
T22 |
1 |
| true |
1410 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T30 |
1 |
|
T367 |
1 |
|
T28 |
17 |
| others[1] |
244 |
1 |
|
T16 |
1 |
|
T25 |
1 |
|
T132 |
1 |
| others[2] |
240 |
1 |
|
T22 |
3 |
|
T282 |
1 |
|
T367 |
2 |
| others[3] |
357 |
1 |
|
T22 |
2 |
|
T132 |
1 |
|
T72 |
1 |
| false |
127 |
1 |
|
T22 |
1 |
|
T43 |
1 |
|
T28 |
6 |
| true |
5727 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
235 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T103 |
1 |
| others[1] |
219 |
1 |
|
T4 |
2 |
|
T37 |
1 |
|
T133 |
1 |
| others[2] |
215 |
1 |
|
T234 |
1 |
|
T18 |
1 |
|
T90 |
1 |
| others[3] |
362 |
1 |
|
T68 |
1 |
|
T60 |
1 |
|
T235 |
1 |
| false |
127 |
1 |
|
T28 |
7 |
|
T201 |
1 |
|
T91 |
1 |
| true |
5764 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T8 |
10 |
|
T48 |
1 |
|
T32 |
16 |
| others[1] |
1237 |
1 |
|
T8 |
9 |
|
T32 |
19 |
|
T33 |
15 |
| others[2] |
1251 |
1 |
|
T8 |
10 |
|
T32 |
20 |
|
T33 |
11 |
| others[3] |
2049 |
1 |
|
T8 |
17 |
|
T12 |
1 |
|
T32 |
34 |
| false |
651 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
3 |
| true |
490 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1178 |
1 |
|
T8 |
6 |
|
T48 |
1 |
|
T32 |
17 |
| others[1] |
1244 |
1 |
|
T8 |
9 |
|
T31 |
1 |
|
T120 |
1 |
| others[2] |
1255 |
1 |
|
T2 |
1 |
|
T8 |
15 |
|
T61 |
1 |
| others[3] |
2099 |
1 |
|
T8 |
16 |
|
T32 |
37 |
|
T33 |
24 |
| false |
682 |
1 |
|
T1 |
1 |
|
T8 |
3 |
|
T32 |
9 |
| true |
464 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
119 |
1 |
|
T125 |
1 |
|
T90 |
1 |
|
T28 |
3 |
| others[1] |
99 |
1 |
|
T68 |
1 |
|
T28 |
7 |
|
T206 |
1 |
| others[2] |
113 |
1 |
|
T90 |
1 |
|
T412 |
1 |
|
T91 |
1 |
| others[3] |
165 |
1 |
|
T56 |
2 |
|
T235 |
1 |
|
T28 |
9 |
| false |
48 |
1 |
|
T235 |
1 |
|
T28 |
1 |
|
T78 |
2 |
| true |
6378 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T16 |
1 |
|
T261 |
1 |
|
T28 |
5 |
| others[1] |
242 |
1 |
|
T54 |
1 |
|
T72 |
1 |
|
T43 |
1 |
| others[2] |
243 |
1 |
|
T4 |
1 |
|
T132 |
1 |
|
T103 |
1 |
| others[3] |
405 |
1 |
|
T4 |
2 |
|
T25 |
1 |
|
T132 |
1 |
| false |
138 |
1 |
|
T4 |
2 |
|
T59 |
1 |
|
T60 |
1 |
| true |
5666 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1072 |
1 |
|
T8 |
5 |
|
T48 |
1 |
|
T32 |
11 |
| others[1] |
1104 |
1 |
|
T2 |
1 |
|
T8 |
11 |
|
T16 |
1 |
| others[2] |
1098 |
1 |
|
T8 |
16 |
|
T32 |
14 |
|
T33 |
7 |
| others[3] |
1726 |
1 |
|
T4 |
3 |
|
T8 |
13 |
|
T6 |
2 |
| false |
532 |
1 |
|
T1 |
1 |
|
T8 |
4 |
|
T67 |
1 |
| true |
1390 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
265 |
1 |
|
T25 |
1 |
|
T22 |
3 |
|
T59 |
1 |
| others[1] |
209 |
1 |
|
T22 |
1 |
|
T90 |
1 |
|
T28 |
6 |
| others[2] |
241 |
1 |
|
T132 |
1 |
|
T282 |
1 |
|
T133 |
1 |
| others[3] |
403 |
1 |
|
T3 |
1 |
|
T22 |
1 |
|
T132 |
1 |
| false |
120 |
1 |
|
T22 |
1 |
|
T37 |
1 |
|
T80 |
1 |
| true |
5684 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
220 |
1 |
|
T37 |
1 |
|
T18 |
1 |
|
T90 |
2 |
| others[1] |
207 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T223 |
1 |
| others[2] |
198 |
1 |
|
T16 |
1 |
|
T40 |
1 |
|
T28 |
6 |
| others[3] |
407 |
1 |
|
T4 |
1 |
|
T103 |
1 |
|
T235 |
2 |
| false |
126 |
1 |
|
T4 |
1 |
|
T67 |
1 |
|
T159 |
1 |
| true |
5764 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T8 |
7 |
|
T32 |
28 |
|
T33 |
16 |
| others[1] |
1230 |
1 |
|
T2 |
1 |
|
T8 |
6 |
|
T32 |
19 |
| others[2] |
1211 |
1 |
|
T8 |
14 |
|
T32 |
12 |
|
T33 |
13 |
| others[3] |
2130 |
1 |
|
T8 |
19 |
|
T22 |
1 |
|
T48 |
1 |
| false |
640 |
1 |
|
T1 |
1 |
|
T8 |
3 |
|
T120 |
1 |
| true |
481 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1261 |
1 |
|
T1 |
1 |
|
T8 |
10 |
|
T12 |
1 |
| others[1] |
1201 |
1 |
|
T8 |
19 |
|
T32 |
18 |
|
T33 |
10 |
| others[2] |
1232 |
1 |
|
T2 |
1 |
|
T8 |
7 |
|
T32 |
25 |
| others[3] |
2117 |
1 |
|
T8 |
10 |
|
T32 |
25 |
|
T33 |
26 |
| false |
641 |
1 |
|
T8 |
3 |
|
T120 |
1 |
|
T32 |
12 |
| true |
470 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
113 |
1 |
|
T133 |
1 |
|
T56 |
1 |
|
T90 |
2 |
| others[1] |
102 |
1 |
|
T90 |
1 |
|
T28 |
5 |
|
T412 |
1 |
| others[2] |
114 |
1 |
|
T90 |
1 |
|
T28 |
3 |
|
T154 |
1 |
| others[3] |
185 |
1 |
|
T235 |
1 |
|
T28 |
5 |
|
T417 |
1 |
| false |
55 |
1 |
|
T56 |
1 |
|
T235 |
1 |
|
T28 |
2 |
| true |
6353 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T22 |
2 |
| others[1] |
236 |
1 |
|
T31 |
1 |
|
T25 |
1 |
|
T30 |
1 |
| others[2] |
254 |
1 |
|
T4 |
2 |
|
T22 |
1 |
|
T104 |
1 |
| others[3] |
418 |
1 |
|
T4 |
1 |
|
T22 |
2 |
|
T37 |
1 |
| false |
134 |
1 |
|
T22 |
1 |
|
T18 |
1 |
|
T367 |
2 |
| true |
5649 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1035 |
1 |
|
T8 |
7 |
|
T6 |
1 |
|
T120 |
1 |
| others[1] |
1071 |
1 |
|
T1 |
1 |
|
T8 |
10 |
|
T16 |
1 |
| others[2] |
1105 |
1 |
|
T8 |
11 |
|
T25 |
1 |
|
T48 |
1 |
| others[3] |
1757 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
15 |
| false |
563 |
1 |
|
T8 |
6 |
|
T32 |
4 |
|
T33 |
2 |
| true |
1391 |
1 |
|
T3 |
1 |
|
T4 |
5 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T22 |
2 |
|
T80 |
1 |
|
T28 |
9 |
| others[1] |
211 |
1 |
|
T16 |
1 |
|
T90 |
1 |
|
T28 |
9 |
| others[2] |
231 |
1 |
|
T31 |
1 |
|
T30 |
1 |
|
T37 |
1 |
| others[3] |
411 |
1 |
|
T22 |
3 |
|
T54 |
1 |
|
T125 |
1 |
| false |
124 |
1 |
|
T22 |
1 |
|
T43 |
1 |
|
T56 |
1 |
| true |
5716 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
219 |
1 |
|
T81 |
1 |
|
T28 |
6 |
|
T157 |
1 |
| others[1] |
233 |
1 |
|
T4 |
1 |
|
T28 |
6 |
|
T156 |
1 |
| others[2] |
258 |
1 |
|
T16 |
1 |
|
T59 |
1 |
|
T125 |
1 |
| others[3] |
403 |
1 |
|
T4 |
2 |
|
T30 |
1 |
|
T72 |
1 |
| false |
123 |
1 |
|
T68 |
1 |
|
T261 |
1 |
|
T28 |
6 |
| true |
5686 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T1 |
1 |
|
T8 |
13 |
|
T48 |
1 |
| others[1] |
1292 |
1 |
|
T2 |
1 |
|
T8 |
7 |
|
T120 |
1 |
| others[2] |
1215 |
1 |
|
T3 |
1 |
|
T8 |
14 |
|
T32 |
21 |
| others[3] |
2060 |
1 |
|
T8 |
12 |
|
T12 |
1 |
|
T32 |
31 |
| false |
625 |
1 |
|
T8 |
3 |
|
T32 |
7 |
|
T33 |
8 |
| true |
491 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T8 |
14 |
|
T32 |
21 |
|
T33 |
11 |
| others[1] |
1226 |
1 |
|
T8 |
5 |
|
T120 |
1 |
|
T32 |
14 |
| others[2] |
1230 |
1 |
|
T2 |
1 |
|
T8 |
10 |
|
T32 |
17 |
| others[3] |
2121 |
1 |
|
T1 |
1 |
|
T8 |
16 |
|
T32 |
36 |
| false |
631 |
1 |
|
T8 |
4 |
|
T32 |
12 |
|
T33 |
3 |
| true |
479 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
106 |
1 |
|
T240 |
1 |
|
T235 |
1 |
|
T40 |
1 |
| others[1] |
91 |
1 |
|
T104 |
1 |
|
T28 |
1 |
|
T78 |
2 |
| others[2] |
109 |
1 |
|
T56 |
1 |
|
T235 |
1 |
|
T28 |
6 |
| others[3] |
199 |
1 |
|
T54 |
1 |
|
T56 |
1 |
|
T28 |
4 |
| false |
49 |
1 |
|
T28 |
4 |
|
T158 |
1 |
|
T418 |
1 |
| true |
6368 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
248 |
1 |
|
T22 |
1 |
|
T132 |
1 |
|
T56 |
1 |
| others[1] |
224 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T234 |
1 |
| others[2] |
248 |
1 |
|
T4 |
1 |
|
T22 |
2 |
|
T125 |
1 |
| others[3] |
413 |
1 |
|
T4 |
1 |
|
T31 |
1 |
|
T25 |
1 |
| false |
102 |
1 |
|
T28 |
5 |
|
T201 |
1 |
|
T285 |
1 |
| true |
5687 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1124 |
1 |
|
T5 |
1 |
|
T8 |
10 |
|
T32 |
14 |
| others[1] |
1046 |
1 |
|
T8 |
6 |
|
T120 |
1 |
|
T32 |
5 |
| others[2] |
1057 |
1 |
|
T4 |
1 |
|
T8 |
13 |
|
T12 |
1 |
| others[3] |
1735 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| false |
590 |
1 |
|
T8 |
9 |
|
T32 |
4 |
|
T33 |
2 |
| true |
1370 |
1 |
|
T4 |
5 |
|
T16 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
262 |
1 |
|
T67 |
1 |
|
T54 |
1 |
|
T60 |
1 |
| others[1] |
231 |
1 |
|
T234 |
1 |
|
T125 |
1 |
|
T241 |
1 |
| others[2] |
241 |
1 |
|
T103 |
1 |
|
T367 |
1 |
|
T223 |
1 |
| others[3] |
395 |
1 |
|
T31 |
1 |
|
T59 |
1 |
|
T72 |
1 |
| false |
108 |
1 |
|
T235 |
1 |
|
T28 |
5 |
|
T157 |
1 |
| true |
5685 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T90 |
1 |
|
T28 |
10 |
|
T203 |
1 |
| others[1] |
240 |
1 |
|
T104 |
1 |
|
T37 |
1 |
|
T18 |
2 |
| others[2] |
236 |
1 |
|
T4 |
3 |
|
T59 |
1 |
|
T72 |
1 |
| others[3] |
397 |
1 |
|
T4 |
2 |
|
T30 |
1 |
|
T68 |
1 |
| false |
119 |
1 |
|
T3 |
1 |
|
T133 |
1 |
|
T90 |
1 |
| true |
5702 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1287 |
1 |
|
T8 |
6 |
|
T32 |
24 |
|
T132 |
1 |
| others[1] |
1310 |
1 |
|
T8 |
10 |
|
T32 |
16 |
|
T33 |
12 |
| others[2] |
1209 |
1 |
|
T2 |
1 |
|
T8 |
9 |
|
T32 |
21 |
| others[3] |
2022 |
1 |
|
T1 |
1 |
|
T8 |
18 |
|
T120 |
1 |
| false |
608 |
1 |
|
T8 |
6 |
|
T32 |
11 |
|
T33 |
7 |
| true |
486 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1231 |
1 |
|
T1 |
1 |
|
T8 |
12 |
|
T120 |
1 |
| others[1] |
1284 |
1 |
|
T8 |
5 |
|
T32 |
18 |
|
T33 |
10 |
| others[2] |
1250 |
1 |
|
T8 |
9 |
|
T32 |
24 |
|
T33 |
15 |
| others[3] |
2051 |
1 |
|
T2 |
1 |
|
T8 |
18 |
|
T32 |
31 |
| false |
637 |
1 |
|
T8 |
5 |
|
T32 |
14 |
|
T33 |
14 |
| true |
469 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
98 |
1 |
|
T235 |
2 |
|
T411 |
1 |
|
T78 |
3 |
| others[1] |
97 |
1 |
|
T28 |
1 |
|
T412 |
1 |
|
T410 |
1 |
| others[2] |
98 |
1 |
|
T103 |
1 |
|
T28 |
2 |
|
T411 |
1 |
| others[3] |
180 |
1 |
|
T234 |
1 |
|
T56 |
1 |
|
T28 |
8 |
| false |
58 |
1 |
|
T56 |
1 |
|
T211 |
1 |
|
T28 |
1 |
| true |
6391 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |