Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T37 |
14 |
|
T56 |
1 |
|
T104 |
1 |
| others[1] |
275 |
1 |
|
T15 |
1 |
|
T37 |
6 |
|
T41 |
1 |
| others[2] |
228 |
1 |
|
T37 |
11 |
|
T56 |
1 |
|
T46 |
1 |
| others[3] |
386 |
1 |
|
T17 |
1 |
|
T37 |
15 |
|
T55 |
1 |
| false |
134 |
1 |
|
T37 |
5 |
|
T56 |
1 |
|
T90 |
1 |
| true |
5556 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T37 |
9 |
|
T67 |
1 |
|
T6 |
1 |
| others[1] |
218 |
1 |
|
T37 |
11 |
|
T44 |
1 |
|
T8 |
1 |
| others[2] |
230 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T37 |
9 |
| others[3] |
367 |
1 |
|
T37 |
16 |
|
T76 |
1 |
|
T55 |
1 |
| false |
135 |
1 |
|
T37 |
7 |
|
T235 |
1 |
|
T19 |
1 |
| true |
5630 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1234 |
1 |
|
T3 |
16 |
|
T9 |
1 |
|
T18 |
17 |
| others[1] |
1191 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T16 |
1 |
| others[2] |
1247 |
1 |
|
T3 |
8 |
|
T18 |
18 |
|
T26 |
8 |
| others[3] |
2031 |
1 |
|
T3 |
10 |
|
T18 |
35 |
|
T26 |
19 |
| false |
631 |
1 |
|
T3 |
6 |
|
T18 |
12 |
|
T26 |
10 |
| true |
485 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1201 |
1 |
|
T3 |
11 |
|
T18 |
16 |
|
T26 |
13 |
| others[1] |
1175 |
1 |
|
T3 |
6 |
|
T15 |
1 |
|
T9 |
1 |
| others[2] |
1272 |
1 |
|
T3 |
11 |
|
T16 |
1 |
|
T18 |
17 |
| others[3] |
2051 |
1 |
|
T3 |
17 |
|
T18 |
36 |
|
T26 |
18 |
| false |
648 |
1 |
|
T3 |
6 |
|
T18 |
12 |
|
T26 |
6 |
| true |
472 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T37 |
4 |
|
T38 |
1 |
|
T86 |
10 |
| others[1] |
110 |
1 |
|
T37 |
4 |
|
T90 |
1 |
|
T309 |
1 |
| others[2] |
117 |
1 |
|
T37 |
2 |
|
T90 |
1 |
|
T405 |
1 |
| others[3] |
158 |
1 |
|
T15 |
1 |
|
T37 |
5 |
|
T235 |
1 |
| false |
45 |
1 |
|
T37 |
5 |
|
T38 |
3 |
|
T406 |
1 |
| true |
6280 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T15 |
1 |
|
T37 |
9 |
|
T44 |
1 |
| others[1] |
253 |
1 |
|
T37 |
14 |
|
T148 |
1 |
|
T6 |
1 |
| others[2] |
237 |
1 |
|
T37 |
11 |
|
T90 |
1 |
|
T8 |
1 |
| others[3] |
379 |
1 |
|
T17 |
1 |
|
T37 |
19 |
|
T67 |
1 |
| false |
136 |
1 |
|
T37 |
1 |
|
T8 |
1 |
|
T202 |
1 |
| true |
5578 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T9 |
1 |
| others[1] |
1051 |
1 |
|
T3 |
13 |
|
T16 |
1 |
|
T18 |
13 |
| others[2] |
1037 |
1 |
|
T3 |
9 |
|
T18 |
8 |
|
T26 |
10 |
| others[3] |
1798 |
1 |
|
T3 |
16 |
|
T17 |
1 |
|
T18 |
17 |
| false |
558 |
1 |
|
T3 |
4 |
|
T18 |
6 |
|
T26 |
4 |
| true |
1338 |
1 |
|
T18 |
44 |
|
T26 |
28 |
|
T67 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T37 |
11 |
|
T55 |
1 |
|
T124 |
1 |
| others[1] |
224 |
1 |
|
T37 |
12 |
|
T76 |
1 |
|
T88 |
1 |
| others[2] |
225 |
1 |
|
T37 |
9 |
|
T148 |
1 |
|
T41 |
1 |
| others[3] |
412 |
1 |
|
T70 |
1 |
|
T37 |
11 |
|
T42 |
1 |
| false |
123 |
1 |
|
T37 |
6 |
|
T104 |
1 |
|
T400 |
1 |
| true |
5598 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T17 |
1 |
|
T37 |
7 |
|
T67 |
1 |
| others[1] |
237 |
1 |
|
T37 |
11 |
|
T76 |
1 |
|
T60 |
1 |
| others[2] |
218 |
1 |
|
T37 |
6 |
|
T55 |
1 |
|
T8 |
1 |
| others[3] |
358 |
1 |
|
T37 |
12 |
|
T6 |
1 |
|
T90 |
1 |
| false |
115 |
1 |
|
T37 |
7 |
|
T63 |
1 |
|
T90 |
1 |
| true |
5680 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1226 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T9 |
1 |
| others[1] |
1247 |
1 |
|
T3 |
12 |
|
T18 |
18 |
|
T26 |
16 |
| others[2] |
1205 |
1 |
|
T3 |
9 |
|
T18 |
22 |
|
T26 |
12 |
| others[3] |
2034 |
1 |
|
T3 |
15 |
|
T16 |
1 |
|
T18 |
29 |
| false |
613 |
1 |
|
T3 |
8 |
|
T18 |
11 |
|
T26 |
3 |
| true |
494 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1212 |
1 |
|
T3 |
7 |
|
T18 |
21 |
|
T26 |
14 |
| others[1] |
1240 |
1 |
|
T3 |
8 |
|
T18 |
14 |
|
T26 |
10 |
| others[2] |
1178 |
1 |
|
T3 |
10 |
|
T9 |
1 |
|
T18 |
13 |
| others[3] |
2098 |
1 |
|
T3 |
20 |
|
T15 |
1 |
|
T18 |
39 |
| false |
611 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T18 |
13 |
| true |
480 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
76 |
1 |
|
T37 |
1 |
|
T203 |
1 |
|
T38 |
2 |
| others[1] |
114 |
1 |
|
T37 |
4 |
|
T241 |
1 |
|
T38 |
5 |
| others[2] |
117 |
1 |
|
T15 |
1 |
|
T37 |
3 |
|
T157 |
1 |
| others[3] |
182 |
1 |
|
T17 |
1 |
|
T37 |
6 |
|
T63 |
1 |
| false |
59 |
1 |
|
T37 |
2 |
|
T235 |
1 |
|
T38 |
6 |
| true |
6271 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T37 |
9 |
|
T40 |
1 |
|
T90 |
1 |
| others[1] |
246 |
1 |
|
T37 |
10 |
|
T88 |
1 |
|
T6 |
1 |
| others[2] |
241 |
1 |
|
T37 |
4 |
|
T67 |
1 |
|
T42 |
1 |
| others[3] |
424 |
1 |
|
T70 |
1 |
|
T11 |
1 |
|
T37 |
18 |
| false |
138 |
1 |
|
T37 |
3 |
|
T44 |
1 |
|
T56 |
1 |
| true |
5528 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1044 |
1 |
|
T3 |
12 |
|
T9 |
1 |
|
T18 |
8 |
| others[1] |
1079 |
1 |
|
T3 |
11 |
|
T18 |
7 |
|
T26 |
5 |
| others[2] |
1041 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T16 |
1 |
| others[3] |
1678 |
1 |
|
T3 |
16 |
|
T17 |
1 |
|
T18 |
17 |
| false |
536 |
1 |
|
T3 |
3 |
|
T18 |
5 |
|
T26 |
5 |
| true |
1441 |
1 |
|
T18 |
52 |
|
T26 |
27 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
243 |
1 |
|
T17 |
1 |
|
T11 |
1 |
|
T37 |
15 |
| others[1] |
242 |
1 |
|
T37 |
11 |
|
T56 |
3 |
|
T104 |
1 |
| others[2] |
263 |
1 |
|
T37 |
11 |
|
T67 |
1 |
|
T56 |
1 |
| others[3] |
373 |
1 |
|
T37 |
19 |
|
T41 |
1 |
|
T55 |
1 |
| false |
118 |
1 |
|
T37 |
3 |
|
T90 |
1 |
|
T235 |
1 |
| true |
5580 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T15 |
1 |
|
T37 |
11 |
|
T90 |
1 |
| others[1] |
209 |
1 |
|
T11 |
1 |
|
T37 |
13 |
|
T55 |
1 |
| others[2] |
225 |
1 |
|
T17 |
1 |
|
T37 |
9 |
|
T397 |
1 |
| others[3] |
366 |
1 |
|
T70 |
1 |
|
T37 |
12 |
|
T76 |
1 |
| false |
109 |
1 |
|
T37 |
2 |
|
T90 |
1 |
|
T205 |
1 |
| true |
5678 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1235 |
1 |
|
T3 |
9 |
|
T18 |
23 |
|
T26 |
7 |
| others[1] |
1185 |
1 |
|
T3 |
7 |
|
T9 |
1 |
|
T18 |
16 |
| others[2] |
1197 |
1 |
|
T3 |
10 |
|
T15 |
1 |
|
T18 |
22 |
| others[3] |
2090 |
1 |
|
T3 |
20 |
|
T16 |
1 |
|
T18 |
31 |
| false |
636 |
1 |
|
T3 |
5 |
|
T18 |
8 |
|
T26 |
5 |
| true |
476 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1187 |
1 |
|
T3 |
13 |
|
T9 |
1 |
|
T18 |
19 |
| others[1] |
1215 |
1 |
|
T3 |
8 |
|
T18 |
13 |
|
T26 |
13 |
| others[2] |
1269 |
1 |
|
T3 |
8 |
|
T18 |
22 |
|
T26 |
12 |
| others[3] |
1976 |
1 |
|
T3 |
17 |
|
T15 |
1 |
|
T16 |
1 |
| false |
701 |
1 |
|
T3 |
5 |
|
T18 |
11 |
|
T26 |
5 |
| true |
471 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
108 |
1 |
|
T37 |
5 |
|
T90 |
1 |
|
T235 |
1 |
| others[1] |
115 |
1 |
|
T37 |
5 |
|
T405 |
1 |
|
T38 |
3 |
| others[2] |
104 |
1 |
|
T17 |
1 |
|
T37 |
3 |
|
T90 |
1 |
| others[3] |
192 |
1 |
|
T37 |
5 |
|
T76 |
1 |
|
T44 |
1 |
| false |
57 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T235 |
1 |
| true |
6243 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T15 |
1 |
|
T37 |
12 |
|
T55 |
1 |
| others[1] |
267 |
1 |
|
T37 |
8 |
|
T148 |
1 |
|
T6 |
1 |
| others[2] |
236 |
1 |
|
T37 |
4 |
|
T76 |
1 |
|
T67 |
1 |
| others[3] |
397 |
1 |
|
T17 |
1 |
|
T37 |
18 |
|
T6 |
2 |
| false |
113 |
1 |
|
T11 |
1 |
|
T37 |
5 |
|
T88 |
1 |
| true |
5560 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1020 |
1 |
|
T3 |
8 |
|
T16 |
1 |
|
T18 |
6 |
| others[1] |
1021 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T18 |
10 |
| others[2] |
1035 |
1 |
|
T3 |
6 |
|
T18 |
7 |
|
T26 |
4 |
| others[3] |
1754 |
1 |
|
T3 |
26 |
|
T18 |
14 |
|
T26 |
2 |
| false |
543 |
1 |
|
T3 |
2 |
|
T9 |
1 |
|
T18 |
7 |
| true |
1446 |
1 |
|
T17 |
1 |
|
T18 |
56 |
|
T26 |
41 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T37 |
7 |
|
T67 |
1 |
|
T44 |
1 |
| others[1] |
227 |
1 |
|
T37 |
11 |
|
T41 |
1 |
|
T216 |
1 |
| others[2] |
243 |
1 |
|
T37 |
11 |
|
T55 |
1 |
|
T397 |
1 |
| others[3] |
386 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T37 |
18 |
| false |
124 |
1 |
|
T37 |
3 |
|
T148 |
1 |
|
T157 |
1 |
| true |
5586 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T37 |
10 |
|
T55 |
1 |
|
T6 |
2 |
| others[1] |
216 |
1 |
|
T70 |
1 |
|
T37 |
10 |
|
T88 |
1 |
| others[2] |
231 |
1 |
|
T37 |
9 |
|
T76 |
1 |
|
T63 |
1 |
| others[3] |
396 |
1 |
|
T37 |
18 |
|
T148 |
1 |
|
T44 |
1 |
| false |
112 |
1 |
|
T37 |
6 |
|
T38 |
6 |
|
T86 |
6 |
| true |
5624 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1251 |
1 |
|
T3 |
16 |
|
T18 |
15 |
|
T26 |
8 |
| others[1] |
1205 |
1 |
|
T3 |
10 |
|
T15 |
1 |
|
T9 |
1 |
| others[2] |
1224 |
1 |
|
T3 |
11 |
|
T18 |
24 |
|
T26 |
11 |
| others[3] |
2001 |
1 |
|
T3 |
11 |
|
T16 |
1 |
|
T18 |
32 |
| false |
639 |
1 |
|
T3 |
3 |
|
T18 |
7 |
|
T26 |
8 |
| true |
499 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1195 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T16 |
1 |
| others[1] |
1216 |
1 |
|
T3 |
10 |
|
T18 |
18 |
|
T26 |
7 |
| others[2] |
1247 |
1 |
|
T3 |
10 |
|
T9 |
1 |
|
T18 |
18 |
| others[3] |
2057 |
1 |
|
T3 |
15 |
|
T18 |
38 |
|
T26 |
19 |
| false |
645 |
1 |
|
T3 |
5 |
|
T18 |
14 |
|
T26 |
10 |
| true |
459 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T37 |
7 |
|
T90 |
2 |
|
T38 |
2 |
| others[1] |
115 |
1 |
|
T15 |
1 |
|
T37 |
4 |
|
T157 |
1 |
| others[2] |
110 |
1 |
|
T37 |
1 |
|
T235 |
2 |
|
T205 |
1 |
| others[3] |
166 |
1 |
|
T37 |
8 |
|
T63 |
1 |
|
T216 |
1 |
| false |
55 |
1 |
|
T11 |
1 |
|
T38 |
2 |
|
T86 |
3 |
| true |
6269 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T15 |
1 |
|
T37 |
8 |
|
T76 |
1 |
| others[1] |
213 |
1 |
|
T37 |
14 |
|
T6 |
1 |
|
T46 |
1 |
| others[2] |
255 |
1 |
|
T70 |
1 |
|
T37 |
10 |
|
T148 |
1 |
| others[3] |
400 |
1 |
|
T17 |
1 |
|
T37 |
12 |
|
T40 |
1 |
| false |
143 |
1 |
|
T37 |
4 |
|
T42 |
1 |
|
T56 |
1 |
| true |
5553 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |