Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank0_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
231 |
1 |
|
T34 |
1 |
|
T56 |
1 |
|
T392 |
1 |
| others[1] |
270 |
1 |
|
T51 |
1 |
|
T63 |
1 |
|
T206 |
2 |
| others[2] |
240 |
1 |
|
T63 |
2 |
|
T28 |
10 |
|
T158 |
1 |
| others[3] |
393 |
1 |
|
T32 |
1 |
|
T9 |
1 |
|
T72 |
1 |
| false |
127 |
1 |
|
T37 |
1 |
|
T63 |
2 |
|
T46 |
1 |
| true |
5636 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
218 |
1 |
|
T5 |
2 |
|
T28 |
4 |
|
T7 |
1 |
| others[1] |
226 |
1 |
|
T15 |
1 |
|
T56 |
1 |
|
T28 |
12 |
| others[2] |
228 |
1 |
|
T50 |
1 |
|
T5 |
1 |
|
T206 |
1 |
| others[3] |
391 |
1 |
|
T22 |
1 |
|
T33 |
1 |
|
T81 |
1 |
| false |
105 |
1 |
|
T51 |
1 |
|
T207 |
1 |
|
T28 |
8 |
| true |
5729 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1220 |
1 |
|
T3 |
6 |
|
T17 |
19 |
|
T29 |
13 |
| others[1] |
1235 |
1 |
|
T3 |
11 |
|
T13 |
1 |
|
T14 |
1 |
| others[2] |
1209 |
1 |
|
T3 |
10 |
|
T17 |
19 |
|
T29 |
11 |
| others[3] |
2099 |
1 |
|
T3 |
17 |
|
T15 |
1 |
|
T17 |
32 |
| false |
634 |
1 |
|
T3 |
7 |
|
T17 |
14 |
|
T29 |
6 |
| true |
500 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1242 |
1 |
|
T3 |
10 |
|
T14 |
1 |
|
T17 |
23 |
| others[1] |
1181 |
1 |
|
T3 |
13 |
|
T17 |
16 |
|
T29 |
14 |
| others[2] |
1225 |
1 |
|
T3 |
8 |
|
T13 |
1 |
|
T15 |
1 |
| others[3] |
2117 |
1 |
|
T3 |
10 |
|
T17 |
30 |
|
T29 |
16 |
| false |
646 |
1 |
|
T3 |
10 |
|
T17 |
11 |
|
T29 |
6 |
| true |
486 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
107 |
1 |
|
T28 |
4 |
|
T393 |
1 |
|
T394 |
1 |
| others[1] |
106 |
1 |
|
T28 |
4 |
|
T113 |
1 |
|
T393 |
1 |
| others[2] |
102 |
1 |
|
T15 |
1 |
|
T206 |
1 |
|
T233 |
1 |
| others[3] |
187 |
1 |
|
T56 |
1 |
|
T206 |
1 |
|
T28 |
7 |
| false |
47 |
1 |
|
T28 |
2 |
|
T31 |
1 |
|
T42 |
1 |
| true |
6348 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
253 |
1 |
|
T33 |
1 |
|
T35 |
1 |
|
T63 |
2 |
| others[1] |
233 |
1 |
|
T62 |
1 |
|
T5 |
1 |
|
T81 |
1 |
| others[2] |
260 |
1 |
|
T9 |
1 |
|
T22 |
1 |
|
T5 |
3 |
| others[3] |
366 |
1 |
|
T15 |
1 |
|
T72 |
1 |
|
T34 |
1 |
| false |
124 |
1 |
|
T5 |
1 |
|
T205 |
1 |
|
T28 |
10 |
| true |
5661 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1073 |
1 |
|
T3 |
6 |
|
T15 |
1 |
|
T17 |
10 |
| others[1] |
1042 |
1 |
|
T3 |
13 |
|
T13 |
1 |
|
T14 |
1 |
| others[2] |
1049 |
1 |
|
T3 |
6 |
|
T17 |
12 |
|
T29 |
2 |
| others[3] |
1772 |
1 |
|
T3 |
20 |
|
T16 |
1 |
|
T17 |
13 |
| false |
531 |
1 |
|
T3 |
6 |
|
T17 |
4 |
|
T29 |
4 |
| true |
1430 |
1 |
|
T17 |
49 |
|
T18 |
1 |
|
T29 |
41 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
218 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T56 |
1 |
| others[1] |
262 |
1 |
|
T63 |
2 |
|
T81 |
1 |
|
T392 |
1 |
| others[2] |
225 |
1 |
|
T32 |
1 |
|
T22 |
1 |
|
T34 |
1 |
| others[3] |
390 |
1 |
|
T9 |
1 |
|
T72 |
1 |
|
T33 |
1 |
| false |
121 |
1 |
|
T28 |
4 |
|
T300 |
1 |
|
T31 |
6 |
| true |
5681 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
208 |
1 |
|
T5 |
1 |
|
T81 |
1 |
|
T28 |
7 |
| others[1] |
232 |
1 |
|
T9 |
1 |
|
T72 |
1 |
|
T5 |
1 |
| others[2] |
220 |
1 |
|
T15 |
1 |
|
T51 |
1 |
|
T5 |
1 |
| others[3] |
388 |
1 |
|
T18 |
1 |
|
T81 |
1 |
|
T56 |
1 |
| false |
134 |
1 |
|
T32 |
1 |
|
T5 |
1 |
|
T28 |
4 |
| true |
5715 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1294 |
1 |
|
T3 |
13 |
|
T13 |
1 |
|
T17 |
22 |
| others[1] |
1245 |
1 |
|
T3 |
14 |
|
T17 |
14 |
|
T29 |
13 |
| others[2] |
1200 |
1 |
|
T3 |
7 |
|
T17 |
17 |
|
T29 |
7 |
| others[3] |
2042 |
1 |
|
T3 |
13 |
|
T14 |
1 |
|
T15 |
1 |
| false |
623 |
1 |
|
T3 |
4 |
|
T16 |
1 |
|
T17 |
10 |
| true |
493 |
1 |
|
T18 |
1 |
|
T32 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1243 |
1 |
|
T3 |
12 |
|
T17 |
20 |
|
T29 |
9 |
| others[1] |
1246 |
1 |
|
T3 |
9 |
|
T17 |
22 |
|
T29 |
13 |
| others[2] |
1237 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T17 |
24 |
| others[3] |
2049 |
1 |
|
T3 |
16 |
|
T13 |
1 |
|
T14 |
1 |
| false |
638 |
1 |
|
T3 |
5 |
|
T17 |
10 |
|
T29 |
2 |
| true |
484 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
89 |
1 |
|
T15 |
1 |
|
T28 |
4 |
|
T393 |
1 |
| others[1] |
112 |
1 |
|
T9 |
1 |
|
T28 |
4 |
|
T31 |
5 |
| others[2] |
126 |
1 |
|
T71 |
1 |
|
T206 |
2 |
|
T28 |
3 |
| others[3] |
159 |
1 |
|
T28 |
5 |
|
T393 |
1 |
|
T394 |
1 |
| false |
57 |
1 |
|
T28 |
3 |
|
T31 |
1 |
|
T42 |
1 |
| true |
6354 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
245 |
1 |
|
T28 |
12 |
|
T7 |
2 |
|
T246 |
1 |
| others[1] |
237 |
1 |
|
T34 |
1 |
|
T50 |
1 |
|
T81 |
2 |
| others[2] |
235 |
1 |
|
T18 |
1 |
|
T22 |
1 |
|
T72 |
1 |
| others[3] |
375 |
1 |
|
T16 |
1 |
|
T32 |
1 |
|
T51 |
1 |
| false |
129 |
1 |
|
T35 |
1 |
|
T28 |
5 |
|
T31 |
10 |
| true |
5676 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1071 |
1 |
|
T3 |
14 |
|
T17 |
12 |
|
T29 |
12 |
| others[1] |
1061 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T17 |
11 |
| others[2] |
1024 |
1 |
|
T3 |
15 |
|
T17 |
19 |
|
T18 |
1 |
| others[3] |
1835 |
1 |
|
T3 |
12 |
|
T14 |
1 |
|
T17 |
14 |
| false |
507 |
1 |
|
T3 |
3 |
|
T13 |
1 |
|
T17 |
2 |
| true |
1399 |
1 |
|
T16 |
1 |
|
T17 |
42 |
|
T29 |
23 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
249 |
1 |
|
T72 |
1 |
|
T37 |
1 |
|
T46 |
1 |
| others[1] |
238 |
1 |
|
T15 |
1 |
|
T81 |
1 |
|
T124 |
1 |
| others[2] |
231 |
1 |
|
T16 |
1 |
|
T205 |
1 |
|
T28 |
9 |
| others[3] |
384 |
1 |
|
T81 |
1 |
|
T392 |
1 |
|
T28 |
21 |
| false |
121 |
1 |
|
T62 |
1 |
|
T392 |
1 |
|
T213 |
1 |
| true |
5674 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
231 |
1 |
|
T18 |
1 |
|
T5 |
1 |
|
T81 |
1 |
| others[1] |
231 |
1 |
|
T50 |
1 |
|
T5 |
2 |
|
T81 |
1 |
| others[2] |
213 |
1 |
|
T71 |
1 |
|
T72 |
1 |
|
T81 |
1 |
| others[3] |
376 |
1 |
|
T5 |
1 |
|
T28 |
15 |
|
T7 |
1 |
| false |
123 |
1 |
|
T16 |
1 |
|
T5 |
1 |
|
T28 |
4 |
| true |
5723 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1182 |
1 |
|
T3 |
8 |
|
T13 |
1 |
|
T15 |
1 |
| others[1] |
1221 |
1 |
|
T3 |
10 |
|
T17 |
23 |
|
T29 |
12 |
| others[2] |
1206 |
1 |
|
T3 |
12 |
|
T17 |
15 |
|
T29 |
9 |
| others[3] |
2091 |
1 |
|
T3 |
14 |
|
T14 |
1 |
|
T17 |
26 |
| false |
707 |
1 |
|
T3 |
7 |
|
T17 |
11 |
|
T29 |
5 |
| true |
490 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1198 |
1 |
|
T3 |
9 |
|
T17 |
16 |
|
T29 |
12 |
| others[1] |
1242 |
1 |
|
T3 |
13 |
|
T17 |
20 |
|
T29 |
10 |
| others[2] |
1246 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T17 |
24 |
| others[3] |
2122 |
1 |
|
T3 |
16 |
|
T13 |
1 |
|
T17 |
30 |
| false |
623 |
1 |
|
T3 |
6 |
|
T14 |
1 |
|
T17 |
10 |
| true |
466 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
89 |
1 |
|
T206 |
1 |
|
T28 |
3 |
|
T393 |
1 |
| others[1] |
108 |
1 |
|
T22 |
1 |
|
T72 |
1 |
|
T50 |
1 |
| others[2] |
99 |
1 |
|
T9 |
1 |
|
T28 |
2 |
|
T31 |
3 |
| others[3] |
164 |
1 |
|
T15 |
1 |
|
T206 |
1 |
|
T28 |
10 |
| false |
61 |
1 |
|
T28 |
1 |
|
T31 |
2 |
|
T42 |
5 |
| true |
6376 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
260 |
1 |
|
T18 |
1 |
|
T63 |
2 |
|
T28 |
10 |
| others[1] |
259 |
1 |
|
T50 |
1 |
|
T63 |
1 |
|
T28 |
11 |
| others[2] |
242 |
1 |
|
T5 |
1 |
|
T233 |
1 |
|
T213 |
1 |
| others[3] |
396 |
1 |
|
T16 |
1 |
|
T9 |
1 |
|
T34 |
1 |
| false |
134 |
1 |
|
T81 |
2 |
|
T28 |
4 |
|
T7 |
1 |
| true |
5606 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1002 |
1 |
|
T3 |
10 |
|
T17 |
4 |
|
T29 |
5 |
| others[1] |
1067 |
1 |
|
T3 |
16 |
|
T17 |
7 |
|
T29 |
7 |
| others[2] |
1087 |
1 |
|
T3 |
8 |
|
T14 |
1 |
|
T17 |
13 |
| others[3] |
1781 |
1 |
|
T3 |
15 |
|
T13 |
1 |
|
T15 |
1 |
| false |
537 |
1 |
|
T3 |
2 |
|
T17 |
7 |
|
T29 |
2 |
| true |
1423 |
1 |
|
T16 |
1 |
|
T17 |
50 |
|
T29 |
37 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
230 |
1 |
|
T63 |
1 |
|
T28 |
8 |
|
T166 |
1 |
| others[1] |
258 |
1 |
|
T63 |
1 |
|
T95 |
1 |
|
T56 |
1 |
| others[2] |
231 |
1 |
|
T16 |
1 |
|
T71 |
1 |
|
T37 |
1 |
| others[3] |
408 |
1 |
|
T63 |
3 |
|
T206 |
1 |
|
T207 |
1 |
| false |
108 |
1 |
|
T51 |
1 |
|
T28 |
3 |
|
T31 |
2 |
| true |
5662 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
214 |
1 |
|
T51 |
1 |
|
T81 |
1 |
|
T206 |
1 |
| others[1] |
224 |
1 |
|
T72 |
1 |
|
T33 |
1 |
|
T5 |
1 |
| others[2] |
217 |
1 |
|
T28 |
7 |
|
T168 |
1 |
|
T393 |
1 |
| others[3] |
400 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T50 |
1 |
| false |
115 |
1 |
|
T5 |
1 |
|
T205 |
1 |
|
T28 |
5 |
| true |
5727 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1227 |
1 |
|
T3 |
14 |
|
T17 |
11 |
|
T29 |
17 |
| others[1] |
1200 |
1 |
|
T3 |
10 |
|
T14 |
1 |
|
T15 |
1 |
| others[2] |
1238 |
1 |
|
T3 |
8 |
|
T13 |
1 |
|
T17 |
23 |
| others[3] |
2090 |
1 |
|
T3 |
15 |
|
T17 |
35 |
|
T29 |
18 |
| false |
638 |
1 |
|
T3 |
4 |
|
T17 |
11 |
|
T29 |
5 |
| true |
504 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1209 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T17 |
15 |
| others[1] |
1233 |
1 |
|
T3 |
12 |
|
T17 |
22 |
|
T29 |
12 |
| others[2] |
1233 |
1 |
|
T3 |
7 |
|
T17 |
23 |
|
T29 |
10 |
| others[3] |
2076 |
1 |
|
T3 |
16 |
|
T13 |
1 |
|
T14 |
1 |
| false |
666 |
1 |
|
T3 |
5 |
|
T17 |
13 |
|
T29 |
10 |
| true |
480 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
109 |
1 |
|
T51 |
1 |
|
T28 |
1 |
|
T166 |
1 |
| others[1] |
105 |
1 |
|
T206 |
1 |
|
T28 |
3 |
|
T31 |
9 |
| others[2] |
100 |
1 |
|
T206 |
1 |
|
T213 |
1 |
|
T28 |
6 |
| others[3] |
163 |
1 |
|
T15 |
1 |
|
T28 |
8 |
|
T395 |
1 |
| false |
44 |
1 |
|
T28 |
1 |
|
T31 |
2 |
|
T42 |
2 |
| true |
6376 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
222 |
1 |
|
T32 |
1 |
|
T71 |
1 |
|
T46 |
1 |
| others[1] |
227 |
1 |
|
T5 |
3 |
|
T63 |
1 |
|
T205 |
1 |
| others[2] |
254 |
1 |
|
T9 |
1 |
|
T37 |
1 |
|
T62 |
1 |
| others[3] |
410 |
1 |
|
T5 |
1 |
|
T63 |
4 |
|
T81 |
1 |
| false |
123 |
1 |
|
T72 |
1 |
|
T35 |
1 |
|
T81 |
1 |
| true |
5661 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |