Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1065 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T18 |
12 |
| others[1] |
1055 |
1 |
|
T3 |
10 |
|
T16 |
1 |
|
T18 |
9 |
| others[2] |
1037 |
1 |
|
T3 |
10 |
|
T9 |
1 |
|
T18 |
16 |
| others[3] |
1772 |
1 |
|
T3 |
18 |
|
T17 |
1 |
|
T18 |
19 |
| false |
496 |
1 |
|
T3 |
6 |
|
T18 |
4 |
|
T26 |
3 |
| true |
1394 |
1 |
|
T18 |
40 |
|
T26 |
38 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
241 |
1 |
|
T17 |
1 |
|
T37 |
11 |
|
T76 |
1 |
| others[1] |
271 |
1 |
|
T37 |
16 |
|
T56 |
1 |
|
T313 |
1 |
| others[2] |
235 |
1 |
|
T37 |
8 |
|
T41 |
1 |
|
T63 |
1 |
| others[3] |
404 |
1 |
|
T37 |
9 |
|
T148 |
1 |
|
T88 |
1 |
| false |
122 |
1 |
|
T70 |
1 |
|
T37 |
5 |
|
T401 |
1 |
| true |
5546 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T17 |
1 |
|
T37 |
7 |
|
T6 |
1 |
| others[1] |
216 |
1 |
|
T37 |
7 |
|
T55 |
1 |
|
T6 |
1 |
| others[2] |
229 |
1 |
|
T37 |
6 |
|
T309 |
1 |
|
T8 |
1 |
| others[3] |
425 |
1 |
|
T37 |
25 |
|
T76 |
1 |
|
T6 |
3 |
| false |
136 |
1 |
|
T11 |
1 |
|
T37 |
3 |
|
T148 |
1 |
| true |
5584 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1242 |
1 |
|
T3 |
10 |
|
T15 |
1 |
|
T18 |
20 |
| others[1] |
1218 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T18 |
12 |
| others[2] |
1156 |
1 |
|
T3 |
11 |
|
T17 |
1 |
|
T18 |
16 |
| others[3] |
2069 |
1 |
|
T3 |
18 |
|
T9 |
1 |
|
T18 |
39 |
| false |
648 |
1 |
|
T3 |
6 |
|
T18 |
13 |
|
T26 |
7 |
| true |
486 |
1 |
|
T70 |
1 |
|
T11 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1220 |
1 |
|
T3 |
8 |
|
T18 |
25 |
|
T26 |
8 |
| others[1] |
1245 |
1 |
|
T3 |
6 |
|
T18 |
20 |
|
T26 |
9 |
| others[2] |
1219 |
1 |
|
T3 |
11 |
|
T16 |
1 |
|
T18 |
20 |
| others[3] |
2034 |
1 |
|
T3 |
16 |
|
T15 |
1 |
|
T9 |
1 |
| false |
632 |
1 |
|
T3 |
10 |
|
T18 |
8 |
|
T26 |
6 |
| true |
469 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
93 |
1 |
|
T37 |
6 |
|
T235 |
1 |
|
T38 |
2 |
| others[1] |
113 |
1 |
|
T15 |
1 |
|
T37 |
4 |
|
T89 |
2 |
| others[2] |
109 |
1 |
|
T17 |
1 |
|
T11 |
1 |
|
T37 |
3 |
| others[3] |
201 |
1 |
|
T37 |
5 |
|
T67 |
1 |
|
T235 |
1 |
| false |
58 |
1 |
|
T38 |
3 |
|
T86 |
2 |
|
T226 |
1 |
| true |
6245 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T70 |
1 |
|
T37 |
11 |
|
T67 |
1 |
| others[1] |
239 |
1 |
|
T15 |
1 |
|
T37 |
12 |
|
T404 |
1 |
| others[2] |
257 |
1 |
|
T37 |
13 |
|
T40 |
1 |
|
T313 |
2 |
| others[3] |
373 |
1 |
|
T17 |
1 |
|
T11 |
1 |
|
T37 |
17 |
| false |
113 |
1 |
|
T37 |
5 |
|
T55 |
1 |
|
T90 |
1 |
| true |
5601 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1026 |
1 |
|
T3 |
11 |
|
T16 |
1 |
|
T18 |
9 |
| others[1] |
1057 |
1 |
|
T3 |
13 |
|
T9 |
1 |
|
T18 |
8 |
| others[2] |
1090 |
1 |
|
T3 |
8 |
|
T18 |
13 |
|
T26 |
4 |
| others[3] |
1718 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T18 |
17 |
| false |
500 |
1 |
|
T3 |
8 |
|
T18 |
5 |
|
T26 |
2 |
| true |
1428 |
1 |
|
T17 |
1 |
|
T18 |
48 |
|
T26 |
37 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T37 |
11 |
|
T55 |
1 |
|
T44 |
1 |
| others[1] |
249 |
1 |
|
T15 |
1 |
|
T37 |
7 |
|
T56 |
1 |
| others[2] |
246 |
1 |
|
T17 |
1 |
|
T37 |
12 |
|
T56 |
2 |
| others[3] |
407 |
1 |
|
T37 |
22 |
|
T76 |
1 |
|
T88 |
1 |
| false |
110 |
1 |
|
T37 |
3 |
|
T56 |
1 |
|
T90 |
1 |
| true |
5580 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T37 |
7 |
|
T401 |
1 |
|
T403 |
1 |
| others[1] |
245 |
1 |
|
T37 |
12 |
|
T6 |
2 |
|
T216 |
1 |
| others[2] |
215 |
1 |
|
T37 |
8 |
|
T235 |
1 |
|
T124 |
1 |
| others[3] |
386 |
1 |
|
T37 |
9 |
|
T148 |
1 |
|
T90 |
1 |
| false |
119 |
1 |
|
T70 |
1 |
|
T37 |
7 |
|
T60 |
1 |
| true |
5640 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1222 |
1 |
|
T3 |
13 |
|
T16 |
1 |
|
T18 |
18 |
| others[1] |
1246 |
1 |
|
T3 |
7 |
|
T18 |
21 |
|
T26 |
6 |
| others[2] |
1213 |
1 |
|
T3 |
12 |
|
T18 |
16 |
|
T26 |
12 |
| others[3] |
2023 |
1 |
|
T3 |
13 |
|
T15 |
1 |
|
T9 |
1 |
| false |
627 |
1 |
|
T3 |
6 |
|
T18 |
7 |
|
T26 |
7 |
| true |
488 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1265 |
1 |
|
T3 |
10 |
|
T18 |
23 |
|
T26 |
12 |
| others[1] |
1194 |
1 |
|
T3 |
9 |
|
T18 |
21 |
|
T26 |
13 |
| others[2] |
1214 |
1 |
|
T3 |
10 |
|
T16 |
1 |
|
T18 |
16 |
| others[3] |
2015 |
1 |
|
T3 |
18 |
|
T15 |
1 |
|
T9 |
1 |
| false |
653 |
1 |
|
T3 |
4 |
|
T18 |
8 |
|
T26 |
3 |
| true |
478 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T37 |
6 |
|
T38 |
3 |
|
T86 |
6 |
| others[1] |
120 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T397 |
1 |
| others[2] |
117 |
1 |
|
T37 |
6 |
|
T88 |
1 |
|
T90 |
1 |
| others[3] |
171 |
1 |
|
T11 |
1 |
|
T37 |
7 |
|
T38 |
6 |
| false |
38 |
1 |
|
T37 |
1 |
|
T235 |
1 |
|
T405 |
1 |
| true |
6269 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T37 |
8 |
|
T148 |
1 |
|
T56 |
2 |
| others[1] |
237 |
1 |
|
T37 |
11 |
|
T56 |
2 |
|
T216 |
1 |
| others[2] |
244 |
1 |
|
T15 |
1 |
|
T37 |
7 |
|
T6 |
1 |
| others[3] |
416 |
1 |
|
T70 |
1 |
|
T37 |
20 |
|
T41 |
1 |
| false |
120 |
1 |
|
T37 |
3 |
|
T90 |
1 |
|
T241 |
1 |
| true |
5573 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1036 |
1 |
|
T3 |
11 |
|
T9 |
1 |
|
T18 |
8 |
| others[1] |
1029 |
1 |
|
T3 |
6 |
|
T18 |
10 |
|
T26 |
4 |
| others[2] |
1024 |
1 |
|
T3 |
12 |
|
T15 |
1 |
|
T18 |
10 |
| others[3] |
1781 |
1 |
|
T3 |
16 |
|
T16 |
1 |
|
T17 |
1 |
| false |
548 |
1 |
|
T3 |
6 |
|
T18 |
5 |
|
T26 |
4 |
| true |
1401 |
1 |
|
T18 |
45 |
|
T26 |
33 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
246 |
1 |
|
T37 |
8 |
|
T148 |
1 |
|
T44 |
1 |
| others[1] |
245 |
1 |
|
T11 |
1 |
|
T37 |
8 |
|
T313 |
1 |
| others[2] |
236 |
1 |
|
T37 |
13 |
|
T397 |
1 |
|
T228 |
1 |
| others[3] |
392 |
1 |
|
T17 |
1 |
|
T37 |
20 |
|
T41 |
1 |
| false |
125 |
1 |
|
T37 |
5 |
|
T401 |
1 |
|
T241 |
1 |
| true |
5575 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
213 |
1 |
|
T37 |
15 |
|
T210 |
1 |
|
T89 |
1 |
| others[1] |
228 |
1 |
|
T37 |
6 |
|
T90 |
1 |
|
T404 |
1 |
| others[2] |
225 |
1 |
|
T11 |
1 |
|
T37 |
10 |
|
T88 |
1 |
| others[3] |
401 |
1 |
|
T70 |
1 |
|
T37 |
21 |
|
T148 |
1 |
| false |
123 |
1 |
|
T37 |
7 |
|
T55 |
1 |
|
T63 |
1 |
| true |
5629 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1245 |
1 |
|
T3 |
10 |
|
T18 |
17 |
|
T26 |
8 |
| others[1] |
1186 |
1 |
|
T3 |
11 |
|
T17 |
1 |
|
T18 |
22 |
| others[2] |
1187 |
1 |
|
T3 |
5 |
|
T9 |
1 |
|
T18 |
14 |
| others[3] |
2123 |
1 |
|
T3 |
22 |
|
T15 |
1 |
|
T16 |
1 |
| false |
595 |
1 |
|
T3 |
3 |
|
T18 |
8 |
|
T26 |
4 |
| true |
483 |
1 |
|
T70 |
1 |
|
T11 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1275 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T18 |
15 |
| others[1] |
1235 |
1 |
|
T3 |
12 |
|
T15 |
1 |
|
T18 |
25 |
| others[2] |
1181 |
1 |
|
T3 |
9 |
|
T18 |
19 |
|
T26 |
8 |
| others[3] |
2018 |
1 |
|
T3 |
18 |
|
T18 |
32 |
|
T26 |
23 |
| false |
642 |
1 |
|
T3 |
6 |
|
T9 |
1 |
|
T18 |
9 |
| true |
468 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T37 |
6 |
|
T55 |
1 |
|
T90 |
1 |
| others[1] |
96 |
1 |
|
T37 |
5 |
|
T38 |
3 |
|
T86 |
7 |
| others[2] |
92 |
1 |
|
T11 |
1 |
|
T37 |
2 |
|
T90 |
1 |
| others[3] |
179 |
1 |
|
T15 |
1 |
|
T70 |
1 |
|
T37 |
6 |
| false |
56 |
1 |
|
T37 |
4 |
|
T148 |
1 |
|
T90 |
1 |
| true |
6292 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
262 |
1 |
|
T37 |
11 |
|
T41 |
1 |
|
T6 |
2 |
| others[1] |
248 |
1 |
|
T11 |
1 |
|
T37 |
12 |
|
T6 |
1 |
| others[2] |
253 |
1 |
|
T37 |
8 |
|
T40 |
1 |
|
T88 |
1 |
| others[3] |
365 |
1 |
|
T37 |
12 |
|
T76 |
1 |
|
T6 |
1 |
| false |
122 |
1 |
|
T17 |
1 |
|
T37 |
5 |
|
T313 |
1 |
| true |
5569 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1093 |
1 |
|
T3 |
9 |
|
T18 |
9 |
|
T26 |
6 |
| others[1] |
1070 |
1 |
|
T3 |
12 |
|
T18 |
8 |
|
T26 |
5 |
| others[2] |
1009 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T16 |
1 |
| others[3] |
1722 |
1 |
|
T3 |
14 |
|
T9 |
1 |
|
T18 |
19 |
| false |
550 |
1 |
|
T3 |
9 |
|
T17 |
1 |
|
T18 |
4 |
| true |
1375 |
1 |
|
T18 |
52 |
|
T26 |
30 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T11 |
1 |
|
T37 |
16 |
|
T63 |
1 |
| others[1] |
222 |
1 |
|
T15 |
1 |
|
T37 |
5 |
|
T88 |
1 |
| others[2] |
236 |
1 |
|
T37 |
9 |
|
T90 |
1 |
|
T60 |
1 |
| others[3] |
400 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T37 |
14 |
| false |
103 |
1 |
|
T37 |
7 |
|
T353 |
1 |
|
T205 |
1 |
| true |
5631 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
216 |
1 |
|
T37 |
13 |
|
T157 |
1 |
|
T403 |
1 |
| others[1] |
234 |
1 |
|
T37 |
13 |
|
T216 |
1 |
|
T8 |
2 |
| others[2] |
217 |
1 |
|
T17 |
1 |
|
T37 |
5 |
|
T148 |
1 |
| others[3] |
364 |
1 |
|
T70 |
1 |
|
T37 |
12 |
|
T76 |
1 |
| false |
129 |
1 |
|
T37 |
6 |
|
T55 |
1 |
|
T235 |
1 |
| true |
5659 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1244 |
1 |
|
T3 |
6 |
|
T18 |
22 |
|
T26 |
12 |
| others[1] |
1225 |
1 |
|
T3 |
9 |
|
T18 |
15 |
|
T26 |
9 |
| others[2] |
1183 |
1 |
|
T3 |
11 |
|
T16 |
1 |
|
T18 |
19 |
| others[3] |
2042 |
1 |
|
T3 |
22 |
|
T15 |
1 |
|
T9 |
1 |
| false |
646 |
1 |
|
T3 |
3 |
|
T18 |
10 |
|
T26 |
7 |
| true |
479 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1259 |
1 |
|
T3 |
6 |
|
T9 |
1 |
|
T18 |
19 |
| others[1] |
1244 |
1 |
|
T3 |
14 |
|
T18 |
22 |
|
T26 |
10 |
| others[2] |
1184 |
1 |
|
T3 |
13 |
|
T16 |
1 |
|
T18 |
17 |
| others[3] |
2010 |
1 |
|
T3 |
16 |
|
T15 |
1 |
|
T18 |
35 |
| false |
645 |
1 |
|
T3 |
2 |
|
T18 |
7 |
|
T26 |
4 |
| true |
477 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
126 |
1 |
|
T37 |
6 |
|
T44 |
1 |
|
T38 |
7 |
| others[1] |
97 |
1 |
|
T37 |
2 |
|
T235 |
1 |
|
T38 |
6 |
| others[2] |
102 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T86 |
3 |
| others[3] |
148 |
1 |
|
T37 |
4 |
|
T400 |
1 |
|
T235 |
1 |
| false |
54 |
1 |
|
T70 |
1 |
|
T37 |
2 |
|
T210 |
1 |
| true |
6292 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |