Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T4 |
1 |
|
T68 |
1 |
|
T282 |
1 |
| others[1] |
236 |
1 |
|
T4 |
1 |
|
T67 |
1 |
|
T56 |
1 |
| others[2] |
241 |
1 |
|
T4 |
1 |
|
T72 |
1 |
|
T159 |
1 |
| others[3] |
412 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T59 |
1 |
| false |
125 |
1 |
|
T4 |
1 |
|
T103 |
1 |
|
T240 |
1 |
| true |
5663 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T8 |
8 |
|
T25 |
1 |
|
T32 |
8 |
| others[1] |
1070 |
1 |
|
T4 |
1 |
|
T8 |
7 |
|
T12 |
1 |
| others[2] |
1027 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
1 |
| others[3] |
1792 |
1 |
|
T4 |
2 |
|
T8 |
17 |
|
T16 |
1 |
| false |
580 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
10 |
| true |
1414 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
267 |
1 |
|
T240 |
1 |
|
T414 |
1 |
|
T90 |
1 |
| others[1] |
215 |
1 |
|
T30 |
1 |
|
T132 |
1 |
|
T125 |
1 |
| others[2] |
204 |
1 |
|
T60 |
1 |
|
T90 |
1 |
|
T223 |
1 |
| others[3] |
415 |
1 |
|
T67 |
1 |
|
T132 |
1 |
|
T59 |
1 |
| false |
114 |
1 |
|
T28 |
6 |
|
T154 |
1 |
|
T410 |
1 |
| true |
5707 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T3 |
1 |
|
T59 |
1 |
|
T72 |
1 |
| others[1] |
221 |
1 |
|
T54 |
1 |
|
T159 |
1 |
|
T18 |
1 |
| others[2] |
240 |
1 |
|
T4 |
1 |
|
T104 |
1 |
|
T234 |
1 |
| others[3] |
371 |
1 |
|
T4 |
1 |
|
T67 |
1 |
|
T103 |
1 |
| false |
133 |
1 |
|
T125 |
1 |
|
T28 |
4 |
|
T156 |
1 |
| true |
5703 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
4 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1256 |
1 |
|
T2 |
1 |
|
T8 |
5 |
|
T48 |
1 |
| others[1] |
1227 |
1 |
|
T8 |
13 |
|
T120 |
1 |
|
T32 |
14 |
| others[2] |
1263 |
1 |
|
T1 |
1 |
|
T8 |
6 |
|
T32 |
21 |
| others[3] |
2042 |
1 |
|
T3 |
1 |
|
T8 |
18 |
|
T22 |
1 |
| false |
649 |
1 |
|
T8 |
7 |
|
T32 |
8 |
|
T33 |
4 |
| true |
485 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T8 |
14 |
|
T61 |
1 |
|
T32 |
17 |
| others[1] |
1247 |
1 |
|
T8 |
6 |
|
T32 |
16 |
|
T33 |
13 |
| others[2] |
1224 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
9 |
| others[3] |
2080 |
1 |
|
T8 |
15 |
|
T120 |
1 |
|
T32 |
40 |
| false |
657 |
1 |
|
T8 |
5 |
|
T32 |
7 |
|
T33 |
4 |
| true |
471 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
105 |
1 |
|
T90 |
1 |
|
T28 |
7 |
|
T158 |
1 |
| others[1] |
116 |
1 |
|
T56 |
1 |
|
T235 |
1 |
|
T28 |
2 |
| others[2] |
127 |
1 |
|
T67 |
1 |
|
T56 |
1 |
|
T28 |
3 |
| others[3] |
181 |
1 |
|
T16 |
1 |
|
T235 |
1 |
|
T28 |
13 |
| false |
57 |
1 |
|
T412 |
1 |
|
T78 |
1 |
|
T88 |
5 |
| true |
6336 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
238 |
1 |
|
T4 |
1 |
|
T31 |
1 |
|
T22 |
1 |
| others[1] |
258 |
1 |
|
T4 |
2 |
|
T22 |
1 |
|
T68 |
1 |
| others[2] |
221 |
1 |
|
T22 |
1 |
|
T132 |
1 |
|
T103 |
1 |
| others[3] |
423 |
1 |
|
T4 |
1 |
|
T22 |
2 |
|
T30 |
1 |
| false |
103 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T28 |
2 |
| true |
5679 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1073 |
1 |
|
T8 |
12 |
|
T22 |
2 |
|
T12 |
1 |
| others[1] |
1045 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
4 |
| others[2] |
1052 |
1 |
|
T8 |
5 |
|
T16 |
1 |
|
T31 |
1 |
| others[3] |
1790 |
1 |
|
T1 |
1 |
|
T4 |
2 |
|
T8 |
21 |
| false |
549 |
1 |
|
T4 |
1 |
|
T8 |
7 |
|
T22 |
1 |
| true |
1413 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
214 |
1 |
|
T25 |
1 |
|
T223 |
1 |
|
T28 |
8 |
| others[1] |
238 |
1 |
|
T104 |
1 |
|
T68 |
1 |
|
T125 |
1 |
| others[2] |
223 |
1 |
|
T31 |
1 |
|
T80 |
1 |
|
T414 |
1 |
| others[3] |
366 |
1 |
|
T16 |
1 |
|
T241 |
1 |
|
T43 |
1 |
| false |
126 |
1 |
|
T90 |
1 |
|
T28 |
5 |
|
T201 |
1 |
| true |
5755 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
201 |
1 |
|
T4 |
2 |
|
T104 |
1 |
|
T282 |
1 |
| others[1] |
239 |
1 |
|
T4 |
1 |
|
T68 |
1 |
|
T72 |
1 |
| others[2] |
238 |
1 |
|
T125 |
1 |
|
T241 |
1 |
|
T18 |
1 |
| others[3] |
352 |
1 |
|
T103 |
1 |
|
T235 |
2 |
|
T18 |
1 |
| false |
114 |
1 |
|
T3 |
1 |
|
T30 |
1 |
|
T81 |
1 |
| true |
5778 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1273 |
1 |
|
T8 |
10 |
|
T48 |
1 |
|
T32 |
19 |
| others[1] |
1228 |
1 |
|
T8 |
9 |
|
T32 |
19 |
|
T33 |
19 |
| others[2] |
1244 |
1 |
|
T1 |
1 |
|
T8 |
13 |
|
T32 |
23 |
| others[3] |
2031 |
1 |
|
T2 |
1 |
|
T8 |
10 |
|
T120 |
1 |
| false |
651 |
1 |
|
T3 |
1 |
|
T8 |
7 |
|
T32 |
8 |
| true |
495 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1210 |
1 |
|
T8 |
7 |
|
T32 |
22 |
|
T33 |
11 |
| others[1] |
1261 |
1 |
|
T8 |
14 |
|
T32 |
15 |
|
T33 |
10 |
| others[2] |
1265 |
1 |
|
T8 |
10 |
|
T22 |
1 |
|
T120 |
1 |
| others[3] |
2057 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
14 |
| false |
653 |
1 |
|
T8 |
4 |
|
T32 |
8 |
|
T33 |
10 |
| true |
476 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T56 |
1 |
|
T90 |
1 |
|
T28 |
2 |
| others[1] |
119 |
1 |
|
T235 |
1 |
|
T40 |
1 |
|
T28 |
3 |
| others[2] |
87 |
1 |
|
T28 |
5 |
|
T158 |
1 |
|
T410 |
1 |
| others[3] |
183 |
1 |
|
T125 |
1 |
|
T235 |
1 |
|
T28 |
11 |
| false |
61 |
1 |
|
T56 |
1 |
|
T28 |
1 |
|
T78 |
1 |
| true |
6356 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T43 |
1 |
|
T240 |
1 |
|
T235 |
1 |
| others[1] |
232 |
1 |
|
T4 |
1 |
|
T104 |
1 |
|
T241 |
1 |
| others[2] |
243 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T132 |
1 |
| others[3] |
380 |
1 |
|
T67 |
1 |
|
T37 |
1 |
|
T68 |
1 |
| false |
120 |
1 |
|
T132 |
1 |
|
T18 |
1 |
|
T367 |
1 |
| true |
5720 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1049 |
1 |
|
T3 |
1 |
|
T8 |
10 |
|
T22 |
1 |
| others[1] |
1046 |
1 |
|
T1 |
1 |
|
T8 |
7 |
|
T22 |
1 |
| others[2] |
1075 |
1 |
|
T4 |
1 |
|
T8 |
9 |
|
T22 |
1 |
| others[3] |
1761 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T8 |
21 |
| false |
550 |
1 |
|
T4 |
1 |
|
T8 |
2 |
|
T11 |
1 |
| true |
1441 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T22 |
2 |
|
T103 |
1 |
|
T104 |
1 |
| others[1] |
234 |
1 |
|
T22 |
1 |
|
T72 |
1 |
|
T235 |
1 |
| others[2] |
235 |
1 |
|
T31 |
1 |
|
T22 |
2 |
|
T67 |
1 |
| others[3] |
405 |
1 |
|
T22 |
1 |
|
T30 |
1 |
|
T132 |
1 |
| false |
132 |
1 |
|
T132 |
1 |
|
T234 |
1 |
|
T54 |
1 |
| true |
5665 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
230 |
1 |
|
T18 |
2 |
|
T90 |
1 |
|
T28 |
7 |
| others[1] |
227 |
1 |
|
T18 |
1 |
|
T211 |
1 |
|
T28 |
17 |
| others[2] |
226 |
1 |
|
T3 |
1 |
|
T67 |
1 |
|
T54 |
1 |
| others[3] |
367 |
1 |
|
T4 |
2 |
|
T30 |
1 |
|
T103 |
1 |
| false |
122 |
1 |
|
T4 |
2 |
|
T80 |
1 |
|
T28 |
7 |
| true |
5750 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1204 |
1 |
|
T8 |
9 |
|
T120 |
1 |
|
T32 |
20 |
| others[1] |
1269 |
1 |
|
T1 |
1 |
|
T8 |
7 |
|
T32 |
12 |
| others[2] |
1326 |
1 |
|
T2 |
1 |
|
T8 |
19 |
|
T32 |
18 |
| others[3] |
2038 |
1 |
|
T8 |
10 |
|
T31 |
1 |
|
T48 |
1 |
| false |
599 |
1 |
|
T8 |
4 |
|
T32 |
7 |
|
T33 |
6 |
| true |
486 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1304 |
1 |
|
T8 |
12 |
|
T120 |
1 |
|
T32 |
21 |
| others[1] |
1238 |
1 |
|
T8 |
8 |
|
T32 |
19 |
|
T33 |
12 |
| others[2] |
1256 |
1 |
|
T8 |
6 |
|
T32 |
21 |
|
T33 |
10 |
| others[3] |
2011 |
1 |
|
T2 |
1 |
|
T8 |
17 |
|
T22 |
1 |
| false |
637 |
1 |
|
T1 |
1 |
|
T8 |
6 |
|
T32 |
6 |
| true |
476 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
104 |
1 |
|
T104 |
1 |
|
T56 |
1 |
|
T261 |
1 |
| others[1] |
102 |
1 |
|
T125 |
1 |
|
T28 |
7 |
|
T413 |
1 |
| others[2] |
105 |
1 |
|
T56 |
1 |
|
T235 |
1 |
|
T28 |
2 |
| others[3] |
202 |
1 |
|
T235 |
1 |
|
T28 |
8 |
|
T412 |
1 |
| false |
47 |
1 |
|
T91 |
1 |
|
T79 |
3 |
|
T88 |
2 |
| true |
6362 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T132 |
1 |
| others[1] |
232 |
1 |
|
T22 |
3 |
|
T282 |
1 |
|
T43 |
1 |
| others[2] |
244 |
1 |
|
T4 |
1 |
|
T80 |
1 |
|
T18 |
1 |
| others[3] |
402 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T22 |
1 |
| false |
128 |
1 |
|
T3 |
1 |
|
T22 |
1 |
|
T104 |
1 |
| true |
5677 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1080 |
1 |
|
T2 |
1 |
|
T8 |
6 |
|
T22 |
2 |
| others[1] |
1077 |
1 |
|
T4 |
1 |
|
T8 |
9 |
|
T6 |
1 |
| others[2] |
1023 |
1 |
|
T1 |
1 |
|
T8 |
6 |
|
T6 |
1 |
| others[3] |
1744 |
1 |
|
T4 |
1 |
|
T8 |
19 |
|
T22 |
3 |
| false |
576 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
9 |
| true |
1422 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
227 |
1 |
|
T25 |
1 |
|
T67 |
1 |
|
T54 |
1 |
| others[1] |
250 |
1 |
|
T159 |
1 |
|
T90 |
1 |
|
T28 |
12 |
| others[2] |
218 |
1 |
|
T132 |
1 |
|
T234 |
1 |
|
T43 |
1 |
| others[3] |
421 |
1 |
|
T31 |
1 |
|
T132 |
1 |
|
T68 |
1 |
| false |
116 |
1 |
|
T37 |
1 |
|
T235 |
1 |
|
T40 |
1 |
| true |
5690 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
240 |
1 |
|
T4 |
2 |
|
T59 |
1 |
|
T90 |
1 |
| others[1] |
217 |
1 |
|
T30 |
1 |
|
T104 |
1 |
|
T159 |
1 |
| others[2] |
250 |
1 |
|
T4 |
1 |
|
T68 |
1 |
|
T54 |
1 |
| others[3] |
382 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T67 |
1 |
| false |
108 |
1 |
|
T90 |
1 |
|
T28 |
4 |
|
T285 |
1 |
| true |
5725 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T8 |
10 |
|
T32 |
17 |
|
T33 |
19 |
| others[1] |
1232 |
1 |
|
T8 |
5 |
|
T32 |
24 |
|
T33 |
7 |
| others[2] |
1246 |
1 |
|
T8 |
9 |
|
T12 |
1 |
|
T32 |
18 |
| others[3] |
2087 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
19 |
| false |
647 |
1 |
|
T8 |
6 |
|
T120 |
1 |
|
T32 |
16 |
| true |
495 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1207 |
1 |
|
T8 |
5 |
|
T32 |
21 |
|
T33 |
12 |
| others[1] |
1304 |
1 |
|
T2 |
1 |
|
T8 |
9 |
|
T32 |
20 |
| others[2] |
1224 |
1 |
|
T1 |
1 |
|
T4 |
2 |
|
T8 |
10 |
| others[3] |
2051 |
1 |
|
T8 |
20 |
|
T32 |
28 |
|
T33 |
21 |
| false |
669 |
1 |
|
T8 |
5 |
|
T120 |
1 |
|
T32 |
12 |
| true |
467 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |