Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1126 |
1 |
|
T3 |
12 |
|
T17 |
7 |
|
T18 |
1 |
| others[1] |
969 |
1 |
|
T3 |
4 |
|
T13 |
1 |
|
T17 |
10 |
| others[2] |
1092 |
1 |
|
T3 |
12 |
|
T15 |
1 |
|
T16 |
1 |
| others[3] |
1809 |
1 |
|
T3 |
17 |
|
T17 |
18 |
|
T29 |
7 |
| false |
525 |
1 |
|
T3 |
6 |
|
T14 |
1 |
|
T17 |
1 |
| true |
1376 |
1 |
|
T17 |
58 |
|
T29 |
39 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
207 |
1 |
|
T37 |
1 |
|
T51 |
1 |
|
T95 |
1 |
| others[1] |
247 |
1 |
|
T50 |
1 |
|
T28 |
9 |
|
T39 |
1 |
| others[2] |
222 |
1 |
|
T71 |
1 |
|
T206 |
1 |
|
T28 |
12 |
| others[3] |
383 |
1 |
|
T32 |
1 |
|
T33 |
1 |
|
T392 |
1 |
| false |
127 |
1 |
|
T56 |
1 |
|
T392 |
1 |
|
T28 |
7 |
| true |
5711 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
211 |
1 |
|
T81 |
1 |
|
T213 |
1 |
|
T28 |
7 |
| others[1] |
225 |
1 |
|
T5 |
1 |
|
T233 |
1 |
|
T28 |
15 |
| others[2] |
229 |
1 |
|
T28 |
10 |
|
T168 |
1 |
|
T7 |
2 |
| others[3] |
384 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
| false |
134 |
1 |
|
T15 |
1 |
|
T5 |
2 |
|
T81 |
1 |
| true |
5714 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1175 |
1 |
|
T3 |
9 |
|
T17 |
21 |
|
T29 |
11 |
| others[1] |
1242 |
1 |
|
T3 |
8 |
|
T17 |
30 |
|
T29 |
16 |
| others[2] |
1253 |
1 |
|
T3 |
6 |
|
T14 |
1 |
|
T17 |
17 |
| others[3] |
2102 |
1 |
|
T3 |
21 |
|
T13 |
1 |
|
T15 |
1 |
| false |
645 |
1 |
|
T3 |
7 |
|
T17 |
6 |
|
T29 |
4 |
| true |
480 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1212 |
1 |
|
T3 |
10 |
|
T13 |
1 |
|
T17 |
17 |
| others[1] |
1264 |
1 |
|
T3 |
14 |
|
T15 |
1 |
|
T17 |
25 |
| others[2] |
1204 |
1 |
|
T3 |
11 |
|
T14 |
1 |
|
T17 |
13 |
| others[3] |
2044 |
1 |
|
T3 |
11 |
|
T17 |
30 |
|
T29 |
20 |
| false |
698 |
1 |
|
T3 |
5 |
|
T17 |
15 |
|
T29 |
3 |
| true |
475 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
115 |
1 |
|
T28 |
1 |
|
T393 |
1 |
|
T31 |
9 |
| others[1] |
101 |
1 |
|
T32 |
1 |
|
T51 |
1 |
|
T206 |
2 |
| others[2] |
109 |
1 |
|
T28 |
6 |
|
T113 |
1 |
|
T31 |
8 |
| others[3] |
159 |
1 |
|
T15 |
1 |
|
T81 |
1 |
|
T28 |
7 |
| false |
56 |
1 |
|
T207 |
1 |
|
T28 |
2 |
|
T31 |
1 |
| true |
6357 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
241 |
1 |
|
T50 |
1 |
|
T51 |
1 |
|
T81 |
1 |
| others[1] |
254 |
1 |
|
T5 |
1 |
|
T56 |
1 |
|
T392 |
1 |
| others[2] |
243 |
1 |
|
T72 |
1 |
|
T81 |
1 |
|
T124 |
1 |
| others[3] |
386 |
1 |
|
T32 |
1 |
|
T33 |
1 |
|
T81 |
1 |
| false |
129 |
1 |
|
T34 |
1 |
|
T46 |
1 |
|
T81 |
1 |
| true |
5644 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1051 |
1 |
|
T3 |
5 |
|
T13 |
1 |
|
T14 |
1 |
| others[1] |
1041 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T17 |
8 |
| others[2] |
1064 |
1 |
|
T3 |
13 |
|
T17 |
9 |
|
T18 |
1 |
| others[3] |
1737 |
1 |
|
T3 |
14 |
|
T17 |
21 |
|
T29 |
12 |
| false |
571 |
1 |
|
T3 |
8 |
|
T17 |
9 |
|
T29 |
4 |
| true |
1433 |
1 |
|
T16 |
1 |
|
T17 |
44 |
|
T29 |
26 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
217 |
1 |
|
T63 |
1 |
|
T392 |
1 |
|
T205 |
1 |
| others[1] |
236 |
1 |
|
T18 |
1 |
|
T37 |
1 |
|
T62 |
1 |
| others[2] |
232 |
1 |
|
T72 |
1 |
|
T63 |
1 |
|
T95 |
1 |
| others[3] |
424 |
1 |
|
T15 |
1 |
|
T34 |
1 |
|
T51 |
1 |
| false |
103 |
1 |
|
T63 |
1 |
|
T28 |
6 |
|
T358 |
2 |
| true |
5685 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
232 |
1 |
|
T32 |
1 |
|
T5 |
1 |
|
T28 |
12 |
| others[1] |
213 |
1 |
|
T9 |
1 |
|
T72 |
1 |
|
T51 |
1 |
| others[2] |
226 |
1 |
|
T71 |
1 |
|
T157 |
1 |
|
T28 |
11 |
| others[3] |
409 |
1 |
|
T5 |
1 |
|
T56 |
1 |
|
T206 |
1 |
| false |
129 |
1 |
|
T5 |
1 |
|
T28 |
6 |
|
T246 |
1 |
| true |
5688 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1222 |
1 |
|
T3 |
13 |
|
T17 |
13 |
|
T29 |
11 |
| others[1] |
1268 |
1 |
|
T3 |
5 |
|
T17 |
18 |
|
T29 |
18 |
| others[2] |
1227 |
1 |
|
T3 |
12 |
|
T14 |
1 |
|
T17 |
18 |
| others[3] |
2058 |
1 |
|
T3 |
16 |
|
T13 |
1 |
|
T15 |
1 |
| false |
637 |
1 |
|
T3 |
5 |
|
T17 |
10 |
|
T29 |
4 |
| true |
485 |
1 |
|
T18 |
1 |
|
T32 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1248 |
1 |
|
T3 |
7 |
|
T17 |
22 |
|
T29 |
14 |
| others[1] |
1277 |
1 |
|
T3 |
8 |
|
T17 |
15 |
|
T29 |
17 |
| others[2] |
1236 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T17 |
22 |
| others[3] |
2011 |
1 |
|
T3 |
22 |
|
T14 |
1 |
|
T17 |
34 |
| false |
651 |
1 |
|
T3 |
6 |
|
T13 |
1 |
|
T17 |
7 |
| true |
474 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
90 |
1 |
|
T51 |
1 |
|
T28 |
7 |
|
T42 |
5 |
| others[1] |
90 |
1 |
|
T28 |
3 |
|
T31 |
2 |
|
T42 |
3 |
| others[2] |
118 |
1 |
|
T15 |
1 |
|
T124 |
1 |
|
T28 |
6 |
| others[3] |
179 |
1 |
|
T22 |
1 |
|
T72 |
1 |
|
T81 |
1 |
| false |
59 |
1 |
|
T28 |
2 |
|
T113 |
1 |
|
T31 |
3 |
| true |
6361 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
231 |
1 |
|
T16 |
1 |
|
T81 |
2 |
|
T206 |
1 |
| others[1] |
236 |
1 |
|
T35 |
1 |
|
T62 |
1 |
|
T5 |
1 |
| others[2] |
247 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T32 |
1 |
| others[3] |
402 |
1 |
|
T71 |
1 |
|
T33 |
1 |
|
T5 |
2 |
| false |
108 |
1 |
|
T72 |
1 |
|
T50 |
1 |
|
T5 |
1 |
| true |
5673 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1103 |
1 |
|
T3 |
9 |
|
T13 |
1 |
|
T17 |
7 |
| others[1] |
1056 |
1 |
|
T3 |
10 |
|
T17 |
10 |
|
T18 |
1 |
| others[2] |
985 |
1 |
|
T3 |
12 |
|
T17 |
13 |
|
T29 |
6 |
| others[3] |
1795 |
1 |
|
T3 |
14 |
|
T14 |
1 |
|
T17 |
15 |
| false |
555 |
1 |
|
T3 |
6 |
|
T15 |
1 |
|
T17 |
5 |
| true |
1403 |
1 |
|
T16 |
1 |
|
T17 |
50 |
|
T29 |
34 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
244 |
1 |
|
T22 |
1 |
|
T124 |
1 |
|
T28 |
9 |
| others[1] |
230 |
1 |
|
T71 |
1 |
|
T33 |
1 |
|
T62 |
1 |
| others[2] |
237 |
1 |
|
T37 |
1 |
|
T81 |
1 |
|
T56 |
1 |
| others[3] |
367 |
1 |
|
T34 |
1 |
|
T206 |
1 |
|
T28 |
17 |
| false |
130 |
1 |
|
T28 |
7 |
|
T31 |
8 |
|
T42 |
6 |
| true |
5689 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
212 |
1 |
|
T18 |
1 |
|
T9 |
1 |
|
T71 |
1 |
| others[1] |
226 |
1 |
|
T5 |
1 |
|
T28 |
11 |
|
T166 |
1 |
| others[2] |
223 |
1 |
|
T5 |
1 |
|
T81 |
1 |
|
T56 |
1 |
| others[3] |
384 |
1 |
|
T32 |
1 |
|
T62 |
1 |
|
T5 |
1 |
| false |
108 |
1 |
|
T5 |
1 |
|
T81 |
1 |
|
T206 |
1 |
| true |
5744 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1264 |
1 |
|
T3 |
6 |
|
T13 |
1 |
|
T14 |
1 |
| others[1] |
1201 |
1 |
|
T3 |
15 |
|
T17 |
22 |
|
T29 |
9 |
| others[2] |
1275 |
1 |
|
T3 |
11 |
|
T17 |
17 |
|
T29 |
9 |
| others[3] |
1978 |
1 |
|
T3 |
14 |
|
T15 |
1 |
|
T17 |
28 |
| false |
679 |
1 |
|
T3 |
5 |
|
T17 |
8 |
|
T29 |
10 |
| true |
500 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1275 |
1 |
|
T3 |
10 |
|
T17 |
30 |
|
T29 |
15 |
| others[1] |
1198 |
1 |
|
T3 |
14 |
|
T17 |
14 |
|
T29 |
14 |
| others[2] |
1252 |
1 |
|
T3 |
7 |
|
T17 |
14 |
|
T29 |
6 |
| others[3] |
2038 |
1 |
|
T3 |
15 |
|
T14 |
1 |
|
T15 |
1 |
| false |
654 |
1 |
|
T3 |
5 |
|
T13 |
1 |
|
T17 |
10 |
| true |
480 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
113 |
1 |
|
T15 |
1 |
|
T206 |
1 |
|
T213 |
1 |
| others[1] |
120 |
1 |
|
T157 |
1 |
|
T28 |
7 |
|
T31 |
5 |
| others[2] |
112 |
1 |
|
T206 |
1 |
|
T28 |
7 |
|
T31 |
3 |
| others[3] |
169 |
1 |
|
T56 |
1 |
|
T233 |
1 |
|
T28 |
2 |
| false |
47 |
1 |
|
T28 |
1 |
|
T31 |
2 |
|
T42 |
2 |
| true |
6336 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
265 |
1 |
|
T9 |
1 |
|
T71 |
1 |
|
T72 |
1 |
| others[1] |
222 |
1 |
|
T95 |
1 |
|
T392 |
1 |
|
T28 |
14 |
| others[2] |
253 |
1 |
|
T51 |
1 |
|
T81 |
1 |
|
T28 |
6 |
| others[3] |
406 |
1 |
|
T32 |
1 |
|
T81 |
2 |
|
T205 |
1 |
| false |
124 |
1 |
|
T392 |
1 |
|
T28 |
8 |
|
T391 |
1 |
| true |
5627 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1089 |
1 |
|
T3 |
10 |
|
T14 |
1 |
|
T17 |
8 |
| others[1] |
1075 |
1 |
|
T3 |
7 |
|
T13 |
1 |
|
T15 |
1 |
| others[2] |
990 |
1 |
|
T3 |
9 |
|
T17 |
11 |
|
T29 |
5 |
| others[3] |
1781 |
1 |
|
T3 |
20 |
|
T16 |
1 |
|
T17 |
19 |
| false |
542 |
1 |
|
T3 |
5 |
|
T17 |
4 |
|
T29 |
3 |
| true |
1420 |
1 |
|
T17 |
47 |
|
T18 |
1 |
|
T29 |
35 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
259 |
1 |
|
T71 |
1 |
|
T22 |
1 |
|
T63 |
2 |
| others[1] |
245 |
1 |
|
T72 |
1 |
|
T51 |
1 |
|
T63 |
1 |
| others[2] |
211 |
1 |
|
T18 |
1 |
|
T33 |
1 |
|
T28 |
9 |
| others[3] |
447 |
1 |
|
T15 |
1 |
|
T32 |
1 |
|
T50 |
1 |
| false |
105 |
1 |
|
T16 |
1 |
|
T28 |
7 |
|
T167 |
1 |
| true |
5630 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
245 |
1 |
|
T5 |
1 |
|
T81 |
1 |
|
T213 |
1 |
| others[1] |
225 |
1 |
|
T32 |
1 |
|
T5 |
2 |
|
T81 |
1 |
| others[2] |
230 |
1 |
|
T157 |
1 |
|
T28 |
12 |
|
T166 |
1 |
| others[3] |
373 |
1 |
|
T22 |
1 |
|
T5 |
1 |
|
T81 |
1 |
| false |
105 |
1 |
|
T62 |
1 |
|
T28 |
8 |
|
T7 |
1 |
| true |
5719 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1268 |
1 |
|
T3 |
11 |
|
T17 |
20 |
|
T29 |
9 |
| others[1] |
1219 |
1 |
|
T3 |
10 |
|
T13 |
1 |
|
T17 |
14 |
| others[2] |
1220 |
1 |
|
T3 |
12 |
|
T15 |
1 |
|
T17 |
20 |
| others[3] |
2075 |
1 |
|
T3 |
13 |
|
T17 |
35 |
|
T29 |
19 |
| false |
629 |
1 |
|
T3 |
5 |
|
T14 |
1 |
|
T17 |
11 |
| true |
486 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1257 |
1 |
|
T3 |
9 |
|
T13 |
1 |
|
T17 |
20 |
| others[1] |
1202 |
1 |
|
T3 |
8 |
|
T17 |
19 |
|
T29 |
12 |
| others[2] |
1199 |
1 |
|
T3 |
9 |
|
T17 |
22 |
|
T29 |
10 |
| others[3] |
2106 |
1 |
|
T3 |
20 |
|
T15 |
1 |
|
T17 |
31 |
| false |
654 |
1 |
|
T3 |
5 |
|
T14 |
1 |
|
T17 |
8 |
| true |
479 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
99 |
1 |
|
T15 |
1 |
|
T51 |
1 |
|
T28 |
3 |
| others[1] |
100 |
1 |
|
T28 |
3 |
|
T31 |
3 |
|
T306 |
1 |
| others[2] |
86 |
1 |
|
T22 |
1 |
|
T206 |
1 |
|
T28 |
3 |
| others[3] |
201 |
1 |
|
T206 |
1 |
|
T28 |
9 |
|
T393 |
1 |
| false |
44 |
1 |
|
T81 |
1 |
|
T205 |
1 |
|
T28 |
2 |
| true |
6367 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |