Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
101 |
1 |
|
T240 |
1 |
|
T56 |
1 |
|
T28 |
6 |
| others[1] |
111 |
1 |
|
T234 |
1 |
|
T56 |
1 |
|
T28 |
4 |
| others[2] |
103 |
1 |
|
T28 |
2 |
|
T410 |
1 |
|
T91 |
1 |
| others[3] |
168 |
1 |
|
T235 |
1 |
|
T28 |
3 |
|
T412 |
2 |
| false |
60 |
1 |
|
T241 |
1 |
|
T235 |
1 |
|
T28 |
1 |
| true |
6379 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
257 |
1 |
|
T4 |
1 |
|
T132 |
1 |
|
T72 |
1 |
| others[1] |
236 |
1 |
|
T3 |
1 |
|
T43 |
1 |
|
T133 |
1 |
| others[2] |
248 |
1 |
|
T4 |
1 |
|
T25 |
1 |
|
T37 |
1 |
| others[3] |
362 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T67 |
1 |
| false |
147 |
1 |
|
T4 |
1 |
|
T68 |
1 |
|
T56 |
1 |
| true |
5672 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1021 |
1 |
|
T1 |
1 |
|
T8 |
8 |
|
T22 |
2 |
| others[1] |
1074 |
1 |
|
T4 |
2 |
|
T8 |
11 |
|
T22 |
2 |
| others[2] |
1057 |
1 |
|
T2 |
1 |
|
T4 |
2 |
|
T8 |
8 |
| others[3] |
1791 |
1 |
|
T8 |
16 |
|
T11 |
1 |
|
T32 |
13 |
| false |
547 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T8 |
6 |
| true |
1432 |
1 |
|
T5 |
1 |
|
T16 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
239 |
1 |
|
T282 |
1 |
|
T133 |
1 |
|
T235 |
1 |
| others[1] |
221 |
1 |
|
T67 |
1 |
|
T261 |
1 |
|
T28 |
13 |
| others[2] |
225 |
1 |
|
T30 |
1 |
|
T240 |
1 |
|
T56 |
1 |
| others[3] |
377 |
1 |
|
T31 |
1 |
|
T159 |
1 |
|
T235 |
1 |
| false |
133 |
1 |
|
T234 |
1 |
|
T259 |
1 |
|
T28 |
3 |
| true |
5727 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T104 |
1 |
|
T68 |
1 |
|
T241 |
1 |
| others[1] |
203 |
1 |
|
T4 |
1 |
|
T67 |
1 |
|
T125 |
1 |
| others[2] |
227 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T159 |
1 |
| others[3] |
397 |
1 |
|
T37 |
1 |
|
T59 |
1 |
|
T54 |
1 |
| false |
105 |
1 |
|
T56 |
1 |
|
T28 |
4 |
|
T201 |
1 |
| true |
5784 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1228 |
1 |
|
T8 |
2 |
|
T32 |
28 |
|
T33 |
14 |
| others[1] |
1217 |
1 |
|
T2 |
1 |
|
T8 |
12 |
|
T31 |
1 |
| others[2] |
1220 |
1 |
|
T8 |
8 |
|
T120 |
1 |
|
T32 |
19 |
| others[3] |
2102 |
1 |
|
T1 |
1 |
|
T8 |
15 |
|
T48 |
1 |
| false |
661 |
1 |
|
T8 |
12 |
|
T12 |
1 |
|
T32 |
10 |
| true |
494 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1183 |
1 |
|
T8 |
10 |
|
T120 |
1 |
|
T32 |
20 |
| others[1] |
1294 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
8 |
| others[2] |
1226 |
1 |
|
T4 |
1 |
|
T8 |
11 |
|
T32 |
18 |
| others[3] |
2094 |
1 |
|
T8 |
17 |
|
T32 |
33 |
|
T33 |
21 |
| false |
655 |
1 |
|
T1 |
1 |
|
T8 |
3 |
|
T32 |
6 |
| true |
470 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T56 |
1 |
|
T28 |
3 |
|
T78 |
2 |
| others[1] |
119 |
1 |
|
T235 |
1 |
|
T28 |
3 |
|
T201 |
1 |
| others[2] |
93 |
1 |
|
T56 |
1 |
|
T28 |
2 |
|
T203 |
1 |
| others[3] |
163 |
1 |
|
T16 |
1 |
|
T103 |
1 |
|
T133 |
1 |
| false |
48 |
1 |
|
T235 |
1 |
|
T28 |
1 |
|
T417 |
1 |
| true |
6385 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
258 |
1 |
|
T31 |
1 |
|
T132 |
1 |
|
T54 |
1 |
| others[1] |
274 |
1 |
|
T16 |
1 |
|
T104 |
1 |
|
T59 |
1 |
| others[2] |
231 |
1 |
|
T103 |
1 |
|
T37 |
1 |
|
T18 |
1 |
| others[3] |
373 |
1 |
|
T4 |
1 |
|
T68 |
1 |
|
T159 |
1 |
| false |
120 |
1 |
|
T132 |
1 |
|
T234 |
1 |
|
T367 |
2 |
| true |
5666 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T8 |
12 |
|
T32 |
13 |
|
T33 |
9 |
| others[1] |
1038 |
1 |
|
T5 |
1 |
|
T8 |
4 |
|
T32 |
11 |
| others[2] |
1031 |
1 |
|
T4 |
3 |
|
T8 |
6 |
|
T61 |
1 |
| others[3] |
1778 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
| false |
548 |
1 |
|
T8 |
4 |
|
T6 |
1 |
|
T120 |
1 |
| true |
1432 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T68 |
1 |
|
T234 |
1 |
|
T259 |
1 |
| others[1] |
245 |
1 |
|
T30 |
1 |
|
T282 |
1 |
|
T240 |
1 |
| others[2] |
235 |
1 |
|
T25 |
1 |
|
T90 |
1 |
|
T261 |
1 |
| others[3] |
412 |
1 |
|
T3 |
1 |
|
T72 |
1 |
|
T241 |
1 |
| false |
115 |
1 |
|
T104 |
1 |
|
T235 |
1 |
|
T28 |
2 |
| true |
5686 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T104 |
1 |
|
T235 |
1 |
|
T18 |
1 |
| others[1] |
218 |
1 |
|
T4 |
1 |
|
T67 |
1 |
|
T125 |
1 |
| others[2] |
257 |
1 |
|
T133 |
1 |
|
T60 |
1 |
|
T28 |
9 |
| others[3] |
383 |
1 |
|
T4 |
1 |
|
T68 |
1 |
|
T241 |
1 |
| false |
116 |
1 |
|
T28 |
5 |
|
T419 |
1 |
|
T416 |
1 |
| true |
5737 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1217 |
1 |
|
T8 |
4 |
|
T32 |
18 |
|
T33 |
13 |
| others[1] |
1202 |
1 |
|
T8 |
5 |
|
T32 |
32 |
|
T33 |
15 |
| others[2] |
1272 |
1 |
|
T1 |
1 |
|
T8 |
15 |
|
T120 |
1 |
| others[3] |
2120 |
1 |
|
T2 |
1 |
|
T8 |
16 |
|
T32 |
26 |
| false |
619 |
1 |
|
T8 |
9 |
|
T32 |
9 |
|
T33 |
5 |
| true |
492 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1286 |
1 |
|
T1 |
1 |
|
T8 |
8 |
|
T32 |
18 |
| others[1] |
1258 |
1 |
|
T8 |
15 |
|
T32 |
22 |
|
T132 |
1 |
| others[2] |
1204 |
1 |
|
T2 |
1 |
|
T8 |
7 |
|
T32 |
21 |
| others[3] |
2057 |
1 |
|
T4 |
2 |
|
T8 |
12 |
|
T61 |
1 |
| false |
650 |
1 |
|
T8 |
7 |
|
T32 |
14 |
|
T33 |
2 |
| true |
467 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T56 |
1 |
|
T235 |
2 |
|
T28 |
3 |
| others[1] |
95 |
1 |
|
T90 |
1 |
|
T28 |
4 |
|
T418 |
1 |
| others[2] |
113 |
1 |
|
T56 |
1 |
|
T261 |
1 |
|
T28 |
5 |
| others[3] |
190 |
1 |
|
T28 |
7 |
|
T412 |
1 |
|
T410 |
2 |
| false |
40 |
1 |
|
T28 |
2 |
|
T412 |
1 |
|
T78 |
5 |
| true |
6375 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
245 |
1 |
|
T4 |
1 |
|
T132 |
2 |
|
T54 |
1 |
| others[1] |
236 |
1 |
|
T16 |
1 |
|
T31 |
1 |
|
T72 |
1 |
| others[2] |
252 |
1 |
|
T4 |
1 |
|
T68 |
1 |
|
T234 |
1 |
| others[3] |
422 |
1 |
|
T4 |
1 |
|
T25 |
1 |
|
T59 |
1 |
| false |
134 |
1 |
|
T4 |
2 |
|
T30 |
1 |
|
T67 |
1 |
| true |
5633 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1095 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
11 |
| others[1] |
1091 |
1 |
|
T2 |
1 |
|
T8 |
11 |
|
T22 |
2 |
| others[2] |
1122 |
1 |
|
T4 |
2 |
|
T8 |
10 |
|
T22 |
1 |
| others[3] |
1680 |
1 |
|
T1 |
1 |
|
T8 |
13 |
|
T16 |
1 |
| false |
528 |
1 |
|
T4 |
2 |
|
T8 |
4 |
|
T32 |
3 |
| true |
1406 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T6 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
242 |
1 |
|
T67 |
1 |
|
T68 |
1 |
|
T125 |
1 |
| others[1] |
201 |
1 |
|
T16 |
1 |
|
T159 |
1 |
|
T282 |
1 |
| others[2] |
228 |
1 |
|
T37 |
1 |
|
T133 |
1 |
|
T60 |
1 |
| others[3] |
424 |
1 |
|
T30 |
1 |
|
T367 |
4 |
|
T90 |
1 |
| false |
129 |
1 |
|
T240 |
1 |
|
T367 |
1 |
|
T81 |
1 |
| true |
5698 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T4 |
1 |
|
T104 |
1 |
|
T56 |
1 |
| others[1] |
251 |
1 |
|
T68 |
1 |
|
T241 |
1 |
|
T56 |
1 |
| others[2] |
241 |
1 |
|
T4 |
1 |
|
T54 |
1 |
|
T72 |
1 |
| others[3] |
376 |
1 |
|
T4 |
2 |
|
T18 |
1 |
|
T40 |
1 |
| false |
106 |
1 |
|
T103 |
1 |
|
T133 |
1 |
|
T28 |
5 |
| true |
5740 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1243 |
1 |
|
T2 |
1 |
|
T8 |
8 |
|
T22 |
1 |
| others[1] |
1233 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T8 |
14 |
| others[2] |
1260 |
1 |
|
T4 |
1 |
|
T8 |
5 |
|
T31 |
1 |
| others[3] |
2041 |
1 |
|
T8 |
17 |
|
T32 |
28 |
|
T33 |
22 |
| false |
662 |
1 |
|
T8 |
5 |
|
T32 |
9 |
|
T33 |
6 |
| true |
483 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1269 |
1 |
|
T8 |
5 |
|
T120 |
1 |
|
T32 |
20 |
| others[1] |
1241 |
1 |
|
T1 |
1 |
|
T8 |
8 |
|
T32 |
14 |
| others[2] |
1268 |
1 |
|
T2 |
1 |
|
T8 |
12 |
|
T32 |
19 |
| others[3] |
2068 |
1 |
|
T8 |
17 |
|
T32 |
38 |
|
T33 |
24 |
| false |
596 |
1 |
|
T8 |
7 |
|
T32 |
9 |
|
T33 |
2 |
| true |
480 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
109 |
1 |
|
T28 |
3 |
|
T201 |
1 |
|
T412 |
1 |
| others[1] |
121 |
1 |
|
T234 |
1 |
|
T235 |
2 |
|
T28 |
9 |
| others[2] |
105 |
1 |
|
T80 |
1 |
|
T28 |
3 |
|
T412 |
1 |
| others[3] |
181 |
1 |
|
T240 |
1 |
|
T56 |
2 |
|
T261 |
1 |
| false |
47 |
1 |
|
T104 |
1 |
|
T28 |
2 |
|
T78 |
3 |
| true |
6359 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T67 |
1 |
|
T103 |
1 |
|
T133 |
1 |
| others[1] |
236 |
1 |
|
T18 |
1 |
|
T28 |
14 |
|
T285 |
1 |
| others[2] |
247 |
1 |
|
T16 |
1 |
|
T104 |
1 |
|
T240 |
1 |
| others[3] |
389 |
1 |
|
T4 |
3 |
|
T54 |
1 |
|
T18 |
1 |
| false |
128 |
1 |
|
T37 |
1 |
|
T241 |
1 |
|
T40 |
1 |
| true |
5675 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1039 |
1 |
|
T5 |
1 |
|
T8 |
8 |
|
T6 |
1 |
| others[1] |
1071 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
12 |
| others[2] |
1096 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
8 |
| others[3] |
1806 |
1 |
|
T4 |
2 |
|
T8 |
17 |
|
T16 |
1 |
| false |
521 |
1 |
|
T8 |
4 |
|
T20 |
1 |
|
T32 |
3 |
| true |
1389 |
1 |
|
T4 |
3 |
|
T31 |
1 |
|
T25 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T22 |
1 |
|
T56 |
1 |
|
T28 |
12 |
| others[1] |
221 |
1 |
|
T22 |
3 |
|
T132 |
1 |
|
T282 |
1 |
| others[2] |
259 |
1 |
|
T67 |
1 |
|
T235 |
1 |
|
T81 |
1 |
| others[3] |
394 |
1 |
|
T25 |
1 |
|
T22 |
2 |
|
T132 |
1 |
| false |
122 |
1 |
|
T3 |
1 |
|
T54 |
1 |
|
T28 |
4 |
| true |
5682 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
206 |
1 |
|
T4 |
1 |
|
T104 |
1 |
|
T37 |
1 |
| others[1] |
226 |
1 |
|
T30 |
1 |
|
T103 |
1 |
|
T240 |
1 |
| others[2] |
222 |
1 |
|
T3 |
1 |
|
T241 |
1 |
|
T56 |
1 |
| others[3] |
385 |
1 |
|
T68 |
1 |
|
T72 |
1 |
|
T90 |
1 |
| false |
120 |
1 |
|
T235 |
1 |
|
T28 |
4 |
|
T158 |
1 |
| true |
5763 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1215 |
1 |
|
T8 |
7 |
|
T32 |
17 |
|
T33 |
13 |
| others[1] |
1249 |
1 |
|
T8 |
11 |
|
T32 |
23 |
|
T33 |
9 |
| others[2] |
1193 |
1 |
|
T8 |
8 |
|
T20 |
1 |
|
T32 |
24 |
| others[3] |
2085 |
1 |
|
T8 |
20 |
|
T120 |
1 |
|
T48 |
1 |
| false |
688 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
3 |
| true |
492 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |