Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_8.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info0_page_cfg_9.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info1_page_cfg.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
252 |
1 |
|
T37 |
10 |
|
T56 |
2 |
|
T90 |
1 |
| others[1] |
255 |
1 |
|
T11 |
1 |
|
T37 |
13 |
|
T41 |
1 |
| others[2] |
237 |
1 |
|
T15 |
1 |
|
T37 |
11 |
|
T40 |
1 |
| others[3] |
382 |
1 |
|
T70 |
1 |
|
T37 |
14 |
|
T148 |
1 |
| false |
125 |
1 |
|
T37 |
6 |
|
T313 |
1 |
|
T8 |
2 |
| true |
5568 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1022 |
1 |
|
T3 |
9 |
|
T16 |
1 |
|
T18 |
9 |
| others[1] |
1036 |
1 |
|
T3 |
11 |
|
T17 |
1 |
|
T18 |
11 |
| others[2] |
1009 |
1 |
|
T3 |
8 |
|
T18 |
9 |
|
T26 |
5 |
| others[3] |
1777 |
1 |
|
T3 |
18 |
|
T15 |
1 |
|
T9 |
1 |
| false |
554 |
1 |
|
T3 |
5 |
|
T18 |
3 |
|
T26 |
1 |
| true |
1421 |
1 |
|
T18 |
53 |
|
T26 |
33 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
215 |
1 |
|
T37 |
5 |
|
T67 |
1 |
|
T52 |
1 |
| others[1] |
208 |
1 |
|
T37 |
9 |
|
T76 |
1 |
|
T60 |
1 |
| others[2] |
229 |
1 |
|
T11 |
1 |
|
T37 |
9 |
|
T157 |
1 |
| others[3] |
430 |
1 |
|
T37 |
20 |
|
T90 |
1 |
|
T401 |
1 |
| false |
128 |
1 |
|
T37 |
7 |
|
T90 |
1 |
|
T399 |
1 |
| true |
5609 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
211 |
1 |
|
T37 |
9 |
|
T76 |
1 |
|
T44 |
1 |
| others[1] |
232 |
1 |
|
T37 |
10 |
|
T6 |
1 |
|
T60 |
1 |
| others[2] |
239 |
1 |
|
T37 |
11 |
|
T88 |
1 |
|
T104 |
1 |
| others[3] |
353 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T37 |
14 |
| false |
118 |
1 |
|
T37 |
5 |
|
T6 |
1 |
|
T124 |
1 |
| true |
5666 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1200 |
1 |
|
T3 |
10 |
|
T17 |
1 |
|
T18 |
22 |
| others[1] |
1249 |
1 |
|
T3 |
13 |
|
T15 |
1 |
|
T16 |
1 |
| others[2] |
1210 |
1 |
|
T3 |
9 |
|
T9 |
1 |
|
T18 |
18 |
| others[3] |
2045 |
1 |
|
T3 |
14 |
|
T18 |
33 |
|
T26 |
17 |
| false |
619 |
1 |
|
T3 |
5 |
|
T18 |
9 |
|
T26 |
6 |
| true |
496 |
1 |
|
T70 |
1 |
|
T76 |
1 |
|
T148 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1157 |
1 |
|
T3 |
6 |
|
T18 |
24 |
|
T26 |
7 |
| others[1] |
1216 |
1 |
|
T3 |
14 |
|
T15 |
1 |
|
T18 |
14 |
| others[2] |
1249 |
1 |
|
T3 |
11 |
|
T18 |
24 |
|
T26 |
13 |
| others[3] |
2063 |
1 |
|
T3 |
18 |
|
T18 |
35 |
|
T26 |
24 |
| false |
658 |
1 |
|
T3 |
2 |
|
T9 |
1 |
|
T16 |
1 |
| true |
476 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
87 |
1 |
|
T37 |
4 |
|
T235 |
2 |
|
T89 |
1 |
| others[1] |
111 |
1 |
|
T37 |
4 |
|
T89 |
1 |
|
T200 |
1 |
| others[2] |
105 |
1 |
|
T17 |
1 |
|
T37 |
3 |
|
T89 |
1 |
| others[3] |
170 |
1 |
|
T37 |
5 |
|
T88 |
1 |
|
T38 |
7 |
| false |
53 |
1 |
|
T15 |
1 |
|
T37 |
2 |
|
T90 |
1 |
| true |
6293 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
255 |
1 |
|
T11 |
1 |
|
T37 |
10 |
|
T56 |
2 |
| others[1] |
235 |
1 |
|
T70 |
1 |
|
T37 |
12 |
|
T6 |
1 |
| others[2] |
234 |
1 |
|
T37 |
9 |
|
T6 |
1 |
|
T63 |
1 |
| others[3] |
402 |
1 |
|
T15 |
1 |
|
T37 |
11 |
|
T41 |
1 |
| false |
124 |
1 |
|
T37 |
5 |
|
T88 |
1 |
|
T8 |
1 |
| true |
5569 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T3 |
7 |
|
T9 |
1 |
|
T18 |
13 |
| others[1] |
1046 |
1 |
|
T3 |
10 |
|
T16 |
1 |
|
T18 |
12 |
| others[2] |
1085 |
1 |
|
T3 |
8 |
|
T18 |
10 |
|
T26 |
10 |
| others[3] |
1687 |
1 |
|
T3 |
20 |
|
T15 |
1 |
|
T18 |
12 |
| false |
519 |
1 |
|
T3 |
6 |
|
T17 |
1 |
|
T18 |
3 |
| true |
1445 |
1 |
|
T18 |
50 |
|
T26 |
29 |
|
T148 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
229 |
1 |
|
T37 |
8 |
|
T88 |
1 |
|
T90 |
1 |
| others[1] |
242 |
1 |
|
T37 |
10 |
|
T67 |
1 |
|
T313 |
1 |
| others[2] |
238 |
1 |
|
T11 |
1 |
|
T37 |
11 |
|
T401 |
1 |
| others[3] |
387 |
1 |
|
T70 |
1 |
|
T37 |
15 |
|
T42 |
1 |
| false |
114 |
1 |
|
T15 |
1 |
|
T37 |
3 |
|
T235 |
1 |
| true |
5609 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T37 |
8 |
|
T90 |
2 |
|
T235 |
1 |
| others[1] |
237 |
1 |
|
T11 |
1 |
|
T37 |
10 |
|
T148 |
1 |
| others[2] |
227 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T37 |
10 |
| others[3] |
376 |
1 |
|
T37 |
15 |
|
T6 |
1 |
|
T104 |
1 |
| false |
112 |
1 |
|
T37 |
5 |
|
T6 |
1 |
|
T401 |
1 |
| true |
5636 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1280 |
1 |
|
T3 |
10 |
|
T18 |
24 |
|
T26 |
8 |
| others[1] |
1212 |
1 |
|
T3 |
12 |
|
T18 |
21 |
|
T26 |
10 |
| others[2] |
1234 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T18 |
11 |
| others[3] |
1991 |
1 |
|
T3 |
18 |
|
T9 |
1 |
|
T16 |
1 |
| false |
624 |
1 |
|
T3 |
3 |
|
T18 |
7 |
|
T26 |
8 |
| true |
478 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1254 |
1 |
|
T3 |
11 |
|
T18 |
19 |
|
T26 |
18 |
| others[1] |
1227 |
1 |
|
T3 |
10 |
|
T18 |
19 |
|
T26 |
10 |
| others[2] |
1257 |
1 |
|
T3 |
8 |
|
T9 |
1 |
|
T18 |
18 |
| others[3] |
1971 |
1 |
|
T3 |
15 |
|
T15 |
1 |
|
T16 |
1 |
| false |
641 |
1 |
|
T3 |
7 |
|
T18 |
12 |
|
T26 |
9 |
| true |
469 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
110 |
1 |
|
T37 |
4 |
|
T148 |
1 |
|
T235 |
1 |
| others[1] |
88 |
1 |
|
T37 |
2 |
|
T405 |
1 |
|
T38 |
2 |
| others[2] |
101 |
1 |
|
T37 |
6 |
|
T55 |
1 |
|
T235 |
1 |
| others[3] |
163 |
1 |
|
T15 |
1 |
|
T37 |
4 |
|
T44 |
1 |
| false |
48 |
1 |
|
T37 |
3 |
|
T86 |
4 |
|
T159 |
2 |
| true |
6309 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T70 |
1 |
|
T37 |
12 |
|
T56 |
1 |
| others[1] |
238 |
1 |
|
T15 |
1 |
|
T37 |
8 |
|
T148 |
1 |
| others[2] |
243 |
1 |
|
T37 |
7 |
|
T56 |
3 |
|
T309 |
1 |
| others[3] |
394 |
1 |
|
T17 |
1 |
|
T37 |
17 |
|
T76 |
1 |
| false |
138 |
1 |
|
T37 |
4 |
|
T6 |
1 |
|
T90 |
1 |
| true |
5550 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1009 |
1 |
|
T3 |
9 |
|
T18 |
9 |
|
T26 |
5 |
| others[1] |
1085 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T17 |
1 |
| others[2] |
1001 |
1 |
|
T3 |
12 |
|
T18 |
11 |
|
T26 |
6 |
| others[3] |
1736 |
1 |
|
T3 |
15 |
|
T16 |
1 |
|
T18 |
19 |
| false |
545 |
1 |
|
T3 |
7 |
|
T9 |
1 |
|
T18 |
4 |
| true |
1443 |
1 |
|
T18 |
43 |
|
T26 |
37 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
222 |
1 |
|
T37 |
6 |
|
T401 |
1 |
|
T52 |
1 |
| others[1] |
275 |
1 |
|
T37 |
16 |
|
T313 |
1 |
|
T157 |
1 |
| others[2] |
233 |
1 |
|
T37 |
11 |
|
T313 |
1 |
|
T89 |
1 |
| others[3] |
417 |
1 |
|
T37 |
16 |
|
T76 |
1 |
|
T44 |
1 |
| false |
118 |
1 |
|
T17 |
1 |
|
T37 |
4 |
|
T148 |
1 |
| true |
5554 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
208 |
1 |
|
T37 |
12 |
|
T6 |
1 |
|
T241 |
1 |
| others[1] |
227 |
1 |
|
T17 |
1 |
|
T37 |
10 |
|
T90 |
2 |
| others[2] |
239 |
1 |
|
T37 |
12 |
|
T76 |
1 |
|
T63 |
1 |
| others[3] |
348 |
1 |
|
T15 |
1 |
|
T37 |
11 |
|
T216 |
1 |
| false |
114 |
1 |
|
T37 |
6 |
|
T6 |
1 |
|
T44 |
1 |
| true |
5683 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1230 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T18 |
19 |
| others[1] |
1280 |
1 |
|
T3 |
13 |
|
T18 |
18 |
|
T26 |
14 |
| others[2] |
1198 |
1 |
|
T3 |
7 |
|
T9 |
1 |
|
T18 |
23 |
| others[3] |
2020 |
1 |
|
T3 |
18 |
|
T16 |
1 |
|
T18 |
32 |
| false |
605 |
1 |
|
T3 |
4 |
|
T18 |
8 |
|
T26 |
8 |
| true |
486 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1199 |
1 |
|
T3 |
8 |
|
T18 |
20 |
|
T26 |
9 |
| others[1] |
1262 |
1 |
|
T3 |
18 |
|
T16 |
1 |
|
T18 |
19 |
| others[2] |
1248 |
1 |
|
T3 |
10 |
|
T18 |
19 |
|
T26 |
16 |
| others[3] |
2031 |
1 |
|
T3 |
13 |
|
T9 |
1 |
|
T18 |
32 |
| false |
618 |
1 |
|
T3 |
2 |
|
T15 |
1 |
|
T18 |
10 |
| true |
461 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
116 |
1 |
|
T17 |
1 |
|
T37 |
5 |
|
T241 |
1 |
| others[1] |
112 |
1 |
|
T37 |
5 |
|
T90 |
1 |
|
T89 |
1 |
| others[2] |
99 |
1 |
|
T15 |
1 |
|
T11 |
1 |
|
T37 |
2 |
| others[3] |
201 |
1 |
|
T37 |
7 |
|
T88 |
1 |
|
T90 |
1 |
| false |
53 |
1 |
|
T37 |
1 |
|
T400 |
1 |
|
T235 |
1 |
| true |
6238 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
263 |
1 |
|
T37 |
14 |
|
T55 |
1 |
|
T6 |
2 |
| others[1] |
246 |
1 |
|
T37 |
6 |
|
T40 |
1 |
|
T88 |
1 |
| others[2] |
236 |
1 |
|
T37 |
10 |
|
T6 |
1 |
|
T56 |
1 |
| others[3] |
417 |
1 |
|
T37 |
18 |
|
T67 |
1 |
|
T44 |
1 |
| false |
120 |
1 |
|
T70 |
1 |
|
T37 |
6 |
|
T42 |
1 |
| true |
5537 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1037 |
1 |
|
T3 |
9 |
|
T18 |
11 |
|
T26 |
2 |
| others[1] |
1055 |
1 |
|
T3 |
8 |
|
T9 |
1 |
|
T18 |
10 |
| others[2] |
1080 |
1 |
|
T3 |
10 |
|
T16 |
1 |
|
T18 |
11 |
| others[3] |
1725 |
1 |
|
T3 |
19 |
|
T15 |
1 |
|
T17 |
1 |
| false |
550 |
1 |
|
T3 |
5 |
|
T18 |
6 |
|
T26 |
2 |
| true |
1372 |
1 |
|
T18 |
45 |
|
T26 |
31 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
254 |
1 |
|
T11 |
1 |
|
T37 |
11 |
|
T67 |
1 |
| others[1] |
222 |
1 |
|
T37 |
7 |
|
T90 |
1 |
|
T52 |
1 |
| others[2] |
238 |
1 |
|
T37 |
12 |
|
T397 |
1 |
|
T353 |
1 |
| others[3] |
387 |
1 |
|
T37 |
22 |
|
T76 |
1 |
|
T88 |
1 |
| false |
125 |
1 |
|
T37 |
2 |
|
T353 |
1 |
|
T312 |
1 |
| true |
5593 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
251 |
1 |
|
T11 |
1 |
|
T37 |
13 |
|
T6 |
1 |
| others[1] |
241 |
1 |
|
T37 |
13 |
|
T67 |
1 |
|
T44 |
1 |
| others[2] |
190 |
1 |
|
T37 |
9 |
|
T90 |
1 |
|
T157 |
1 |
| others[3] |
380 |
1 |
|
T15 |
1 |
|
T37 |
14 |
|
T76 |
1 |
| false |
125 |
1 |
|
T37 |
1 |
|
T6 |
1 |
|
T90 |
1 |
| true |
5632 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1248 |
1 |
|
T3 |
5 |
|
T18 |
23 |
|
T26 |
10 |
| others[1] |
1225 |
1 |
|
T3 |
14 |
|
T15 |
1 |
|
T18 |
14 |
| others[2] |
1202 |
1 |
|
T3 |
8 |
|
T18 |
26 |
|
T26 |
6 |
| others[3] |
1998 |
1 |
|
T3 |
21 |
|
T9 |
1 |
|
T18 |
30 |
| false |
668 |
1 |
|
T3 |
3 |
|
T16 |
1 |
|
T18 |
7 |
| true |
478 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1219 |
1 |
|
T3 |
13 |
|
T9 |
1 |
|
T18 |
16 |
| others[1] |
1248 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T18 |
15 |
| others[2] |
1208 |
1 |
|
T3 |
10 |
|
T18 |
22 |
|
T26 |
13 |
| others[3] |
2031 |
1 |
|
T3 |
14 |
|
T16 |
1 |
|
T18 |
36 |
| false |
647 |
1 |
|
T3 |
6 |
|
T18 |
11 |
|
T26 |
3 |
| true |
466 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |