Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1277 |
1 |
|
T8 |
10 |
|
T32 |
15 |
|
T33 |
13 |
| others[1] |
1212 |
1 |
|
T2 |
1 |
|
T8 |
14 |
|
T120 |
1 |
| others[2] |
1224 |
1 |
|
T1 |
1 |
|
T8 |
9 |
|
T32 |
23 |
| others[3] |
2057 |
1 |
|
T8 |
12 |
|
T32 |
25 |
|
T33 |
21 |
| false |
678 |
1 |
|
T8 |
4 |
|
T32 |
12 |
|
T33 |
3 |
| true |
474 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
117 |
1 |
|
T104 |
1 |
|
T68 |
1 |
|
T28 |
5 |
| others[1] |
108 |
1 |
|
T56 |
2 |
|
T90 |
1 |
|
T28 |
2 |
| others[2] |
111 |
1 |
|
T125 |
1 |
|
T235 |
1 |
|
T28 |
4 |
| others[3] |
174 |
1 |
|
T159 |
1 |
|
T235 |
1 |
|
T90 |
1 |
| false |
62 |
1 |
|
T28 |
4 |
|
T412 |
2 |
|
T410 |
1 |
| true |
6350 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T43 |
1 |
|
T60 |
1 |
|
T90 |
1 |
| others[1] |
245 |
1 |
|
T4 |
1 |
|
T72 |
1 |
|
T18 |
2 |
| others[2] |
259 |
1 |
|
T3 |
1 |
|
T104 |
1 |
|
T282 |
1 |
| others[3] |
408 |
1 |
|
T103 |
1 |
|
T68 |
1 |
|
T234 |
1 |
| false |
122 |
1 |
|
T67 |
1 |
|
T18 |
1 |
|
T28 |
10 |
| true |
5651 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1070 |
1 |
|
T3 |
1 |
|
T8 |
11 |
|
T22 |
1 |
| others[1] |
1097 |
1 |
|
T5 |
1 |
|
T8 |
16 |
|
T16 |
1 |
| others[2] |
1022 |
1 |
|
T4 |
2 |
|
T8 |
4 |
|
T22 |
3 |
| others[3] |
1747 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T8 |
16 |
| false |
542 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
2 |
| true |
1444 |
1 |
|
T4 |
2 |
|
T62 |
1 |
|
T61 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
237 |
1 |
|
T37 |
1 |
|
T240 |
1 |
|
T367 |
1 |
| others[1] |
250 |
1 |
|
T72 |
1 |
|
T367 |
3 |
|
T28 |
14 |
| others[2] |
244 |
1 |
|
T241 |
1 |
|
T90 |
1 |
|
T223 |
1 |
| others[3] |
372 |
1 |
|
T103 |
1 |
|
T68 |
1 |
|
T125 |
1 |
| false |
129 |
1 |
|
T3 |
1 |
|
T31 |
1 |
|
T367 |
1 |
| true |
5690 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T30 |
1 |
|
T37 |
1 |
|
T28 |
6 |
| others[1] |
258 |
1 |
|
T4 |
1 |
|
T104 |
1 |
|
T60 |
1 |
| others[2] |
207 |
1 |
|
T4 |
1 |
|
T282 |
1 |
|
T133 |
1 |
| others[3] |
374 |
1 |
|
T4 |
2 |
|
T159 |
1 |
|
T18 |
2 |
| false |
103 |
1 |
|
T28 |
10 |
|
T158 |
1 |
|
T202 |
1 |
| true |
5744 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1239 |
1 |
|
T3 |
1 |
|
T8 |
12 |
|
T32 |
31 |
| others[1] |
1217 |
1 |
|
T2 |
1 |
|
T8 |
8 |
|
T48 |
1 |
| others[2] |
1280 |
1 |
|
T1 |
1 |
|
T8 |
9 |
|
T120 |
1 |
| others[3] |
2069 |
1 |
|
T8 |
12 |
|
T32 |
25 |
|
T33 |
21 |
| false |
622 |
1 |
|
T8 |
8 |
|
T32 |
13 |
|
T33 |
3 |
| true |
495 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1189 |
1 |
|
T2 |
1 |
|
T8 |
9 |
|
T32 |
14 |
| others[1] |
1283 |
1 |
|
T1 |
1 |
|
T8 |
11 |
|
T20 |
1 |
| others[2] |
1239 |
1 |
|
T8 |
9 |
|
T120 |
1 |
|
T32 |
21 |
| others[3] |
2099 |
1 |
|
T8 |
14 |
|
T22 |
1 |
|
T32 |
42 |
| false |
642 |
1 |
|
T8 |
6 |
|
T12 |
1 |
|
T32 |
9 |
| true |
470 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T28 |
3 |
|
T207 |
1 |
|
T410 |
1 |
| others[1] |
103 |
1 |
|
T56 |
1 |
|
T235 |
2 |
|
T40 |
1 |
| others[2] |
94 |
1 |
|
T56 |
1 |
|
T28 |
5 |
|
T410 |
1 |
| others[3] |
181 |
1 |
|
T241 |
1 |
|
T28 |
9 |
|
T158 |
1 |
| false |
45 |
1 |
|
T78 |
3 |
|
T79 |
2 |
|
T88 |
1 |
| true |
6385 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
250 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T16 |
1 |
| others[1] |
226 |
1 |
|
T132 |
1 |
|
T18 |
1 |
|
T90 |
1 |
| others[2] |
269 |
1 |
|
T22 |
3 |
|
T235 |
1 |
|
T18 |
1 |
| others[3] |
385 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T132 |
1 |
| false |
123 |
1 |
|
T4 |
1 |
|
T31 |
1 |
|
T22 |
1 |
| true |
5669 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1094 |
1 |
|
T3 |
1 |
|
T8 |
11 |
|
T16 |
1 |
| others[1] |
1117 |
1 |
|
T8 |
8 |
|
T25 |
1 |
|
T22 |
2 |
| others[2] |
1009 |
1 |
|
T1 |
1 |
|
T8 |
9 |
|
T6 |
1 |
| others[3] |
1714 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T8 |
11 |
| false |
560 |
1 |
|
T2 |
1 |
|
T8 |
10 |
|
T32 |
5 |
| true |
1428 |
1 |
|
T4 |
4 |
|
T31 |
1 |
|
T62 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
236 |
1 |
|
T104 |
1 |
|
T234 |
1 |
|
T235 |
1 |
| others[1] |
232 |
1 |
|
T3 |
1 |
|
T125 |
1 |
|
T60 |
1 |
| others[2] |
220 |
1 |
|
T43 |
1 |
|
T133 |
1 |
|
T39 |
1 |
| others[3] |
372 |
1 |
|
T132 |
2 |
|
T68 |
1 |
|
T72 |
1 |
| false |
126 |
1 |
|
T59 |
1 |
|
T235 |
1 |
|
T28 |
7 |
| true |
5736 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
232 |
1 |
|
T4 |
1 |
|
T30 |
1 |
|
T37 |
1 |
| others[1] |
217 |
1 |
|
T4 |
1 |
|
T159 |
1 |
|
T235 |
2 |
| others[2] |
227 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T104 |
1 |
| others[3] |
377 |
1 |
|
T4 |
1 |
|
T125 |
1 |
|
T282 |
1 |
| false |
133 |
1 |
|
T103 |
1 |
|
T18 |
1 |
|
T261 |
1 |
| true |
5736 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1209 |
1 |
|
T1 |
1 |
|
T8 |
13 |
|
T32 |
14 |
| others[1] |
1211 |
1 |
|
T2 |
1 |
|
T8 |
7 |
|
T32 |
20 |
| others[2] |
1240 |
1 |
|
T8 |
9 |
|
T32 |
25 |
|
T33 |
17 |
| others[3] |
2154 |
1 |
|
T8 |
18 |
|
T48 |
1 |
|
T32 |
32 |
| false |
609 |
1 |
|
T8 |
2 |
|
T120 |
1 |
|
T48 |
1 |
| true |
499 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T197 |
1 |
|
T420 |
1 |
|
T421 |
1 |
| others[1] |
7 |
1 |
|
T198 |
1 |
|
T195 |
1 |
|
T422 |
1 |
| others[2] |
6 |
1 |
|
T175 |
1 |
|
T423 |
1 |
|
T424 |
1 |
| others[3] |
10 |
1 |
|
T199 |
1 |
|
T425 |
1 |
|
T426 |
1 |
| false |
7 |
1 |
|
T276 |
1 |
|
T427 |
1 |
|
T428 |
1 |
| true |
46 |
1 |
|
T84 |
1 |
|
T185 |
1 |
|
T94 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T429 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
3 |
1 |
|
T44 |
1 |
|
T430 |
1 |
|
T431 |
1 |
| others[2] |
3 |
1 |
|
T432 |
1 |
|
T433 |
1 |
|
T434 |
1 |
| others[3] |
3 |
1 |
|
T435 |
1 |
|
T403 |
1 |
|
T436 |
1 |
| false |
8 |
1 |
|
T179 |
1 |
|
T406 |
1 |
|
T437 |
1 |
| true |
28 |
1 |
|
T42 |
1 |
|
T346 |
1 |
|
T180 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10117 |
1 |
|
T8 |
13 |
|
T9 |
1 |
|
T10 |
1 |
| others[1] |
783 |
1 |
|
T2 |
1 |
|
T8 |
10 |
|
T52 |
10 |
| others[2] |
744 |
1 |
|
T8 |
5 |
|
T120 |
1 |
|
T52 |
13 |
| others[3] |
1353 |
1 |
|
T1 |
1 |
|
T8 |
15 |
|
T20 |
1 |
| false |
411 |
1 |
|
T8 |
6 |
|
T52 |
5 |
|
T107 |
3 |
| true |
576 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2323 |
1 |
|
T8 |
11 |
|
T120 |
1 |
|
T55 |
27 |
| others[1] |
2469 |
1 |
|
T8 |
11 |
|
T67 |
1 |
|
T55 |
21 |
| others[2] |
2291 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
6 |
| others[3] |
4033 |
1 |
|
T8 |
18 |
|
T10 |
1 |
|
T26 |
1 |
| false |
1242 |
1 |
|
T8 |
3 |
|
T55 |
8 |
|
T32 |
7 |
| true |
1626 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9539 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T67 |
1 |
| others[1] |
255 |
1 |
|
T4 |
1 |
|
T234 |
1 |
|
T107 |
2 |
| others[2] |
289 |
1 |
|
T2 |
1 |
|
T22 |
1 |
|
T120 |
1 |
| others[3] |
471 |
1 |
|
T4 |
3 |
|
T31 |
1 |
|
T22 |
3 |
| false |
130 |
1 |
|
T25 |
1 |
|
T22 |
2 |
|
T30 |
1 |
| true |
3300 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9775 |
1 |
|
T4 |
1 |
|
T8 |
8 |
|
T9 |
1 |
| others[1] |
478 |
1 |
|
T2 |
1 |
|
T8 |
3 |
|
T62 |
1 |
| others[2] |
514 |
1 |
|
T4 |
2 |
|
T8 |
3 |
|
T31 |
1 |
| others[3] |
787 |
1 |
|
T4 |
1 |
|
T8 |
8 |
|
T11 |
1 |
| false |
246 |
1 |
|
T1 |
1 |
|
T22 |
1 |
|
T52 |
3 |
| true |
2184 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9516 |
1 |
|
T16 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
246 |
1 |
|
T30 |
1 |
|
T60 |
1 |
|
T56 |
1 |
| others[2] |
258 |
1 |
|
T120 |
1 |
|
T104 |
1 |
|
T37 |
1 |
| others[3] |
452 |
1 |
|
T132 |
2 |
|
T43 |
1 |
|
T90 |
1 |
| false |
126 |
1 |
|
T72 |
1 |
|
T28 |
4 |
|
T154 |
1 |
| true |
3386 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9504 |
1 |
|
T3 |
1 |
|
T120 |
1 |
|
T55 |
108 |
| others[1] |
249 |
1 |
|
T4 |
1 |
|
T234 |
1 |
|
T125 |
1 |
| others[2] |
236 |
1 |
|
T103 |
1 |
|
T37 |
1 |
|
T18 |
2 |
| others[3] |
415 |
1 |
|
T4 |
1 |
|
T241 |
1 |
|
T133 |
1 |
| false |
130 |
1 |
|
T4 |
1 |
|
T235 |
1 |
|
T80 |
1 |
| true |
3450 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10047 |
1 |
|
T1 |
1 |
|
T8 |
11 |
|
T9 |
1 |
| others[1] |
778 |
1 |
|
T8 |
6 |
|
T61 |
1 |
|
T120 |
1 |
| others[2] |
796 |
1 |
|
T8 |
8 |
|
T48 |
1 |
|
T52 |
13 |
| others[3] |
1381 |
1 |
|
T8 |
15 |
|
T52 |
21 |
|
T107 |
5 |
| false |
435 |
1 |
|
T2 |
1 |
|
T8 |
9 |
|
T52 |
4 |
| true |
547 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10056 |
1 |
|
T2 |
1 |
|
T8 |
9 |
|
T10 |
1 |
| others[1] |
763 |
1 |
|
T8 |
6 |
|
T120 |
1 |
|
T52 |
11 |
| others[2] |
810 |
1 |
|
T1 |
1 |
|
T8 |
14 |
|
T52 |
12 |
| others[3] |
1364 |
1 |
|
T8 |
16 |
|
T132 |
1 |
|
T52 |
17 |
| false |
378 |
1 |
|
T8 |
4 |
|
T52 |
7 |
|
T159 |
1 |
| true |
576 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2350 |
1 |
|
T8 |
10 |
|
T26 |
1 |
|
T55 |
16 |
| others[1] |
2347 |
1 |
|
T2 |
1 |
|
T8 |
7 |
|
T10 |
1 |
| others[2] |
2372 |
1 |
|
T8 |
9 |
|
T55 |
26 |
|
T32 |
21 |
| others[3] |
4057 |
1 |
|
T1 |
1 |
|
T8 |
19 |
|
T55 |
35 |
| false |
1240 |
1 |
|
T8 |
4 |
|
T55 |
10 |
|
T32 |
6 |
| true |
1581 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9529 |
1 |
|
T30 |
1 |
|
T120 |
1 |
|
T55 |
108 |
| others[1] |
288 |
1 |
|
T4 |
2 |
|
T107 |
2 |
|
T235 |
1 |
| others[2] |
280 |
1 |
|
T31 |
1 |
|
T59 |
1 |
|
T107 |
3 |
| others[3] |
440 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T103 |
1 |
| false |
135 |
1 |
|
T4 |
1 |
|
T28 |
5 |
|
T201 |
1 |
| true |
3275 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9750 |
1 |
|
T1 |
1 |
|
T8 |
2 |
|
T10 |
1 |
| others[1] |
472 |
1 |
|
T8 |
10 |
|
T61 |
1 |
|
T67 |
1 |
| others[2] |
451 |
1 |
|
T4 |
2 |
|
T5 |
1 |
|
T8 |
3 |
| others[3] |
798 |
1 |
|
T4 |
1 |
|
T8 |
5 |
|
T6 |
1 |
| false |
244 |
1 |
|
T8 |
1 |
|
T30 |
1 |
|
T132 |
1 |
| true |
2232 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
3 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |