Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
91 |
1 |
|
T51 |
1 |
|
T206 |
1 |
|
T28 |
2 |
| others[1] |
107 |
1 |
|
T28 |
3 |
|
T31 |
5 |
|
T42 |
5 |
| others[2] |
113 |
1 |
|
T28 |
3 |
|
T393 |
1 |
|
T394 |
1 |
| others[3] |
162 |
1 |
|
T15 |
1 |
|
T33 |
1 |
|
T206 |
1 |
| false |
62 |
1 |
|
T32 |
1 |
|
T157 |
1 |
|
T28 |
4 |
| true |
6362 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
259 |
1 |
|
T9 |
1 |
|
T62 |
1 |
|
T207 |
1 |
| others[1] |
231 |
1 |
|
T50 |
1 |
|
T35 |
1 |
|
T5 |
1 |
| others[2] |
231 |
1 |
|
T32 |
1 |
|
T63 |
1 |
|
T81 |
2 |
| others[3] |
427 |
1 |
|
T72 |
1 |
|
T51 |
1 |
|
T63 |
4 |
| false |
125 |
1 |
|
T28 |
3 |
|
T358 |
3 |
|
T31 |
3 |
| true |
5624 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1049 |
1 |
|
T3 |
12 |
|
T17 |
11 |
|
T29 |
11 |
| others[1] |
1075 |
1 |
|
T3 |
7 |
|
T17 |
7 |
|
T29 |
1 |
| others[2] |
1062 |
1 |
|
T3 |
7 |
|
T14 |
1 |
|
T17 |
11 |
| others[3] |
1754 |
1 |
|
T3 |
19 |
|
T13 |
1 |
|
T17 |
18 |
| false |
539 |
1 |
|
T3 |
6 |
|
T15 |
1 |
|
T17 |
5 |
| true |
1418 |
1 |
|
T16 |
1 |
|
T17 |
48 |
|
T29 |
31 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
257 |
1 |
|
T16 |
1 |
|
T72 |
1 |
|
T62 |
1 |
| others[1] |
218 |
1 |
|
T37 |
1 |
|
T81 |
2 |
|
T392 |
1 |
| others[2] |
248 |
1 |
|
T18 |
1 |
|
T9 |
1 |
|
T33 |
1 |
| others[3] |
368 |
1 |
|
T50 |
1 |
|
T46 |
1 |
|
T28 |
16 |
| false |
132 |
1 |
|
T205 |
1 |
|
T28 |
8 |
|
T393 |
1 |
| true |
5674 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
229 |
1 |
|
T15 |
1 |
|
T56 |
1 |
|
T206 |
1 |
| others[1] |
236 |
1 |
|
T9 |
1 |
|
T5 |
1 |
|
T28 |
13 |
| others[2] |
259 |
1 |
|
T62 |
1 |
|
T5 |
2 |
|
T81 |
1 |
| others[3] |
361 |
1 |
|
T16 |
1 |
|
T71 |
1 |
|
T33 |
1 |
| false |
108 |
1 |
|
T213 |
1 |
|
T28 |
9 |
|
T168 |
1 |
| true |
5704 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1186 |
1 |
|
T3 |
12 |
|
T13 |
1 |
|
T17 |
16 |
| others[1] |
1269 |
1 |
|
T3 |
5 |
|
T17 |
22 |
|
T29 |
12 |
| others[2] |
1246 |
1 |
|
T3 |
10 |
|
T15 |
1 |
|
T17 |
23 |
| others[3] |
2053 |
1 |
|
T3 |
15 |
|
T14 |
1 |
|
T17 |
31 |
| false |
647 |
1 |
|
T3 |
9 |
|
T17 |
8 |
|
T29 |
6 |
| true |
496 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1214 |
1 |
|
T3 |
7 |
|
T17 |
24 |
|
T29 |
11 |
| others[1] |
1218 |
1 |
|
T3 |
8 |
|
T14 |
1 |
|
T17 |
17 |
| others[2] |
1258 |
1 |
|
T3 |
13 |
|
T17 |
19 |
|
T29 |
15 |
| others[3] |
2071 |
1 |
|
T3 |
19 |
|
T13 |
1 |
|
T17 |
28 |
| false |
655 |
1 |
|
T3 |
4 |
|
T15 |
1 |
|
T17 |
12 |
| true |
481 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
103 |
1 |
|
T15 |
1 |
|
T206 |
1 |
|
T28 |
3 |
| others[1] |
101 |
1 |
|
T32 |
1 |
|
T206 |
1 |
|
T28 |
1 |
| others[2] |
107 |
1 |
|
T28 |
2 |
|
T31 |
7 |
|
T42 |
7 |
| others[3] |
180 |
1 |
|
T28 |
4 |
|
T246 |
1 |
|
T31 |
3 |
| false |
68 |
1 |
|
T28 |
2 |
|
T31 |
5 |
|
T42 |
7 |
| true |
6338 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
239 |
1 |
|
T32 |
1 |
|
T34 |
1 |
|
T206 |
1 |
| others[1] |
231 |
1 |
|
T71 |
1 |
|
T5 |
2 |
|
T46 |
1 |
| others[2] |
247 |
1 |
|
T50 |
1 |
|
T62 |
1 |
|
T205 |
1 |
| others[3] |
406 |
1 |
|
T16 |
1 |
|
T33 |
1 |
|
T35 |
1 |
| false |
131 |
1 |
|
T72 |
1 |
|
T81 |
1 |
|
T28 |
3 |
| true |
5643 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1003 |
1 |
|
T3 |
9 |
|
T13 |
1 |
|
T17 |
4 |
| others[1] |
1061 |
1 |
|
T3 |
6 |
|
T17 |
8 |
|
T29 |
2 |
| others[2] |
1050 |
1 |
|
T3 |
14 |
|
T17 |
17 |
|
T29 |
5 |
| others[3] |
1731 |
1 |
|
T3 |
19 |
|
T15 |
1 |
|
T17 |
14 |
| false |
594 |
1 |
|
T3 |
3 |
|
T14 |
1 |
|
T17 |
8 |
| true |
1458 |
1 |
|
T16 |
1 |
|
T17 |
49 |
|
T29 |
25 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
236 |
1 |
|
T37 |
1 |
|
T124 |
1 |
|
T28 |
7 |
| others[1] |
235 |
1 |
|
T32 |
1 |
|
T71 |
1 |
|
T62 |
1 |
| others[2] |
231 |
1 |
|
T63 |
3 |
|
T81 |
1 |
|
T28 |
11 |
| others[3] |
409 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T50 |
1 |
| false |
136 |
1 |
|
T22 |
1 |
|
T33 |
1 |
|
T207 |
1 |
| true |
5650 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
234 |
1 |
|
T22 |
1 |
|
T5 |
2 |
|
T81 |
1 |
| others[1] |
216 |
1 |
|
T16 |
1 |
|
T9 |
1 |
|
T50 |
1 |
| others[2] |
215 |
1 |
|
T72 |
1 |
|
T62 |
1 |
|
T5 |
1 |
| others[3] |
392 |
1 |
|
T33 |
1 |
|
T51 |
1 |
|
T81 |
1 |
| false |
105 |
1 |
|
T71 |
1 |
|
T28 |
4 |
|
T211 |
1 |
| true |
5735 |
1 |
|
T3 |
51 |
|
T13 |
1 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1230 |
1 |
|
T3 |
14 |
|
T14 |
1 |
|
T15 |
1 |
| others[1] |
1276 |
1 |
|
T3 |
4 |
|
T17 |
25 |
|
T29 |
13 |
| others[2] |
1223 |
1 |
|
T3 |
11 |
|
T13 |
1 |
|
T17 |
24 |
| others[3] |
2010 |
1 |
|
T3 |
18 |
|
T17 |
29 |
|
T29 |
24 |
| false |
664 |
1 |
|
T3 |
4 |
|
T17 |
6 |
|
T29 |
6 |
| true |
494 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
3 |
1 |
|
T396 |
1 |
|
T397 |
1 |
|
T398 |
1 |
| others[1] |
3 |
1 |
|
T97 |
1 |
|
T399 |
1 |
|
T400 |
1 |
| others[2] |
6 |
1 |
|
T401 |
1 |
|
T402 |
1 |
|
T403 |
1 |
| others[3] |
14 |
1 |
|
T200 |
1 |
|
T201 |
1 |
|
T202 |
1 |
| false |
3 |
1 |
|
T143 |
1 |
|
T404 |
1 |
|
T405 |
1 |
| true |
46 |
1 |
|
T4 |
1 |
|
T132 |
1 |
|
T135 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1 |
1 |
|
T406 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
3 |
1 |
|
T407 |
1 |
|
T408 |
1 |
|
T409 |
1 |
| others[2] |
8 |
1 |
|
T176 |
1 |
|
T410 |
1 |
|
T411 |
1 |
| others[3] |
5 |
1 |
|
T41 |
1 |
|
T412 |
1 |
|
T413 |
1 |
| false |
7 |
1 |
|
T414 |
1 |
|
T415 |
1 |
|
T416 |
1 |
| true |
23 |
1 |
|
T40 |
1 |
|
T384 |
1 |
|
T417 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
1 |
1 |
|
T418 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
3 |
1 |
|
T419 |
1 |
|
T420 |
1 |
|
T421 |
1 |
| others[2] |
3 |
1 |
|
T422 |
1 |
|
T423 |
1 |
|
T424 |
1 |
| others[3] |
5 |
1 |
|
T40 |
1 |
|
T414 |
1 |
|
T425 |
1 |
| false |
9 |
1 |
|
T426 |
1 |
|
T427 |
1 |
|
T428 |
1 |
| true |
26 |
1 |
|
T41 |
1 |
|
T176 |
1 |
|
T407 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10376 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
10 |
| others[1] |
807 |
1 |
|
T3 |
10 |
|
T83 |
1 |
|
T55 |
8 |
| others[2] |
786 |
1 |
|
T3 |
15 |
|
T8 |
1 |
|
T14 |
1 |
| others[3] |
1315 |
1 |
|
T3 |
12 |
|
T15 |
1 |
|
T109 |
1 |
| false |
393 |
1 |
|
T3 |
4 |
|
T55 |
6 |
|
T216 |
1 |
| true |
589 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2336 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T17 |
13 |
| others[1] |
2470 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T17 |
23 |
| others[2] |
2457 |
1 |
|
T3 |
11 |
|
T17 |
21 |
|
T29 |
8 |
| others[3] |
4099 |
1 |
|
T3 |
20 |
|
T13 |
1 |
|
T14 |
1 |
| false |
1321 |
1 |
|
T3 |
3 |
|
T17 |
9 |
|
T29 |
6 |
| true |
1583 |
1 |
|
T1 |
1 |
|
T8 |
2 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9859 |
1 |
|
T16 |
1 |
|
T17 |
100 |
|
T29 |
62 |
| others[1] |
305 |
1 |
|
T72 |
1 |
|
T100 |
1 |
|
T206 |
1 |
| others[2] |
263 |
1 |
|
T62 |
1 |
|
T51 |
1 |
|
T5 |
1 |
| others[3] |
459 |
1 |
|
T8 |
2 |
|
T71 |
1 |
|
T5 |
2 |
| false |
143 |
1 |
|
T14 |
1 |
|
T63 |
1 |
|
T79 |
1 |
| true |
3237 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10098 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
4 |
| others[1] |
459 |
1 |
|
T3 |
4 |
|
T15 |
1 |
|
T65 |
1 |
| others[2] |
488 |
1 |
|
T3 |
7 |
|
T13 |
1 |
|
T5 |
1 |
| others[3] |
763 |
1 |
|
T3 |
9 |
|
T143 |
1 |
|
T51 |
1 |
| false |
230 |
1 |
|
T3 |
4 |
|
T46 |
1 |
|
T206 |
1 |
| true |
2228 |
1 |
|
T3 |
23 |
|
T8 |
2 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9835 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
269 |
1 |
|
T213 |
1 |
|
T28 |
7 |
|
T113 |
1 |
| others[2] |
284 |
1 |
|
T14 |
1 |
|
T15 |
1 |
|
T207 |
1 |
| others[3] |
432 |
1 |
|
T13 |
1 |
|
T9 |
1 |
|
T63 |
4 |
| false |
131 |
1 |
|
T34 |
1 |
|
T81 |
1 |
|
T206 |
2 |
| true |
3315 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9819 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
274 |
1 |
|
T50 |
1 |
|
T95 |
1 |
|
T157 |
1 |
| others[2] |
270 |
1 |
|
T13 |
1 |
|
T15 |
1 |
|
T62 |
1 |
| others[3] |
429 |
1 |
|
T81 |
1 |
|
T28 |
18 |
|
T167 |
1 |
| false |
119 |
1 |
|
T16 |
1 |
|
T81 |
1 |
|
T205 |
1 |
| true |
3355 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10409 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
7 |
| others[1] |
757 |
1 |
|
T3 |
14 |
|
T79 |
1 |
|
T38 |
1 |
| others[2] |
846 |
1 |
|
T3 |
10 |
|
T56 |
1 |
|
T55 |
8 |
| others[3] |
1307 |
1 |
|
T3 |
18 |
|
T8 |
1 |
|
T13 |
1 |
| false |
385 |
1 |
|
T3 |
2 |
|
T52 |
1 |
|
T55 |
7 |
| true |
562 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10351 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T13 |
1 |
| others[1] |
791 |
1 |
|
T3 |
10 |
|
T8 |
1 |
|
T84 |
1 |
| others[2] |
769 |
1 |
|
T3 |
8 |
|
T14 |
1 |
|
T65 |
1 |
| others[3] |
1306 |
1 |
|
T3 |
16 |
|
T8 |
1 |
|
T15 |
1 |
| false |
422 |
1 |
|
T3 |
8 |
|
T55 |
4 |
|
T28 |
13 |
| true |
596 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2440 |
1 |
|
T3 |
12 |
|
T14 |
1 |
|
T17 |
18 |
| others[1] |
2399 |
1 |
|
T3 |
7 |
|
T17 |
22 |
|
T29 |
10 |
| others[2] |
2431 |
1 |
|
T3 |
12 |
|
T13 |
1 |
|
T17 |
10 |
| others[3] |
4128 |
1 |
|
T2 |
1 |
|
T3 |
18 |
|
T15 |
1 |
| false |
1240 |
1 |
|
T3 |
2 |
|
T17 |
12 |
|
T29 |
9 |
| true |
1597 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9851 |
1 |
|
T8 |
1 |
|
T17 |
100 |
|
T29 |
62 |
| others[1] |
279 |
1 |
|
T5 |
1 |
|
T81 |
1 |
|
T392 |
1 |
| others[2] |
278 |
1 |
|
T81 |
1 |
|
T38 |
1 |
|
T100 |
2 |
| others[3] |
481 |
1 |
|
T8 |
1 |
|
T18 |
1 |
|
T9 |
1 |
| false |
140 |
1 |
|
T32 |
1 |
|
T5 |
1 |
|
T46 |
1 |
| true |
3206 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10069 |
1 |
|
T2 |
1 |
|
T3 |
3 |
|
T8 |
1 |
| others[1] |
488 |
1 |
|
T3 |
1 |
|
T8 |
1 |
|
T13 |
1 |
| others[2] |
488 |
1 |
|
T3 |
7 |
|
T9 |
1 |
|
T71 |
1 |
| others[3] |
738 |
1 |
|
T3 |
12 |
|
T15 |
1 |
|
T143 |
1 |
| false |
231 |
1 |
|
T3 |
1 |
|
T62 |
1 |
|
T55 |
3 |
| true |
2221 |
1 |
|
T3 |
27 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9842 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
265 |
1 |
|
T72 |
1 |
|
T63 |
1 |
|
T109 |
1 |
| others[2] |
288 |
1 |
|
T71 |
1 |
|
T63 |
1 |
|
T28 |
6 |
| others[3] |
431 |
1 |
|
T16 |
1 |
|
T34 |
1 |
|
T50 |
1 |
| false |
122 |
1 |
|
T32 |
1 |
|
T62 |
1 |
|
T63 |
1 |
| true |
3287 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |