Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.bank1_info2_page_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.dis.val
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.ecc_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.hw_info_cfg_override.scramble_dis
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_0.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
114 |
1 |
|
T37 |
6 |
|
T203 |
1 |
|
T38 |
3 |
| others[1] |
94 |
1 |
|
T37 |
3 |
|
T235 |
1 |
|
T46 |
1 |
| others[2] |
101 |
1 |
|
T37 |
3 |
|
T38 |
2 |
|
T86 |
3 |
| others[3] |
180 |
1 |
|
T15 |
1 |
|
T37 |
8 |
|
T38 |
10 |
| false |
53 |
1 |
|
T37 |
2 |
|
T235 |
1 |
|
T38 |
2 |
| true |
6277 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
247 |
1 |
|
T37 |
6 |
|
T55 |
1 |
|
T104 |
1 |
| others[1] |
244 |
1 |
|
T37 |
8 |
|
T148 |
1 |
|
T40 |
1 |
| others[2] |
257 |
1 |
|
T37 |
8 |
|
T76 |
1 |
|
T67 |
1 |
| others[3] |
392 |
1 |
|
T17 |
1 |
|
T11 |
1 |
|
T37 |
16 |
| false |
124 |
1 |
|
T37 |
7 |
|
T309 |
1 |
|
T312 |
1 |
| true |
5555 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1016 |
1 |
|
T3 |
9 |
|
T9 |
1 |
|
T18 |
9 |
| others[1] |
1011 |
1 |
|
T3 |
10 |
|
T18 |
8 |
|
T26 |
7 |
| others[2] |
1083 |
1 |
|
T3 |
15 |
|
T18 |
14 |
|
T26 |
4 |
| others[3] |
1741 |
1 |
|
T3 |
13 |
|
T15 |
1 |
|
T16 |
1 |
| false |
571 |
1 |
|
T3 |
4 |
|
T18 |
3 |
|
T26 |
5 |
| true |
1397 |
1 |
|
T17 |
1 |
|
T18 |
51 |
|
T26 |
31 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
253 |
1 |
|
T37 |
14 |
|
T63 |
1 |
|
T228 |
1 |
| others[1] |
253 |
1 |
|
T37 |
6 |
|
T42 |
1 |
|
T313 |
1 |
| others[2] |
228 |
1 |
|
T70 |
1 |
|
T37 |
10 |
|
T44 |
1 |
| others[3] |
408 |
1 |
|
T15 |
1 |
|
T11 |
1 |
|
T37 |
15 |
| false |
113 |
1 |
|
T37 |
5 |
|
T202 |
1 |
|
T38 |
6 |
| true |
5564 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
256 |
1 |
|
T37 |
13 |
|
T55 |
1 |
|
T157 |
1 |
| others[1] |
199 |
1 |
|
T37 |
10 |
|
T90 |
1 |
|
T8 |
2 |
| others[2] |
228 |
1 |
|
T11 |
1 |
|
T37 |
10 |
|
T67 |
1 |
| others[3] |
380 |
1 |
|
T70 |
1 |
|
T37 |
16 |
|
T6 |
2 |
| false |
115 |
1 |
|
T37 |
5 |
|
T400 |
1 |
|
T89 |
1 |
| true |
5641 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1171 |
1 |
|
T3 |
11 |
|
T18 |
19 |
|
T26 |
19 |
| others[1] |
1201 |
1 |
|
T3 |
11 |
|
T18 |
14 |
|
T26 |
6 |
| others[2] |
1253 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T17 |
1 |
| others[3] |
2094 |
1 |
|
T3 |
17 |
|
T9 |
1 |
|
T16 |
1 |
| false |
623 |
1 |
|
T3 |
3 |
|
T18 |
9 |
|
T26 |
6 |
| true |
477 |
1 |
|
T70 |
1 |
|
T11 |
1 |
|
T76 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1191 |
1 |
|
T3 |
10 |
|
T18 |
27 |
|
T26 |
12 |
| others[1] |
1243 |
1 |
|
T3 |
6 |
|
T18 |
13 |
|
T26 |
11 |
| others[2] |
1211 |
1 |
|
T3 |
12 |
|
T18 |
20 |
|
T26 |
15 |
| others[3] |
2052 |
1 |
|
T3 |
16 |
|
T15 |
1 |
|
T16 |
1 |
| false |
659 |
1 |
|
T3 |
7 |
|
T9 |
1 |
|
T18 |
12 |
| true |
463 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
92 |
1 |
|
T37 |
2 |
|
T400 |
1 |
|
T210 |
1 |
| others[1] |
104 |
1 |
|
T37 |
5 |
|
T235 |
1 |
|
T399 |
1 |
| others[2] |
126 |
1 |
|
T15 |
1 |
|
T37 |
4 |
|
T235 |
1 |
| others[3] |
179 |
1 |
|
T70 |
1 |
|
T37 |
10 |
|
T90 |
1 |
| false |
45 |
1 |
|
T38 |
2 |
|
T86 |
3 |
|
T159 |
2 |
| true |
6273 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
244 |
1 |
|
T15 |
1 |
|
T11 |
1 |
|
T37 |
7 |
| others[1] |
265 |
1 |
|
T37 |
12 |
|
T41 |
1 |
|
T88 |
1 |
| others[2] |
247 |
1 |
|
T37 |
14 |
|
T6 |
1 |
|
T313 |
1 |
| others[3] |
365 |
1 |
|
T70 |
1 |
|
T37 |
14 |
|
T76 |
1 |
| false |
128 |
1 |
|
T37 |
5 |
|
T67 |
1 |
|
T42 |
1 |
| true |
5570 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1051 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T18 |
7 |
| others[1] |
1041 |
1 |
|
T3 |
14 |
|
T17 |
1 |
|
T18 |
11 |
| others[2] |
1020 |
1 |
|
T3 |
7 |
|
T18 |
10 |
|
T26 |
9 |
| others[3] |
1748 |
1 |
|
T3 |
17 |
|
T9 |
1 |
|
T18 |
13 |
| false |
557 |
1 |
|
T3 |
5 |
|
T16 |
1 |
|
T18 |
4 |
| true |
1402 |
1 |
|
T18 |
55 |
|
T26 |
28 |
|
T41 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
228 |
1 |
|
T37 |
7 |
|
T313 |
1 |
|
T403 |
1 |
| others[1] |
248 |
1 |
|
T37 |
10 |
|
T148 |
1 |
|
T90 |
1 |
| others[2] |
248 |
1 |
|
T37 |
6 |
|
T63 |
1 |
|
T313 |
1 |
| others[3] |
382 |
1 |
|
T70 |
1 |
|
T37 |
16 |
|
T67 |
1 |
| false |
115 |
1 |
|
T37 |
5 |
|
T42 |
1 |
|
T405 |
1 |
| true |
5598 |
1 |
|
T3 |
51 |
|
T15 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
231 |
1 |
|
T15 |
1 |
|
T37 |
11 |
|
T6 |
1 |
| others[1] |
188 |
1 |
|
T37 |
6 |
|
T63 |
1 |
|
T8 |
1 |
| others[2] |
241 |
1 |
|
T17 |
1 |
|
T37 |
9 |
|
T6 |
2 |
| others[3] |
402 |
1 |
|
T37 |
13 |
|
T76 |
1 |
|
T88 |
1 |
| false |
98 |
1 |
|
T37 |
8 |
|
T215 |
1 |
|
T203 |
1 |
| true |
5659 |
1 |
|
T3 |
51 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1200 |
1 |
|
T3 |
15 |
|
T16 |
1 |
|
T18 |
21 |
| others[1] |
1273 |
1 |
|
T3 |
8 |
|
T18 |
18 |
|
T26 |
14 |
| others[2] |
1213 |
1 |
|
T3 |
9 |
|
T9 |
1 |
|
T18 |
22 |
| others[3] |
2028 |
1 |
|
T3 |
14 |
|
T15 |
1 |
|
T18 |
24 |
| false |
611 |
1 |
|
T3 |
5 |
|
T18 |
15 |
|
T26 |
6 |
| true |
494 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
11 |
1 |
|
T407 |
1 |
|
T184 |
1 |
|
T408 |
1 |
| others[1] |
7 |
1 |
|
T196 |
1 |
|
T107 |
1 |
|
T409 |
1 |
| others[2] |
5 |
1 |
|
T410 |
1 |
|
T411 |
1 |
|
T185 |
1 |
| others[3] |
7 |
1 |
|
T412 |
1 |
|
T413 |
1 |
|
T414 |
1 |
| false |
3 |
1 |
|
T415 |
1 |
|
T416 |
1 |
|
T417 |
1 |
| true |
50 |
1 |
|
T4 |
1 |
|
T5 |
1 |
|
T33 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
6 |
1 |
|
T418 |
1 |
|
T419 |
1 |
|
T420 |
1 |
| others[1] |
1 |
1 |
|
T421 |
1 |
|
- |
- |
|
- |
- |
| others[2] |
1 |
1 |
|
T422 |
1 |
|
- |
- |
|
- |
- |
| others[3] |
1 |
1 |
|
T423 |
1 |
|
- |
- |
|
- |
- |
| false |
13 |
1 |
|
T47 |
1 |
|
T48 |
1 |
|
T396 |
1 |
| true |
22 |
1 |
|
T174 |
1 |
|
T424 |
1 |
|
T425 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
1 |
1 |
|
T426 |
1 |
|
- |
- |
|
- |
- |
| others[1] |
4 |
1 |
|
T48 |
1 |
|
T427 |
1 |
|
T419 |
1 |
| others[2] |
3 |
1 |
|
T422 |
1 |
|
T428 |
1 |
|
T429 |
1 |
| others[3] |
3 |
1 |
|
T430 |
1 |
|
T431 |
1 |
|
T432 |
1 |
| false |
11 |
1 |
|
T174 |
1 |
|
T423 |
1 |
|
T420 |
1 |
| true |
22 |
1 |
|
T47 |
1 |
|
T396 |
1 |
|
T424 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10731 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
11 |
| others[1] |
786 |
1 |
|
T3 |
15 |
|
T10 |
8 |
|
T37 |
26 |
| others[2] |
797 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T10 |
4 |
| others[3] |
1276 |
1 |
|
T3 |
9 |
|
T16 |
1 |
|
T10 |
5 |
| false |
378 |
1 |
|
T3 |
5 |
|
T9 |
1 |
|
T10 |
2 |
| true |
568 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2473 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T18 |
17 |
| others[1] |
2506 |
1 |
|
T3 |
10 |
|
T18 |
26 |
|
T26 |
9 |
| others[2] |
2489 |
1 |
|
T3 |
10 |
|
T9 |
1 |
|
T18 |
17 |
| others[3] |
4176 |
1 |
|
T2 |
1 |
|
T3 |
15 |
|
T16 |
1 |
| false |
1285 |
1 |
|
T3 |
5 |
|
T17 |
1 |
|
T18 |
8 |
| true |
1607 |
1 |
|
T1 |
1 |
|
T10 |
20 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10200 |
1 |
|
T10 |
1 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
269 |
1 |
|
T37 |
16 |
|
T6 |
1 |
|
T90 |
1 |
| others[2] |
269 |
1 |
|
T17 |
1 |
|
T37 |
4 |
|
T55 |
1 |
| others[3] |
478 |
1 |
|
T15 |
1 |
|
T10 |
4 |
|
T37 |
23 |
| false |
133 |
1 |
|
T10 |
1 |
|
T11 |
1 |
|
T37 |
2 |
| true |
3187 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10438 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
4 |
| others[1] |
421 |
1 |
|
T3 |
5 |
|
T15 |
1 |
|
T10 |
6 |
| others[2] |
449 |
1 |
|
T3 |
6 |
|
T9 |
1 |
|
T37 |
5 |
| others[3] |
786 |
1 |
|
T3 |
8 |
|
T10 |
7 |
|
T20 |
1 |
| false |
216 |
1 |
|
T10 |
1 |
|
T37 |
2 |
|
T58 |
4 |
| true |
2226 |
1 |
|
T3 |
28 |
|
T16 |
1 |
|
T10 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10197 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
7 |
| others[1] |
269 |
1 |
|
T37 |
17 |
|
T56 |
1 |
|
T120 |
1 |
| others[2] |
262 |
1 |
|
T37 |
5 |
|
T88 |
1 |
|
T45 |
1 |
| others[3] |
417 |
1 |
|
T37 |
19 |
|
T63 |
1 |
|
T56 |
3 |
| false |
140 |
1 |
|
T37 |
9 |
|
T312 |
1 |
|
T38 |
5 |
| true |
3251 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10189 |
1 |
|
T15 |
1 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
243 |
1 |
|
T37 |
2 |
|
T88 |
1 |
|
T90 |
1 |
| others[2] |
250 |
1 |
|
T9 |
1 |
|
T37 |
12 |
|
T6 |
1 |
| others[3] |
435 |
1 |
|
T16 |
1 |
|
T11 |
1 |
|
T37 |
17 |
| false |
139 |
1 |
|
T37 |
4 |
|
T89 |
1 |
|
T433 |
1 |
| true |
3280 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
51 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10728 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
6 |
| others[1] |
771 |
1 |
|
T3 |
7 |
|
T10 |
1 |
|
T37 |
21 |
| others[2] |
793 |
1 |
|
T3 |
11 |
|
T9 |
1 |
|
T10 |
2 |
| others[3] |
1267 |
1 |
|
T3 |
17 |
|
T16 |
1 |
|
T10 |
7 |
| false |
400 |
1 |
|
T3 |
10 |
|
T10 |
1 |
|
T37 |
8 |
| true |
577 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10713 |
1 |
|
T2 |
1 |
|
T3 |
16 |
|
T9 |
1 |
| others[1] |
836 |
1 |
|
T3 |
6 |
|
T10 |
7 |
|
T37 |
20 |
| others[2] |
739 |
1 |
|
T3 |
7 |
|
T10 |
2 |
|
T37 |
20 |
| others[3] |
1278 |
1 |
|
T3 |
17 |
|
T15 |
1 |
|
T10 |
5 |
| false |
373 |
1 |
|
T3 |
5 |
|
T10 |
3 |
|
T37 |
11 |
| true |
575 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2454 |
1 |
|
T3 |
12 |
|
T16 |
1 |
|
T18 |
22 |
| others[1] |
2477 |
1 |
|
T3 |
6 |
|
T18 |
24 |
|
T26 |
13 |
| others[2] |
2517 |
1 |
|
T3 |
11 |
|
T9 |
1 |
|
T18 |
22 |
| others[3] |
4138 |
1 |
|
T2 |
1 |
|
T3 |
19 |
|
T15 |
1 |
| false |
1305 |
1 |
|
T3 |
3 |
|
T18 |
10 |
|
T26 |
3 |
| true |
1623 |
1 |
|
T10 |
20 |
|
T17 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10175 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
12 |
| others[1] |
256 |
1 |
|
T10 |
1 |
|
T37 |
9 |
|
T44 |
1 |
| others[2] |
287 |
1 |
|
T15 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| others[3] |
492 |
1 |
|
T10 |
4 |
|
T11 |
1 |
|
T37 |
16 |
| false |
145 |
1 |
|
T10 |
2 |
|
T37 |
4 |
|
T148 |
1 |
| true |
3159 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T10 |
10 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10421 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T10 |
1 |
| others[1] |
475 |
1 |
|
T3 |
6 |
|
T15 |
1 |
|
T10 |
1 |
| others[2] |
458 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T10 |
2 |
| others[3] |
779 |
1 |
|
T3 |
5 |
|
T10 |
2 |
|
T20 |
1 |
| false |
232 |
1 |
|
T9 |
1 |
|
T10 |
2 |
|
T37 |
6 |
| true |
2149 |
1 |
|
T3 |
29 |
|
T10 |
12 |
|
T70 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |