Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10233 |
1 |
|
T9 |
1 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
265 |
1 |
|
T37 |
4 |
|
T313 |
1 |
|
T90 |
1 |
| others[2] |
287 |
1 |
|
T37 |
10 |
|
T76 |
1 |
|
T235 |
1 |
| others[3] |
412 |
1 |
|
T17 |
1 |
|
T37 |
21 |
|
T41 |
1 |
| false |
152 |
1 |
|
T16 |
1 |
|
T37 |
7 |
|
T313 |
1 |
| true |
3165 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10188 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
16 |
| others[1] |
268 |
1 |
|
T37 |
13 |
|
T55 |
1 |
|
T6 |
1 |
| others[2] |
238 |
1 |
|
T37 |
4 |
|
T148 |
1 |
|
T67 |
1 |
| others[3] |
432 |
1 |
|
T16 |
1 |
|
T37 |
16 |
|
T76 |
1 |
| false |
110 |
1 |
|
T37 |
1 |
|
T120 |
1 |
|
T124 |
1 |
| true |
3278 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10746 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T16 |
1 |
| others[1] |
759 |
1 |
|
T3 |
10 |
|
T10 |
5 |
|
T37 |
28 |
| others[2] |
751 |
1 |
|
T3 |
16 |
|
T9 |
1 |
|
T10 |
2 |
| others[3] |
1276 |
1 |
|
T3 |
9 |
|
T10 |
4 |
|
T37 |
29 |
| false |
427 |
1 |
|
T3 |
6 |
|
T10 |
2 |
|
T20 |
1 |
| true |
555 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10744 |
1 |
|
T2 |
1 |
|
T3 |
12 |
|
T9 |
1 |
| others[1] |
784 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T16 |
1 |
| others[2] |
764 |
1 |
|
T3 |
10 |
|
T10 |
3 |
|
T20 |
1 |
| others[3] |
1254 |
1 |
|
T3 |
14 |
|
T10 |
9 |
|
T37 |
26 |
| false |
388 |
1 |
|
T3 |
8 |
|
T10 |
1 |
|
T37 |
10 |
| true |
580 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2472 |
1 |
|
T3 |
8 |
|
T18 |
18 |
|
T26 |
9 |
| others[1] |
2475 |
1 |
|
T3 |
9 |
|
T18 |
21 |
|
T26 |
14 |
| others[2] |
2517 |
1 |
|
T3 |
10 |
|
T17 |
1 |
|
T18 |
20 |
| others[3] |
4160 |
1 |
|
T2 |
1 |
|
T3 |
17 |
|
T15 |
1 |
| false |
1279 |
1 |
|
T3 |
7 |
|
T9 |
1 |
|
T18 |
10 |
| true |
1611 |
1 |
|
T10 |
20 |
|
T20 |
1 |
|
T37 |
48 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10201 |
1 |
|
T10 |
2 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
292 |
1 |
|
T9 |
1 |
|
T10 |
3 |
|
T37 |
9 |
| others[2] |
254 |
1 |
|
T10 |
4 |
|
T70 |
1 |
|
T37 |
11 |
| others[3] |
434 |
1 |
|
T10 |
3 |
|
T37 |
19 |
|
T6 |
1 |
| false |
141 |
1 |
|
T11 |
1 |
|
T37 |
3 |
|
T67 |
1 |
| true |
3192 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10401 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T10 |
4 |
| others[1] |
480 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T16 |
1 |
| others[2] |
468 |
1 |
|
T3 |
5 |
|
T37 |
11 |
|
T88 |
1 |
| others[3] |
780 |
1 |
|
T3 |
11 |
|
T10 |
2 |
|
T37 |
21 |
| false |
251 |
1 |
|
T3 |
2 |
|
T10 |
1 |
|
T37 |
10 |
| true |
2134 |
1 |
|
T3 |
21 |
|
T9 |
1 |
|
T10 |
12 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10170 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
11 |
| others[1] |
292 |
1 |
|
T9 |
1 |
|
T16 |
1 |
|
T37 |
6 |
| others[2] |
223 |
1 |
|
T37 |
6 |
|
T216 |
1 |
|
T157 |
1 |
| others[3] |
440 |
1 |
|
T15 |
1 |
|
T70 |
1 |
|
T37 |
13 |
| false |
131 |
1 |
|
T37 |
9 |
|
T88 |
1 |
|
T63 |
1 |
| true |
3258 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T10 |
20 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10174 |
1 |
|
T15 |
1 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
254 |
1 |
|
T37 |
8 |
|
T6 |
1 |
|
T19 |
3 |
| others[2] |
248 |
1 |
|
T37 |
10 |
|
T76 |
1 |
|
T6 |
1 |
| others[3] |
434 |
1 |
|
T17 |
1 |
|
T11 |
1 |
|
T37 |
14 |
| false |
133 |
1 |
|
T37 |
9 |
|
T60 |
1 |
|
T83 |
1 |
| true |
3271 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10710 |
1 |
|
T2 |
1 |
|
T3 |
12 |
|
T9 |
1 |
| others[1] |
806 |
1 |
|
T3 |
12 |
|
T10 |
3 |
|
T20 |
1 |
| others[2] |
777 |
1 |
|
T3 |
12 |
|
T10 |
5 |
|
T11 |
1 |
| others[3] |
1265 |
1 |
|
T3 |
12 |
|
T16 |
1 |
|
T10 |
6 |
| false |
395 |
1 |
|
T3 |
3 |
|
T10 |
1 |
|
T37 |
9 |
| true |
561 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10718 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T10 |
1 |
| others[1] |
775 |
1 |
|
T3 |
8 |
|
T10 |
5 |
|
T37 |
24 |
| others[2] |
752 |
1 |
|
T3 |
13 |
|
T16 |
1 |
|
T10 |
6 |
| others[3] |
1300 |
1 |
|
T3 |
19 |
|
T9 |
1 |
|
T10 |
4 |
| false |
408 |
1 |
|
T3 |
3 |
|
T10 |
4 |
|
T37 |
14 |
| true |
561 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2490 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T15 |
1 |
| others[1] |
2431 |
1 |
|
T3 |
11 |
|
T18 |
25 |
|
T26 |
17 |
| others[2] |
2453 |
1 |
|
T3 |
7 |
|
T18 |
18 |
|
T26 |
9 |
| others[3] |
4212 |
1 |
|
T3 |
17 |
|
T18 |
25 |
|
T26 |
18 |
| false |
1339 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T18 |
18 |
| true |
1589 |
1 |
|
T10 |
20 |
|
T20 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10202 |
1 |
|
T10 |
1 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
276 |
1 |
|
T10 |
1 |
|
T37 |
8 |
|
T148 |
1 |
| others[2] |
272 |
1 |
|
T10 |
4 |
|
T37 |
17 |
|
T40 |
1 |
| others[3] |
485 |
1 |
|
T10 |
6 |
|
T11 |
1 |
|
T37 |
17 |
| false |
136 |
1 |
|
T10 |
2 |
|
T37 |
3 |
|
T90 |
1 |
| true |
3143 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10428 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T10 |
2 |
| others[1] |
466 |
1 |
|
T3 |
2 |
|
T10 |
3 |
|
T17 |
1 |
| others[2] |
445 |
1 |
|
T3 |
2 |
|
T10 |
1 |
|
T37 |
11 |
| others[3] |
774 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T9 |
1 |
| false |
233 |
1 |
|
T3 |
2 |
|
T37 |
4 |
|
T255 |
1 |
| true |
2168 |
1 |
|
T3 |
28 |
|
T16 |
1 |
|
T10 |
12 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10178 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
13 |
| others[1] |
266 |
1 |
|
T37 |
7 |
|
T120 |
1 |
|
T104 |
1 |
| others[2] |
261 |
1 |
|
T37 |
8 |
|
T67 |
1 |
|
T90 |
1 |
| others[3] |
446 |
1 |
|
T11 |
1 |
|
T37 |
13 |
|
T148 |
1 |
| false |
132 |
1 |
|
T37 |
9 |
|
T83 |
1 |
|
T403 |
1 |
| true |
3231 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10150 |
1 |
|
T17 |
1 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
260 |
1 |
|
T37 |
15 |
|
T67 |
1 |
|
T44 |
1 |
| others[2] |
254 |
1 |
|
T9 |
1 |
|
T70 |
1 |
|
T37 |
11 |
| others[3] |
421 |
1 |
|
T16 |
1 |
|
T37 |
6 |
|
T88 |
1 |
| false |
131 |
1 |
|
T37 |
4 |
|
T216 |
1 |
|
T90 |
2 |
| true |
3298 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10709 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T10 |
2 |
| others[1] |
799 |
1 |
|
T3 |
10 |
|
T9 |
1 |
|
T10 |
6 |
| others[2] |
758 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T16 |
1 |
| others[3] |
1269 |
1 |
|
T3 |
16 |
|
T10 |
7 |
|
T20 |
1 |
| false |
417 |
1 |
|
T3 |
6 |
|
T10 |
1 |
|
T37 |
8 |
| true |
562 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10709 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T10 |
2 |
| others[1] |
802 |
1 |
|
T3 |
12 |
|
T9 |
1 |
|
T10 |
5 |
| others[2] |
765 |
1 |
|
T3 |
7 |
|
T16 |
1 |
|
T10 |
3 |
| others[3] |
1271 |
1 |
|
T3 |
15 |
|
T15 |
1 |
|
T10 |
5 |
| false |
388 |
1 |
|
T3 |
10 |
|
T10 |
5 |
|
T37 |
10 |
| true |
579 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2457 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T15 |
1 |
| others[1] |
2424 |
1 |
|
T3 |
12 |
|
T18 |
18 |
|
T26 |
12 |
| others[2] |
2528 |
1 |
|
T3 |
14 |
|
T9 |
1 |
|
T16 |
1 |
| others[3] |
4192 |
1 |
|
T3 |
12 |
|
T17 |
1 |
|
T18 |
30 |
| false |
1298 |
1 |
|
T3 |
3 |
|
T18 |
8 |
|
T26 |
4 |
| true |
1615 |
1 |
|
T10 |
20 |
|
T20 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10219 |
1 |
|
T10 |
2 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
270 |
1 |
|
T16 |
1 |
|
T10 |
1 |
|
T37 |
6 |
| others[2] |
275 |
1 |
|
T10 |
4 |
|
T11 |
1 |
|
T37 |
10 |
| others[3] |
461 |
1 |
|
T15 |
1 |
|
T10 |
7 |
|
T37 |
17 |
| false |
142 |
1 |
|
T37 |
8 |
|
T56 |
1 |
|
T216 |
1 |
| true |
3147 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10374 |
1 |
|
T2 |
1 |
|
T3 |
3 |
|
T10 |
1 |
| others[1] |
477 |
1 |
|
T3 |
3 |
|
T70 |
1 |
|
T37 |
13 |
| others[2] |
455 |
1 |
|
T3 |
2 |
|
T10 |
2 |
|
T17 |
1 |
| others[3] |
786 |
1 |
|
T3 |
14 |
|
T15 |
1 |
|
T9 |
1 |
| false |
218 |
1 |
|
T3 |
4 |
|
T10 |
1 |
|
T37 |
5 |
| true |
2204 |
1 |
|
T3 |
25 |
|
T10 |
10 |
|
T37 |
54 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10175 |
1 |
|
T17 |
1 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
234 |
1 |
|
T37 |
13 |
|
T42 |
1 |
|
T313 |
2 |
| others[2] |
276 |
1 |
|
T15 |
1 |
|
T11 |
1 |
|
T37 |
12 |
| others[3] |
453 |
1 |
|
T16 |
1 |
|
T37 |
16 |
|
T148 |
1 |
| false |
153 |
1 |
|
T37 |
7 |
|
T90 |
1 |
|
T401 |
1 |
| true |
3223 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10191 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
12 |
| others[1] |
259 |
1 |
|
T9 |
1 |
|
T37 |
3 |
|
T88 |
1 |
| others[2] |
286 |
1 |
|
T16 |
1 |
|
T70 |
1 |
|
T37 |
9 |
| others[3] |
405 |
1 |
|
T15 |
1 |
|
T11 |
1 |
|
T37 |
12 |
| false |
131 |
1 |
|
T37 |
3 |
|
T6 |
1 |
|
T90 |
1 |
| true |
3242 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T10 |
20 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10733 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T10 |
3 |
| others[1] |
773 |
1 |
|
T3 |
18 |
|
T10 |
2 |
|
T20 |
1 |
| others[2] |
790 |
1 |
|
T3 |
7 |
|
T10 |
5 |
|
T37 |
19 |
| others[3] |
1275 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T9 |
1 |
| false |
376 |
1 |
|
T3 |
8 |
|
T10 |
3 |
|
T37 |
11 |
| true |
567 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10704 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T10 |
4 |
| others[1] |
775 |
1 |
|
T3 |
9 |
|
T10 |
7 |
|
T20 |
1 |
| others[2] |
727 |
1 |
|
T3 |
7 |
|
T10 |
4 |
|
T37 |
18 |
| others[3] |
1307 |
1 |
|
T3 |
18 |
|
T15 |
1 |
|
T9 |
1 |
| false |
427 |
1 |
|
T3 |
8 |
|
T16 |
1 |
|
T37 |
11 |
| true |
574 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2452 |
1 |
|
T3 |
9 |
|
T18 |
26 |
|
T26 |
13 |
| others[1] |
2563 |
1 |
|
T3 |
11 |
|
T18 |
16 |
|
T26 |
14 |
| others[2] |
2438 |
1 |
|
T3 |
12 |
|
T9 |
1 |
|
T18 |
18 |
| others[3] |
4167 |
1 |
|
T2 |
1 |
|
T3 |
12 |
|
T15 |
1 |
| false |
1320 |
1 |
|
T3 |
7 |
|
T16 |
1 |
|
T18 |
6 |
| true |
1574 |
1 |
|
T10 |
20 |
|
T17 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10190 |
1 |
|
T10 |
2 |
|
T17 |
1 |
|
T18 |
100 |
| others[1] |
298 |
1 |
|
T10 |
2 |
|
T37 |
7 |
|
T6 |
1 |
| others[2] |
252 |
1 |
|
T10 |
2 |
|
T37 |
13 |
|
T76 |
1 |
| others[3] |
433 |
1 |
|
T15 |
1 |
|
T9 |
1 |
|
T16 |
1 |
| false |
147 |
1 |
|
T10 |
3 |
|
T37 |
4 |
|
T41 |
1 |
| true |
3194 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T10 |
6 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |