Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9520 |
1 |
|
T22 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
278 |
1 |
|
T104 |
1 |
|
T37 |
1 |
|
T54 |
1 |
| others[2] |
276 |
1 |
|
T3 |
1 |
|
T16 |
1 |
|
T31 |
1 |
| others[3] |
448 |
1 |
|
T2 |
1 |
|
T22 |
3 |
|
T132 |
1 |
| false |
143 |
1 |
|
T25 |
1 |
|
T22 |
1 |
|
T159 |
1 |
| true |
3282 |
1 |
|
T1 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9514 |
1 |
|
T4 |
2 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
266 |
1 |
|
T235 |
1 |
|
T261 |
1 |
|
T28 |
10 |
| others[2] |
246 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T103 |
1 |
| others[3] |
445 |
1 |
|
T4 |
1 |
|
T54 |
1 |
|
T72 |
1 |
| false |
135 |
1 |
|
T104 |
1 |
|
T60 |
1 |
|
T235 |
1 |
| true |
3341 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10026 |
1 |
|
T5 |
1 |
|
T8 |
9 |
|
T10 |
1 |
| others[1] |
815 |
1 |
|
T1 |
1 |
|
T8 |
12 |
|
T120 |
1 |
| others[2] |
768 |
1 |
|
T8 |
8 |
|
T52 |
9 |
|
T103 |
1 |
| others[3] |
1381 |
1 |
|
T2 |
1 |
|
T8 |
17 |
|
T20 |
1 |
| false |
400 |
1 |
|
T8 |
3 |
|
T22 |
1 |
|
T61 |
1 |
| true |
557 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10067 |
1 |
|
T2 |
1 |
|
T8 |
9 |
|
T10 |
1 |
| others[1] |
746 |
1 |
|
T8 |
6 |
|
T120 |
1 |
|
T52 |
7 |
| others[2] |
775 |
1 |
|
T1 |
1 |
|
T8 |
10 |
|
T52 |
11 |
| others[3] |
1389 |
1 |
|
T8 |
17 |
|
T52 |
21 |
|
T107 |
8 |
| false |
404 |
1 |
|
T8 |
7 |
|
T52 |
3 |
|
T107 |
2 |
| true |
566 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2274 |
1 |
|
T2 |
1 |
|
T8 |
12 |
|
T26 |
1 |
| others[1] |
2302 |
1 |
|
T8 |
8 |
|
T10 |
1 |
|
T120 |
1 |
| others[2] |
2400 |
1 |
|
T1 |
1 |
|
T8 |
11 |
|
T55 |
29 |
| others[3] |
4057 |
1 |
|
T8 |
15 |
|
T16 |
1 |
|
T55 |
37 |
| false |
1296 |
1 |
|
T8 |
3 |
|
T55 |
12 |
|
T32 |
12 |
| true |
1618 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9520 |
1 |
|
T1 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
280 |
1 |
|
T54 |
1 |
|
T107 |
3 |
|
T232 |
2 |
| others[2] |
285 |
1 |
|
T234 |
1 |
|
T159 |
1 |
|
T107 |
2 |
| others[3] |
441 |
1 |
|
T31 |
1 |
|
T25 |
1 |
|
T59 |
1 |
| false |
174 |
1 |
|
T16 |
1 |
|
T104 |
1 |
|
T125 |
1 |
| true |
3247 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9734 |
1 |
|
T8 |
4 |
|
T16 |
1 |
|
T10 |
1 |
| others[1] |
448 |
1 |
|
T8 |
2 |
|
T30 |
1 |
|
T48 |
1 |
| others[2] |
446 |
1 |
|
T2 |
1 |
|
T8 |
10 |
|
T48 |
1 |
| others[3] |
784 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T8 |
5 |
| false |
237 |
1 |
|
T4 |
1 |
|
T8 |
3 |
|
T31 |
1 |
| true |
2298 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9520 |
1 |
|
T16 |
1 |
|
T67 |
1 |
|
T55 |
108 |
| others[1] |
285 |
1 |
|
T37 |
1 |
|
T159 |
1 |
|
T90 |
1 |
| others[2] |
231 |
1 |
|
T2 |
1 |
|
T132 |
1 |
|
T282 |
1 |
| others[3] |
464 |
1 |
|
T120 |
1 |
|
T132 |
1 |
|
T54 |
1 |
| false |
136 |
1 |
|
T68 |
1 |
|
T43 |
1 |
|
T81 |
1 |
| true |
3311 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9520 |
1 |
|
T4 |
2 |
|
T67 |
1 |
|
T55 |
108 |
| others[1] |
278 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T121 |
1 |
| others[2] |
281 |
1 |
|
T4 |
1 |
|
T133 |
1 |
|
T56 |
1 |
| others[3] |
430 |
1 |
|
T4 |
1 |
|
T37 |
1 |
|
T125 |
1 |
| false |
111 |
1 |
|
T18 |
2 |
|
T81 |
1 |
|
T28 |
6 |
| true |
3327 |
1 |
|
T1 |
1 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10051 |
1 |
|
T2 |
1 |
|
T8 |
17 |
|
T10 |
1 |
| others[1] |
853 |
1 |
|
T1 |
1 |
|
T8 |
8 |
|
T31 |
1 |
| others[2] |
742 |
1 |
|
T8 |
6 |
|
T52 |
3 |
|
T159 |
1 |
| others[3] |
1339 |
1 |
|
T8 |
12 |
|
T132 |
1 |
|
T52 |
21 |
| false |
418 |
1 |
|
T8 |
6 |
|
T52 |
7 |
|
T57 |
3 |
| true |
544 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10080 |
1 |
|
T8 |
17 |
|
T10 |
1 |
|
T26 |
1 |
| others[1] |
820 |
1 |
|
T8 |
9 |
|
T52 |
7 |
|
T107 |
3 |
| others[2] |
781 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
8 |
| others[3] |
1254 |
1 |
|
T8 |
14 |
|
T61 |
1 |
|
T120 |
1 |
| false |
428 |
1 |
|
T8 |
1 |
|
T52 |
3 |
|
T107 |
2 |
| true |
584 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2393 |
1 |
|
T8 |
11 |
|
T67 |
1 |
|
T55 |
22 |
| others[1] |
2361 |
1 |
|
T8 |
14 |
|
T26 |
1 |
|
T55 |
32 |
| others[2] |
2444 |
1 |
|
T8 |
5 |
|
T55 |
11 |
|
T32 |
20 |
| others[3] |
3922 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
17 |
| false |
1235 |
1 |
|
T8 |
2 |
|
T55 |
10 |
|
T32 |
13 |
| true |
1592 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9535 |
1 |
|
T22 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
268 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T54 |
1 |
| others[2] |
261 |
1 |
|
T22 |
2 |
|
T132 |
1 |
|
T107 |
2 |
| others[3] |
464 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T25 |
1 |
| false |
147 |
1 |
|
T31 |
1 |
|
T22 |
1 |
|
T367 |
1 |
| true |
3272 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9734 |
1 |
|
T5 |
1 |
|
T8 |
7 |
|
T10 |
1 |
| others[1] |
483 |
1 |
|
T8 |
5 |
|
T30 |
1 |
|
T52 |
13 |
| others[2] |
505 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
3 |
| others[3] |
722 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T8 |
9 |
| false |
239 |
1 |
|
T4 |
1 |
|
T8 |
2 |
|
T25 |
1 |
| true |
2264 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T8 |
23 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9525 |
1 |
|
T22 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
269 |
1 |
|
T16 |
1 |
|
T22 |
3 |
|
T132 |
1 |
| others[2] |
258 |
1 |
|
T3 |
1 |
|
T132 |
1 |
|
T159 |
1 |
| others[3] |
467 |
1 |
|
T1 |
1 |
|
T22 |
2 |
|
T104 |
1 |
| false |
136 |
1 |
|
T76 |
1 |
|
T28 |
3 |
|
T154 |
1 |
| true |
3292 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9503 |
1 |
|
T55 |
108 |
|
T32 |
100 |
|
T33 |
62 |
| others[1] |
249 |
1 |
|
T3 |
1 |
|
T90 |
1 |
|
T28 |
15 |
| others[2] |
279 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T60 |
1 |
| others[3] |
405 |
1 |
|
T4 |
4 |
|
T68 |
1 |
|
T125 |
1 |
| false |
129 |
1 |
|
T120 |
1 |
|
T59 |
1 |
|
T133 |
1 |
| true |
3382 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10135 |
1 |
|
T8 |
15 |
|
T10 |
1 |
|
T120 |
1 |
| others[1] |
760 |
1 |
|
T1 |
1 |
|
T8 |
8 |
|
T22 |
1 |
| others[2] |
768 |
1 |
|
T8 |
9 |
|
T61 |
1 |
|
T52 |
9 |
| others[3] |
1320 |
1 |
|
T8 |
11 |
|
T52 |
22 |
|
T107 |
9 |
| false |
413 |
1 |
|
T2 |
1 |
|
T8 |
6 |
|
T52 |
5 |
| true |
551 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10006 |
1 |
|
T1 |
1 |
|
T8 |
6 |
|
T10 |
1 |
| others[1] |
767 |
1 |
|
T2 |
1 |
|
T8 |
11 |
|
T52 |
14 |
| others[2] |
822 |
1 |
|
T8 |
11 |
|
T120 |
1 |
|
T52 |
7 |
| others[3] |
1381 |
1 |
|
T8 |
13 |
|
T48 |
1 |
|
T52 |
24 |
| false |
404 |
1 |
|
T8 |
8 |
|
T52 |
9 |
|
T107 |
1 |
| true |
567 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2407 |
1 |
|
T8 |
5 |
|
T26 |
1 |
|
T55 |
20 |
| others[1] |
2384 |
1 |
|
T8 |
8 |
|
T120 |
1 |
|
T55 |
18 |
| others[2] |
2284 |
1 |
|
T8 |
16 |
|
T55 |
20 |
|
T32 |
26 |
| others[3] |
4014 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
13 |
| false |
1239 |
1 |
|
T8 |
7 |
|
T55 |
12 |
|
T32 |
6 |
| true |
1619 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9534 |
1 |
|
T120 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
285 |
1 |
|
T22 |
6 |
|
T72 |
1 |
|
T159 |
1 |
| others[2] |
240 |
1 |
|
T4 |
2 |
|
T30 |
1 |
|
T107 |
2 |
| others[3] |
456 |
1 |
|
T4 |
3 |
|
T16 |
1 |
|
T67 |
1 |
| false |
146 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T107 |
1 |
| true |
3286 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9734 |
1 |
|
T8 |
3 |
|
T10 |
1 |
|
T31 |
1 |
| others[1] |
481 |
1 |
|
T8 |
2 |
|
T52 |
8 |
|
T107 |
3 |
| others[2] |
454 |
1 |
|
T8 |
5 |
|
T22 |
3 |
|
T48 |
1 |
| others[3] |
748 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T8 |
7 |
| false |
273 |
1 |
|
T8 |
3 |
|
T22 |
1 |
|
T52 |
4 |
| true |
2257 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
5 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9517 |
1 |
|
T2 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
272 |
1 |
|
T282 |
1 |
|
T60 |
1 |
|
T367 |
2 |
| others[2] |
261 |
1 |
|
T54 |
1 |
|
T133 |
1 |
|
T56 |
1 |
| others[3] |
450 |
1 |
|
T30 |
1 |
|
T67 |
1 |
|
T103 |
1 |
| false |
133 |
1 |
|
T31 |
1 |
|
T367 |
1 |
|
T223 |
1 |
| true |
3314 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T4 |
6 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9484 |
1 |
|
T55 |
108 |
|
T32 |
100 |
|
T33 |
62 |
| others[1] |
268 |
1 |
|
T4 |
1 |
|
T56 |
1 |
|
T235 |
1 |
| others[2] |
244 |
1 |
|
T4 |
1 |
|
T54 |
1 |
|
T159 |
1 |
| others[3] |
440 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T282 |
1 |
| false |
136 |
1 |
|
T67 |
1 |
|
T37 |
1 |
|
T40 |
1 |
| true |
3375 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
3 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10062 |
1 |
|
T8 |
12 |
|
T10 |
1 |
|
T26 |
1 |
| others[1] |
755 |
1 |
|
T8 |
9 |
|
T52 |
10 |
|
T107 |
3 |
| others[2] |
803 |
1 |
|
T2 |
1 |
|
T8 |
14 |
|
T52 |
8 |
| others[3] |
1381 |
1 |
|
T5 |
1 |
|
T8 |
12 |
|
T22 |
1 |
| false |
386 |
1 |
|
T1 |
1 |
|
T8 |
2 |
|
T120 |
1 |
| true |
560 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10046 |
1 |
|
T1 |
1 |
|
T8 |
8 |
|
T10 |
1 |
| others[1] |
842 |
1 |
|
T2 |
1 |
|
T8 |
14 |
|
T52 |
14 |
| others[2] |
782 |
1 |
|
T8 |
12 |
|
T52 |
8 |
|
T107 |
3 |
| others[3] |
1276 |
1 |
|
T8 |
11 |
|
T61 |
1 |
|
T120 |
1 |
| false |
412 |
1 |
|
T8 |
4 |
|
T52 |
5 |
|
T107 |
2 |
| true |
589 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2361 |
1 |
|
T8 |
9 |
|
T26 |
1 |
|
T55 |
19 |
| others[1] |
2405 |
1 |
|
T8 |
9 |
|
T55 |
24 |
|
T32 |
17 |
| others[2] |
2304 |
1 |
|
T1 |
1 |
|
T8 |
7 |
|
T10 |
1 |
| others[3] |
4015 |
1 |
|
T2 |
1 |
|
T8 |
20 |
|
T120 |
1 |
| false |
1232 |
1 |
|
T8 |
4 |
|
T55 |
12 |
|
T32 |
12 |
| true |
1630 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9548 |
1 |
|
T1 |
1 |
|
T25 |
1 |
|
T22 |
1 |
| others[1] |
253 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T59 |
1 |
| others[2] |
240 |
1 |
|
T72 |
1 |
|
T232 |
4 |
|
T367 |
1 |
| others[3] |
491 |
1 |
|
T16 |
1 |
|
T22 |
4 |
|
T107 |
3 |
| false |
131 |
1 |
|
T22 |
1 |
|
T107 |
4 |
|
T240 |
1 |
| true |
3284 |
1 |
|
T4 |
6 |
|
T5 |
1 |
|
T8 |
49 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |