Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_1.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_2.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_3.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_4.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9850 |
1 |
|
T16 |
1 |
|
T17 |
100 |
|
T29 |
62 |
| others[1] |
234 |
1 |
|
T32 |
1 |
|
T5 |
1 |
|
T28 |
10 |
| others[2] |
269 |
1 |
|
T62 |
1 |
|
T206 |
1 |
|
T28 |
12 |
| others[3] |
383 |
1 |
|
T33 |
1 |
|
T95 |
1 |
|
T28 |
18 |
| false |
117 |
1 |
|
T13 |
1 |
|
T18 |
1 |
|
T56 |
1 |
| true |
3382 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10368 |
1 |
|
T2 |
1 |
|
T3 |
11 |
|
T17 |
100 |
| others[1] |
843 |
1 |
|
T3 |
7 |
|
T13 |
1 |
|
T79 |
1 |
| others[2] |
782 |
1 |
|
T3 |
8 |
|
T8 |
1 |
|
T52 |
1 |
| others[3] |
1261 |
1 |
|
T3 |
21 |
|
T14 |
1 |
|
T15 |
1 |
| false |
429 |
1 |
|
T3 |
4 |
|
T8 |
1 |
|
T55 |
3 |
| true |
552 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10357 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T13 |
1 |
| others[1] |
749 |
1 |
|
T3 |
7 |
|
T14 |
1 |
|
T35 |
1 |
| others[2] |
801 |
1 |
|
T3 |
15 |
|
T125 |
1 |
|
T55 |
11 |
| others[3] |
1316 |
1 |
|
T3 |
10 |
|
T8 |
1 |
|
T65 |
1 |
| false |
417 |
1 |
|
T3 |
6 |
|
T8 |
1 |
|
T79 |
1 |
| true |
595 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2431 |
1 |
|
T3 |
5 |
|
T17 |
18 |
|
T29 |
10 |
| others[1] |
2394 |
1 |
|
T3 |
12 |
|
T14 |
1 |
|
T17 |
23 |
| others[2] |
2415 |
1 |
|
T3 |
8 |
|
T13 |
1 |
|
T17 |
24 |
| others[3] |
4176 |
1 |
|
T3 |
22 |
|
T15 |
1 |
|
T17 |
27 |
| false |
1237 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T17 |
8 |
| true |
1582 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9864 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
263 |
1 |
|
T63 |
1 |
|
T100 |
2 |
|
T206 |
1 |
| others[2] |
276 |
1 |
|
T50 |
1 |
|
T37 |
1 |
|
T63 |
2 |
| others[3] |
477 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T71 |
1 |
| false |
160 |
1 |
|
T5 |
1 |
|
T81 |
2 |
|
T100 |
1 |
| true |
3195 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10061 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T17 |
100 |
| others[1] |
438 |
1 |
|
T3 |
2 |
|
T5 |
1 |
|
T83 |
1 |
| others[2] |
489 |
1 |
|
T3 |
5 |
|
T16 |
1 |
|
T51 |
1 |
| others[3] |
779 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T18 |
1 |
| false |
218 |
1 |
|
T63 |
1 |
|
T55 |
6 |
|
T206 |
1 |
| true |
2250 |
1 |
|
T3 |
34 |
|
T8 |
2 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9856 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
244 |
1 |
|
T63 |
1 |
|
T28 |
10 |
|
T395 |
1 |
| others[2] |
281 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T22 |
1 |
| others[3] |
451 |
1 |
|
T71 |
1 |
|
T72 |
1 |
|
T63 |
3 |
| false |
159 |
1 |
|
T63 |
1 |
|
T81 |
1 |
|
T28 |
9 |
| true |
3244 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9836 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
270 |
1 |
|
T15 |
1 |
|
T18 |
1 |
|
T50 |
1 |
| others[2] |
265 |
1 |
|
T13 |
1 |
|
T32 |
1 |
|
T62 |
1 |
| others[3] |
428 |
1 |
|
T5 |
1 |
|
T206 |
1 |
|
T28 |
19 |
| false |
129 |
1 |
|
T16 |
1 |
|
T28 |
3 |
|
T166 |
1 |
| true |
3307 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10374 |
1 |
|
T2 |
1 |
|
T3 |
12 |
|
T17 |
100 |
| others[1] |
768 |
1 |
|
T3 |
9 |
|
T8 |
2 |
|
T35 |
1 |
| others[2] |
778 |
1 |
|
T3 |
13 |
|
T13 |
1 |
|
T74 |
1 |
| others[3] |
1314 |
1 |
|
T3 |
12 |
|
T14 |
1 |
|
T79 |
1 |
| false |
442 |
1 |
|
T3 |
5 |
|
T71 |
1 |
|
T52 |
1 |
| true |
559 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10414 |
1 |
|
T2 |
1 |
|
T3 |
6 |
|
T17 |
100 |
| others[1] |
772 |
1 |
|
T3 |
12 |
|
T8 |
2 |
|
T13 |
1 |
| others[2] |
777 |
1 |
|
T3 |
10 |
|
T14 |
1 |
|
T15 |
1 |
| others[3] |
1283 |
1 |
|
T3 |
18 |
|
T79 |
1 |
|
T38 |
1 |
| false |
403 |
1 |
|
T3 |
5 |
|
T65 |
1 |
|
T46 |
1 |
| true |
586 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2469 |
1 |
|
T3 |
11 |
|
T13 |
1 |
|
T17 |
29 |
| others[1] |
2416 |
1 |
|
T3 |
10 |
|
T14 |
1 |
|
T17 |
19 |
| others[2] |
2455 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T17 |
15 |
| others[3] |
4048 |
1 |
|
T3 |
16 |
|
T15 |
1 |
|
T17 |
30 |
| false |
1249 |
1 |
|
T3 |
6 |
|
T17 |
7 |
|
T29 |
6 |
| true |
1598 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9893 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
250 |
1 |
|
T71 |
1 |
|
T33 |
1 |
|
T62 |
1 |
| others[2] |
280 |
1 |
|
T8 |
1 |
|
T13 |
1 |
|
T22 |
1 |
| others[3] |
459 |
1 |
|
T8 |
1 |
|
T50 |
1 |
|
T51 |
1 |
| false |
144 |
1 |
|
T37 |
1 |
|
T100 |
3 |
|
T28 |
2 |
| true |
3209 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10082 |
1 |
|
T2 |
1 |
|
T3 |
6 |
|
T17 |
100 |
| others[1] |
465 |
1 |
|
T3 |
5 |
|
T14 |
1 |
|
T143 |
1 |
| others[2] |
432 |
1 |
|
T3 |
4 |
|
T8 |
1 |
|
T13 |
1 |
| others[3] |
768 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T32 |
1 |
| false |
238 |
1 |
|
T3 |
2 |
|
T8 |
1 |
|
T34 |
1 |
| true |
2250 |
1 |
|
T3 |
25 |
|
T16 |
1 |
|
T65 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9850 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
284 |
1 |
|
T14 |
1 |
|
T63 |
1 |
|
T46 |
1 |
| others[2] |
249 |
1 |
|
T13 |
1 |
|
T51 |
1 |
|
T63 |
1 |
| others[3] |
479 |
1 |
|
T18 |
1 |
|
T32 |
1 |
|
T34 |
1 |
| false |
141 |
1 |
|
T50 |
1 |
|
T56 |
1 |
|
T28 |
4 |
| true |
3232 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9892 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
259 |
1 |
|
T16 |
1 |
|
T56 |
1 |
|
T233 |
1 |
| others[2] |
259 |
1 |
|
T51 |
1 |
|
T81 |
1 |
|
T206 |
1 |
| others[3] |
412 |
1 |
|
T71 |
1 |
|
T28 |
12 |
|
T168 |
1 |
| false |
114 |
1 |
|
T62 |
1 |
|
T205 |
1 |
|
T28 |
4 |
| true |
3299 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10432 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T14 |
1 |
| others[1] |
853 |
1 |
|
T3 |
14 |
|
T8 |
1 |
|
T15 |
1 |
| others[2] |
768 |
1 |
|
T3 |
8 |
|
T8 |
1 |
|
T16 |
1 |
| others[3] |
1229 |
1 |
|
T3 |
15 |
|
T13 |
1 |
|
T63 |
1 |
| false |
379 |
1 |
|
T3 |
4 |
|
T5 |
1 |
|
T55 |
6 |
| true |
574 |
1 |
|
T18 |
1 |
|
T32 |
1 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10364 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T14 |
1 |
| others[1] |
777 |
1 |
|
T3 |
7 |
|
T109 |
1 |
|
T38 |
1 |
| others[2] |
802 |
1 |
|
T3 |
12 |
|
T8 |
1 |
|
T15 |
1 |
| others[3] |
1285 |
1 |
|
T3 |
18 |
|
T8 |
1 |
|
T13 |
1 |
| false |
434 |
1 |
|
T3 |
4 |
|
T84 |
1 |
|
T392 |
1 |
| true |
573 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2416 |
1 |
|
T2 |
1 |
|
T3 |
12 |
|
T17 |
16 |
| others[1] |
2400 |
1 |
|
T3 |
5 |
|
T17 |
17 |
|
T29 |
8 |
| others[2] |
2508 |
1 |
|
T3 |
9 |
|
T13 |
1 |
|
T17 |
26 |
| others[3] |
4064 |
1 |
|
T3 |
22 |
|
T15 |
1 |
|
T17 |
30 |
| false |
1279 |
1 |
|
T3 |
3 |
|
T14 |
1 |
|
T17 |
11 |
| true |
1568 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9860 |
1 |
|
T8 |
1 |
|
T17 |
100 |
|
T29 |
62 |
| others[1] |
279 |
1 |
|
T9 |
1 |
|
T5 |
1 |
|
T63 |
1 |
| others[2] |
290 |
1 |
|
T8 |
1 |
|
T32 |
1 |
|
T62 |
1 |
| others[3] |
484 |
1 |
|
T16 |
1 |
|
T33 |
1 |
|
T34 |
1 |
| false |
123 |
1 |
|
T72 |
1 |
|
T63 |
1 |
|
T56 |
1 |
| true |
3199 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10085 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T8 |
1 |
| others[1] |
447 |
1 |
|
T3 |
8 |
|
T18 |
1 |
|
T5 |
1 |
| others[2] |
476 |
1 |
|
T3 |
4 |
|
T14 |
1 |
|
T65 |
1 |
| others[3] |
791 |
1 |
|
T3 |
7 |
|
T8 |
1 |
|
T16 |
1 |
| false |
270 |
1 |
|
T3 |
1 |
|
T15 |
1 |
|
T5 |
1 |
| true |
2166 |
1 |
|
T3 |
23 |
|
T13 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9847 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
246 |
1 |
|
T63 |
1 |
|
T157 |
1 |
|
T213 |
1 |
| others[2] |
281 |
1 |
|
T14 |
1 |
|
T50 |
1 |
|
T63 |
1 |
| others[3] |
452 |
1 |
|
T32 |
1 |
|
T9 |
1 |
|
T37 |
1 |
| false |
136 |
1 |
|
T95 |
1 |
|
T205 |
1 |
|
T28 |
7 |
| true |
3273 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9855 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
264 |
1 |
|
T62 |
1 |
|
T51 |
1 |
|
T205 |
1 |
| others[2] |
269 |
1 |
|
T33 |
1 |
|
T79 |
1 |
|
T95 |
1 |
| others[3] |
386 |
1 |
|
T22 |
1 |
|
T5 |
2 |
|
T81 |
1 |
| false |
138 |
1 |
|
T81 |
1 |
|
T206 |
1 |
|
T28 |
3 |
| true |
3323 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10343 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T17 |
100 |
| others[1] |
769 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T71 |
1 |
| others[2] |
814 |
1 |
|
T3 |
13 |
|
T8 |
1 |
|
T65 |
1 |
| others[3] |
1347 |
1 |
|
T3 |
15 |
|
T8 |
1 |
|
T13 |
1 |
| false |
407 |
1 |
|
T3 |
5 |
|
T55 |
2 |
|
T216 |
1 |
| true |
555 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10343 |
1 |
|
T2 |
1 |
|
T3 |
16 |
|
T17 |
100 |
| others[1] |
789 |
1 |
|
T3 |
11 |
|
T8 |
2 |
|
T55 |
8 |
| others[2] |
815 |
1 |
|
T3 |
11 |
|
T14 |
1 |
|
T38 |
1 |
| others[3] |
1294 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T83 |
1 |
| false |
421 |
1 |
|
T3 |
4 |
|
T13 |
1 |
|
T55 |
5 |
| true |
573 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2427 |
1 |
|
T3 |
9 |
|
T13 |
1 |
|
T17 |
22 |
| others[1] |
2365 |
1 |
|
T3 |
11 |
|
T17 |
22 |
|
T29 |
9 |
| others[2] |
2469 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T17 |
17 |
| others[3] |
4053 |
1 |
|
T2 |
1 |
|
T3 |
18 |
|
T17 |
29 |
| false |
1315 |
1 |
|
T3 |
6 |
|
T14 |
1 |
|
T17 |
10 |
| true |
1606 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9859 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
264 |
1 |
|
T13 |
1 |
|
T81 |
2 |
|
T100 |
3 |
| others[2] |
267 |
1 |
|
T46 |
1 |
|
T81 |
1 |
|
T100 |
1 |
| others[3] |
471 |
1 |
|
T32 |
1 |
|
T34 |
1 |
|
T50 |
1 |
| false |
143 |
1 |
|
T37 |
1 |
|
T5 |
1 |
|
T28 |
5 |
| true |
3231 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10089 |
1 |
|
T2 |
1 |
|
T3 |
3 |
|
T15 |
1 |
| others[1] |
491 |
1 |
|
T3 |
3 |
|
T72 |
1 |
|
T35 |
1 |
| others[2] |
469 |
1 |
|
T3 |
6 |
|
T16 |
1 |
|
T65 |
1 |
| others[3] |
779 |
1 |
|
T3 |
9 |
|
T13 |
1 |
|
T34 |
1 |
| false |
244 |
1 |
|
T3 |
4 |
|
T37 |
1 |
|
T55 |
4 |
| true |
2163 |
1 |
|
T3 |
26 |
|
T8 |
2 |
|
T14 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9851 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
266 |
1 |
|
T37 |
1 |
|
T63 |
1 |
|
T28 |
10 |
| others[2] |
274 |
1 |
|
T22 |
1 |
|
T51 |
1 |
|
T63 |
1 |
| others[3] |
451 |
1 |
|
T13 |
1 |
|
T32 |
1 |
|
T63 |
2 |
| false |
140 |
1 |
|
T14 |
1 |
|
T63 |
1 |
|
T81 |
1 |
| true |
3253 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |