Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9716 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
5 |
| others[1] |
514 |
1 |
|
T8 |
7 |
|
T16 |
1 |
|
T22 |
1 |
| others[2] |
498 |
1 |
|
T8 |
4 |
|
T11 |
1 |
|
T22 |
1 |
| others[3] |
782 |
1 |
|
T8 |
2 |
|
T31 |
1 |
|
T22 |
3 |
| false |
266 |
1 |
|
T4 |
2 |
|
T8 |
2 |
|
T52 |
5 |
| true |
2171 |
1 |
|
T3 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9510 |
1 |
|
T120 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
275 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T22 |
1 |
| others[2] |
274 |
1 |
|
T22 |
2 |
|
T104 |
1 |
|
T60 |
1 |
| others[3] |
459 |
1 |
|
T22 |
3 |
|
T67 |
1 |
|
T132 |
2 |
| false |
125 |
1 |
|
T39 |
1 |
|
T28 |
3 |
|
T201 |
1 |
| true |
3304 |
1 |
|
T1 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9502 |
1 |
|
T16 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
230 |
1 |
|
T4 |
1 |
|
T67 |
1 |
|
T54 |
1 |
| others[2] |
228 |
1 |
|
T4 |
1 |
|
T241 |
1 |
|
T18 |
1 |
| others[3] |
488 |
1 |
|
T1 |
1 |
|
T3 |
1 |
|
T37 |
1 |
| false |
119 |
1 |
|
T2 |
1 |
|
T4 |
1 |
|
T240 |
1 |
| true |
3380 |
1 |
|
T4 |
3 |
|
T5 |
1 |
|
T8 |
49 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10038 |
1 |
|
T8 |
9 |
|
T10 |
1 |
|
T26 |
1 |
| others[1] |
849 |
1 |
|
T8 |
12 |
|
T120 |
1 |
|
T52 |
19 |
| others[2] |
826 |
1 |
|
T8 |
7 |
|
T52 |
9 |
|
T107 |
3 |
| others[3] |
1279 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
16 |
| false |
402 |
1 |
|
T8 |
5 |
|
T52 |
7 |
|
T107 |
5 |
| true |
553 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10053 |
1 |
|
T8 |
7 |
|
T10 |
1 |
|
T120 |
1 |
| others[1] |
782 |
1 |
|
T8 |
9 |
|
T52 |
10 |
|
T107 |
5 |
| others[2] |
754 |
1 |
|
T8 |
11 |
|
T52 |
9 |
|
T107 |
5 |
| others[3] |
1377 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
19 |
| false |
417 |
1 |
|
T8 |
3 |
|
T52 |
7 |
|
T107 |
1 |
| true |
564 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2361 |
1 |
|
T2 |
1 |
|
T8 |
7 |
|
T55 |
20 |
| others[1] |
2438 |
1 |
|
T1 |
1 |
|
T8 |
10 |
|
T55 |
25 |
| others[2] |
2401 |
1 |
|
T8 |
12 |
|
T55 |
26 |
|
T32 |
24 |
| others[3] |
3925 |
1 |
|
T8 |
16 |
|
T10 |
1 |
|
T26 |
1 |
| false |
1225 |
1 |
|
T8 |
4 |
|
T120 |
1 |
|
T55 |
9 |
| true |
1597 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9549 |
1 |
|
T55 |
108 |
|
T32 |
100 |
|
T132 |
1 |
| others[1] |
285 |
1 |
|
T4 |
1 |
|
T22 |
2 |
|
T30 |
1 |
| others[2] |
268 |
1 |
|
T4 |
1 |
|
T16 |
1 |
|
T22 |
2 |
| others[3] |
465 |
1 |
|
T31 |
1 |
|
T22 |
1 |
|
T68 |
1 |
| false |
155 |
1 |
|
T22 |
1 |
|
T107 |
1 |
|
T235 |
1 |
| true |
3225 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9711 |
1 |
|
T4 |
2 |
|
T8 |
6 |
|
T10 |
1 |
| others[1] |
498 |
1 |
|
T1 |
1 |
|
T8 |
5 |
|
T53 |
1 |
| others[2] |
435 |
1 |
|
T2 |
1 |
|
T5 |
1 |
|
T8 |
7 |
| others[3] |
776 |
1 |
|
T4 |
3 |
|
T8 |
6 |
|
T16 |
1 |
| false |
269 |
1 |
|
T8 |
2 |
|
T25 |
1 |
|
T61 |
1 |
| true |
2258 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T8 |
23 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9517 |
1 |
|
T55 |
108 |
|
T32 |
100 |
|
T33 |
62 |
| others[1] |
295 |
1 |
|
T1 |
1 |
|
T16 |
1 |
|
T22 |
1 |
| others[2] |
260 |
1 |
|
T22 |
3 |
|
T133 |
1 |
|
T56 |
1 |
| others[3] |
425 |
1 |
|
T3 |
1 |
|
T25 |
1 |
|
T22 |
1 |
| false |
146 |
1 |
|
T22 |
1 |
|
T60 |
1 |
|
T28 |
4 |
| true |
3304 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9507 |
1 |
|
T55 |
108 |
|
T32 |
100 |
|
T33 |
62 |
| others[1] |
235 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T68 |
1 |
| others[2] |
282 |
1 |
|
T4 |
2 |
|
T30 |
1 |
|
T67 |
1 |
| others[3] |
412 |
1 |
|
T4 |
1 |
|
T159 |
1 |
|
T282 |
1 |
| false |
141 |
1 |
|
T16 |
1 |
|
T103 |
1 |
|
T223 |
1 |
| true |
3370 |
1 |
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10038 |
1 |
|
T3 |
1 |
|
T8 |
9 |
|
T10 |
1 |
| others[1] |
794 |
1 |
|
T8 |
11 |
|
T132 |
1 |
|
T52 |
10 |
| others[2] |
823 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T4 |
1 |
| others[3] |
1323 |
1 |
|
T4 |
1 |
|
T8 |
14 |
|
T61 |
1 |
| false |
413 |
1 |
|
T8 |
6 |
|
T31 |
1 |
|
T52 |
6 |
| true |
556 |
1 |
|
T4 |
4 |
|
T5 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10013 |
1 |
|
T8 |
7 |
|
T10 |
1 |
|
T26 |
1 |
| others[1] |
818 |
1 |
|
T8 |
9 |
|
T12 |
1 |
|
T61 |
1 |
| others[2] |
830 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
10 |
| others[3] |
1295 |
1 |
|
T8 |
15 |
|
T20 |
1 |
|
T52 |
17 |
| false |
424 |
1 |
|
T8 |
8 |
|
T52 |
9 |
|
T107 |
1 |
| true |
567 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2449 |
1 |
|
T8 |
10 |
|
T55 |
22 |
|
T32 |
26 |
| others[1] |
2393 |
1 |
|
T8 |
11 |
|
T26 |
1 |
|
T55 |
29 |
| others[2] |
2354 |
1 |
|
T1 |
1 |
|
T8 |
9 |
|
T16 |
1 |
| others[3] |
3901 |
1 |
|
T2 |
1 |
|
T8 |
11 |
|
T10 |
1 |
| false |
1284 |
1 |
|
T8 |
8 |
|
T55 |
7 |
|
T32 |
12 |
| true |
1566 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9555 |
1 |
|
T22 |
4 |
|
T30 |
1 |
|
T55 |
108 |
| others[1] |
247 |
1 |
|
T4 |
1 |
|
T22 |
1 |
|
T234 |
1 |
| others[2] |
287 |
1 |
|
T22 |
1 |
|
T37 |
1 |
|
T107 |
2 |
| others[3] |
470 |
1 |
|
T3 |
1 |
|
T4 |
1 |
|
T132 |
2 |
| false |
144 |
1 |
|
T1 |
1 |
|
T235 |
1 |
|
T232 |
1 |
| true |
3244 |
1 |
|
T2 |
1 |
|
T4 |
4 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9719 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T8 |
4 |
| others[1] |
508 |
1 |
|
T8 |
3 |
|
T62 |
1 |
|
T61 |
1 |
| others[2] |
474 |
1 |
|
T4 |
2 |
|
T8 |
1 |
|
T11 |
1 |
| others[3] |
826 |
1 |
|
T5 |
1 |
|
T8 |
6 |
|
T52 |
10 |
| false |
246 |
1 |
|
T2 |
1 |
|
T8 |
5 |
|
T20 |
1 |
| true |
2174 |
1 |
|
T3 |
1 |
|
T4 |
3 |
|
T8 |
30 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9506 |
1 |
|
T16 |
1 |
|
T55 |
108 |
|
T32 |
100 |
| others[1] |
252 |
1 |
|
T104 |
1 |
|
T72 |
1 |
|
T60 |
1 |
| others[2] |
264 |
1 |
|
T43 |
1 |
|
T240 |
1 |
|
T56 |
1 |
| others[3] |
440 |
1 |
|
T1 |
1 |
|
T31 |
1 |
|
T414 |
1 |
| false |
123 |
1 |
|
T3 |
1 |
|
T59 |
1 |
|
T56 |
1 |
| true |
3362 |
1 |
|
T2 |
1 |
|
T4 |
6 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
9509 |
1 |
|
T16 |
1 |
|
T67 |
1 |
|
T55 |
108 |
| others[1] |
224 |
1 |
|
T1 |
1 |
|
T4 |
1 |
|
T234 |
1 |
| others[2] |
258 |
1 |
|
T2 |
1 |
|
T4 |
3 |
|
T120 |
1 |
| others[3] |
439 |
1 |
|
T59 |
1 |
|
T235 |
1 |
|
T18 |
2 |
| false |
134 |
1 |
|
T76 |
1 |
|
T41 |
1 |
|
T90 |
1 |
| true |
3383 |
1 |
|
T3 |
1 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10102 |
1 |
|
T8 |
12 |
|
T10 |
1 |
|
T26 |
1 |
| others[1] |
772 |
1 |
|
T8 |
8 |
|
T132 |
1 |
|
T52 |
15 |
| others[2] |
816 |
1 |
|
T8 |
7 |
|
T120 |
1 |
|
T52 |
10 |
| others[3] |
1284 |
1 |
|
T1 |
1 |
|
T2 |
1 |
|
T8 |
15 |
| false |
434 |
1 |
|
T8 |
7 |
|
T48 |
1 |
|
T52 |
4 |
| true |
539 |
1 |
|
T3 |
1 |
|
T4 |
6 |
|
T5 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |