Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10425 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T10 |
4 |
| others[1] |
467 |
1 |
|
T3 |
2 |
|
T15 |
1 |
|
T10 |
2 |
| others[2] |
461 |
1 |
|
T3 |
5 |
|
T10 |
2 |
|
T37 |
11 |
| others[3] |
772 |
1 |
|
T3 |
8 |
|
T10 |
2 |
|
T37 |
18 |
| false |
245 |
1 |
|
T3 |
5 |
|
T16 |
1 |
|
T10 |
2 |
| true |
2144 |
1 |
|
T3 |
27 |
|
T9 |
1 |
|
T10 |
8 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10203 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
8 |
| others[1] |
270 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T37 |
5 |
| others[2] |
257 |
1 |
|
T37 |
11 |
|
T42 |
1 |
|
T56 |
1 |
| others[3] |
420 |
1 |
|
T37 |
12 |
|
T148 |
1 |
|
T56 |
3 |
| false |
141 |
1 |
|
T9 |
1 |
|
T37 |
6 |
|
T309 |
1 |
| true |
3223 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10191 |
1 |
|
T9 |
1 |
|
T17 |
1 |
|
T18 |
100 |
| others[1] |
249 |
1 |
|
T37 |
8 |
|
T88 |
1 |
|
T45 |
1 |
| others[2] |
266 |
1 |
|
T37 |
8 |
|
T104 |
1 |
|
T397 |
1 |
| others[3] |
393 |
1 |
|
T70 |
1 |
|
T11 |
1 |
|
T37 |
17 |
| false |
134 |
1 |
|
T37 |
3 |
|
T148 |
1 |
|
T6 |
1 |
| true |
3281 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10773 |
1 |
|
T2 |
1 |
|
T3 |
11 |
|
T10 |
7 |
| others[1] |
791 |
1 |
|
T3 |
11 |
|
T10 |
5 |
|
T37 |
25 |
| others[2] |
771 |
1 |
|
T3 |
11 |
|
T15 |
1 |
|
T10 |
5 |
| others[3] |
1237 |
1 |
|
T3 |
14 |
|
T16 |
1 |
|
T10 |
3 |
| false |
375 |
1 |
|
T3 |
4 |
|
T9 |
1 |
|
T20 |
1 |
| true |
567 |
1 |
|
T17 |
1 |
|
T70 |
1 |
|
T11 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10697 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T10 |
7 |
| others[1] |
769 |
1 |
|
T3 |
8 |
|
T9 |
1 |
|
T16 |
1 |
| others[2] |
777 |
1 |
|
T3 |
16 |
|
T10 |
3 |
|
T37 |
17 |
| others[3] |
1278 |
1 |
|
T3 |
13 |
|
T10 |
8 |
|
T37 |
30 |
| false |
420 |
1 |
|
T3 |
5 |
|
T10 |
1 |
|
T37 |
7 |
| true |
573 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2488 |
1 |
|
T3 |
11 |
|
T18 |
19 |
|
T26 |
14 |
| others[1] |
2475 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T18 |
18 |
| others[2] |
2483 |
1 |
|
T2 |
1 |
|
T3 |
15 |
|
T9 |
1 |
| others[3] |
4094 |
1 |
|
T3 |
15 |
|
T16 |
1 |
|
T18 |
38 |
| false |
1302 |
1 |
|
T3 |
2 |
|
T18 |
5 |
|
T26 |
4 |
| true |
1672 |
1 |
|
T10 |
20 |
|
T17 |
1 |
|
T20 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10201 |
1 |
|
T10 |
3 |
|
T18 |
100 |
|
T26 |
62 |
| others[1] |
263 |
1 |
|
T10 |
2 |
|
T37 |
7 |
|
T56 |
2 |
| others[2] |
238 |
1 |
|
T10 |
3 |
|
T37 |
9 |
|
T63 |
1 |
| others[3] |
445 |
1 |
|
T10 |
1 |
|
T17 |
1 |
|
T37 |
19 |
| false |
153 |
1 |
|
T10 |
1 |
|
T37 |
6 |
|
T88 |
1 |
| true |
3214 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10405 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T15 |
1 |
| others[1] |
477 |
1 |
|
T3 |
1 |
|
T10 |
1 |
|
T20 |
1 |
| others[2] |
446 |
1 |
|
T3 |
2 |
|
T16 |
1 |
|
T37 |
10 |
| others[3] |
807 |
1 |
|
T3 |
9 |
|
T10 |
1 |
|
T37 |
23 |
| false |
249 |
1 |
|
T3 |
2 |
|
T10 |
1 |
|
T37 |
3 |
| true |
2130 |
1 |
|
T3 |
32 |
|
T9 |
1 |
|
T10 |
16 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10181 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
6 |
| others[1] |
232 |
1 |
|
T17 |
1 |
|
T37 |
15 |
|
T157 |
1 |
| others[2] |
279 |
1 |
|
T15 |
1 |
|
T9 |
1 |
|
T37 |
6 |
| others[3] |
436 |
1 |
|
T37 |
12 |
|
T76 |
1 |
|
T67 |
1 |
| false |
136 |
1 |
|
T16 |
1 |
|
T37 |
2 |
|
T148 |
1 |
| true |
3250 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T10 |
20 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10186 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
5 |
| others[1] |
266 |
1 |
|
T37 |
12 |
|
T404 |
1 |
|
T38 |
19 |
| others[2] |
243 |
1 |
|
T37 |
9 |
|
T6 |
2 |
|
T89 |
2 |
| others[3] |
409 |
1 |
|
T37 |
20 |
|
T67 |
1 |
|
T90 |
1 |
| false |
148 |
1 |
|
T37 |
2 |
|
T76 |
1 |
|
T6 |
1 |
| true |
3262 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10684 |
1 |
|
T2 |
1 |
|
T3 |
10 |
|
T9 |
1 |
| others[1] |
795 |
1 |
|
T3 |
10 |
|
T10 |
4 |
|
T37 |
19 |
| others[2] |
776 |
1 |
|
T3 |
5 |
|
T10 |
4 |
|
T37 |
18 |
| others[3] |
1286 |
1 |
|
T3 |
18 |
|
T16 |
1 |
|
T10 |
3 |
| false |
401 |
1 |
|
T3 |
8 |
|
T10 |
5 |
|
T37 |
5 |
| true |
572 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10719 |
1 |
|
T2 |
1 |
|
T3 |
6 |
|
T10 |
4 |
| others[1] |
719 |
1 |
|
T3 |
10 |
|
T10 |
4 |
|
T37 |
19 |
| others[2] |
799 |
1 |
|
T3 |
13 |
|
T9 |
1 |
|
T10 |
4 |
| others[3] |
1299 |
1 |
|
T3 |
18 |
|
T10 |
4 |
|
T20 |
1 |
| false |
392 |
1 |
|
T3 |
4 |
|
T16 |
1 |
|
T10 |
4 |
| true |
586 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
2433 |
1 |
|
T3 |
11 |
|
T18 |
17 |
|
T26 |
11 |
| others[1] |
2476 |
1 |
|
T2 |
1 |
|
T3 |
15 |
|
T16 |
1 |
| others[2] |
2502 |
1 |
|
T3 |
8 |
|
T9 |
1 |
|
T18 |
23 |
| others[3] |
4198 |
1 |
|
T3 |
10 |
|
T15 |
1 |
|
T17 |
1 |
| false |
1309 |
1 |
|
T3 |
7 |
|
T18 |
9 |
|
T26 |
4 |
| true |
1596 |
1 |
|
T10 |
20 |
|
T20 |
1 |
|
T70 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10192 |
1 |
|
T16 |
1 |
|
T10 |
1 |
|
T18 |
100 |
| others[1] |
298 |
1 |
|
T10 |
1 |
|
T37 |
11 |
|
T44 |
1 |
| others[2] |
255 |
1 |
|
T10 |
2 |
|
T37 |
7 |
|
T227 |
1 |
| others[3] |
450 |
1 |
|
T10 |
3 |
|
T70 |
1 |
|
T37 |
17 |
| false |
134 |
1 |
|
T10 |
1 |
|
T37 |
8 |
|
T67 |
1 |
| true |
3185 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T15 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10405 |
1 |
|
T2 |
1 |
|
T3 |
4 |
|
T10 |
1 |
| others[1] |
485 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T10 |
3 |
| others[2] |
438 |
1 |
|
T3 |
6 |
|
T70 |
1 |
|
T37 |
7 |
| others[3] |
756 |
1 |
|
T3 |
7 |
|
T10 |
3 |
|
T17 |
1 |
| false |
258 |
1 |
|
T3 |
2 |
|
T10 |
1 |
|
T37 |
6 |
| true |
2172 |
1 |
|
T3 |
24 |
|
T9 |
1 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10206 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T37 |
14 |
| others[1] |
265 |
1 |
|
T15 |
1 |
|
T37 |
10 |
|
T88 |
1 |
| others[2] |
267 |
1 |
|
T70 |
1 |
|
T37 |
8 |
|
T90 |
1 |
| others[3] |
444 |
1 |
|
T37 |
19 |
|
T104 |
1 |
|
T60 |
1 |
| false |
136 |
1 |
|
T9 |
1 |
|
T37 |
3 |
|
T90 |
1 |
| true |
3196 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T16 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10176 |
1 |
|
T18 |
100 |
|
T26 |
62 |
|
T11 |
1 |
| others[1] |
248 |
1 |
|
T15 |
1 |
|
T37 |
8 |
|
T76 |
1 |
| others[2] |
282 |
1 |
|
T37 |
11 |
|
T6 |
3 |
|
T120 |
1 |
| others[3] |
440 |
1 |
|
T37 |
16 |
|
T148 |
1 |
|
T6 |
1 |
| false |
133 |
1 |
|
T37 |
10 |
|
T38 |
7 |
|
T86 |
5 |
| true |
3235 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T9 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| NAME | COUNT | AT LEAST | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| others[0] |
10676 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T9 |
1 |
| others[1] |
787 |
1 |
|
T3 |
9 |
|
T10 |
6 |
|
T37 |
20 |
| others[2] |
788 |
1 |
|
T3 |
13 |
|
T10 |
4 |
|
T37 |
15 |
| others[3] |
1303 |
1 |
|
T3 |
12 |
|
T16 |
1 |
|
T10 |
6 |
| false |
405 |
1 |
|
T3 |
10 |
|
T10 |
1 |
|
T37 |
12 |
| true |
555 |
1 |
|
T15 |
1 |
|
T17 |
1 |
|
T70 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |