Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_5.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_6.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.ecc_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.erase_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.he_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.prog_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.rd_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables |
6 |
0 |
6 |
100.00 |
Variables for Group Instance mubi4_cov_of_mubi4_cov_of_flash_ctrl_core_reg_block.mp_region_cfg_7.scramble_en
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value |
6 |
0 |
6 |
100.00 |
100 |
1 |
1 |
0 |
|
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9830 |
1 |
|
T16 |
1 |
|
T17 |
100 |
|
T29 |
62 |
| others[1] |
253 |
1 |
|
T62 |
1 |
|
T5 |
1 |
|
T81 |
1 |
| others[2] |
255 |
1 |
|
T14 |
1 |
|
T50 |
1 |
|
T81 |
2 |
| others[3] |
435 |
1 |
|
T5 |
2 |
|
T79 |
1 |
|
T28 |
15 |
| false |
131 |
1 |
|
T157 |
1 |
|
T28 |
4 |
|
T110 |
1 |
| true |
3331 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10390 |
1 |
|
T2 |
1 |
|
T3 |
9 |
|
T13 |
1 |
| others[1] |
771 |
1 |
|
T3 |
12 |
|
T55 |
10 |
|
T100 |
3 |
| others[2] |
806 |
1 |
|
T3 |
13 |
|
T65 |
1 |
|
T52 |
1 |
| others[3] |
1333 |
1 |
|
T3 |
15 |
|
T81 |
1 |
|
T38 |
1 |
| false |
385 |
1 |
|
T3 |
2 |
|
T8 |
2 |
|
T79 |
1 |
| true |
550 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10358 |
1 |
|
T2 |
1 |
|
T3 |
11 |
|
T17 |
100 |
| others[1] |
789 |
1 |
|
T3 |
8 |
|
T15 |
1 |
|
T65 |
1 |
| others[2] |
765 |
1 |
|
T3 |
9 |
|
T8 |
1 |
|
T55 |
9 |
| others[3] |
1319 |
1 |
|
T3 |
20 |
|
T14 |
1 |
|
T55 |
15 |
| false |
417 |
1 |
|
T3 |
3 |
|
T8 |
1 |
|
T13 |
1 |
| true |
587 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2371 |
1 |
|
T3 |
9 |
|
T17 |
23 |
|
T29 |
8 |
| others[1] |
2482 |
1 |
|
T3 |
9 |
|
T15 |
1 |
|
T17 |
17 |
| others[2] |
2415 |
1 |
|
T3 |
6 |
|
T17 |
17 |
|
T29 |
15 |
| others[3] |
4058 |
1 |
|
T2 |
1 |
|
T3 |
21 |
|
T13 |
1 |
| false |
1316 |
1 |
|
T3 |
6 |
|
T17 |
14 |
|
T29 |
6 |
| true |
1593 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9841 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
290 |
1 |
|
T35 |
1 |
|
T63 |
1 |
|
T81 |
1 |
| others[2] |
266 |
1 |
|
T14 |
1 |
|
T18 |
1 |
|
T71 |
1 |
| others[3] |
469 |
1 |
|
T34 |
1 |
|
T62 |
1 |
|
T5 |
1 |
| false |
144 |
1 |
|
T13 |
1 |
|
T32 |
1 |
|
T5 |
1 |
| true |
3225 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10043 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T17 |
100 |
| others[1] |
467 |
1 |
|
T3 |
4 |
|
T9 |
1 |
|
T34 |
1 |
| others[2] |
461 |
1 |
|
T3 |
7 |
|
T15 |
1 |
|
T50 |
1 |
| others[3] |
777 |
1 |
|
T3 |
5 |
|
T22 |
1 |
|
T72 |
1 |
| false |
263 |
1 |
|
T3 |
3 |
|
T37 |
1 |
|
T51 |
1 |
| true |
2224 |
1 |
|
T3 |
27 |
|
T8 |
2 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9863 |
1 |
|
T14 |
1 |
|
T17 |
100 |
|
T29 |
62 |
| others[1] |
234 |
1 |
|
T28 |
11 |
|
T113 |
1 |
|
T393 |
1 |
| others[2] |
302 |
1 |
|
T22 |
1 |
|
T28 |
7 |
|
T208 |
1 |
| others[3] |
409 |
1 |
|
T33 |
1 |
|
T51 |
1 |
|
T81 |
1 |
| false |
138 |
1 |
|
T81 |
1 |
|
T392 |
1 |
|
T28 |
5 |
| true |
3289 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9823 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
241 |
1 |
|
T13 |
1 |
|
T14 |
1 |
|
T205 |
1 |
| others[2] |
277 |
1 |
|
T33 |
1 |
|
T5 |
3 |
|
T109 |
1 |
| others[3] |
430 |
1 |
|
T22 |
1 |
|
T72 |
1 |
|
T50 |
1 |
| false |
119 |
1 |
|
T16 |
1 |
|
T9 |
1 |
|
T207 |
1 |
| true |
3345 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10371 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T8 |
1 |
| others[1] |
797 |
1 |
|
T3 |
16 |
|
T65 |
1 |
|
T63 |
1 |
| others[2] |
785 |
1 |
|
T3 |
11 |
|
T8 |
1 |
|
T14 |
1 |
| others[3] |
1314 |
1 |
|
T3 |
16 |
|
T13 |
1 |
|
T79 |
1 |
| false |
427 |
1 |
|
T3 |
1 |
|
T55 |
5 |
|
T216 |
1 |
| true |
541 |
1 |
|
T16 |
1 |
|
T18 |
1 |
|
T32 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10353 |
1 |
|
T2 |
1 |
|
T3 |
13 |
|
T13 |
1 |
| others[1] |
777 |
1 |
|
T3 |
12 |
|
T8 |
1 |
|
T34 |
1 |
| others[2] |
765 |
1 |
|
T3 |
5 |
|
T14 |
1 |
|
T65 |
1 |
| others[3] |
1366 |
1 |
|
T3 |
15 |
|
T8 |
1 |
|
T71 |
1 |
| false |
389 |
1 |
|
T3 |
6 |
|
T74 |
1 |
|
T79 |
1 |
| true |
585 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
2492 |
1 |
|
T2 |
1 |
|
T3 |
8 |
|
T14 |
1 |
| others[1] |
2424 |
1 |
|
T3 |
7 |
|
T17 |
20 |
|
T29 |
7 |
| others[2] |
2499 |
1 |
|
T3 |
5 |
|
T17 |
18 |
|
T29 |
13 |
| others[3] |
3970 |
1 |
|
T3 |
25 |
|
T13 |
1 |
|
T17 |
41 |
| false |
1240 |
1 |
|
T3 |
6 |
|
T15 |
1 |
|
T17 |
11 |
| true |
1610 |
1 |
|
T8 |
2 |
|
T16 |
1 |
|
T18 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9869 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
282 |
1 |
|
T14 |
1 |
|
T9 |
1 |
|
T34 |
1 |
| others[2] |
265 |
1 |
|
T8 |
1 |
|
T392 |
1 |
|
T124 |
1 |
| others[3] |
460 |
1 |
|
T8 |
1 |
|
T15 |
1 |
|
T18 |
1 |
| false |
138 |
1 |
|
T71 |
1 |
|
T63 |
3 |
|
T28 |
7 |
| true |
3221 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10095 |
1 |
|
T2 |
1 |
|
T3 |
5 |
|
T17 |
100 |
| others[1] |
460 |
1 |
|
T3 |
5 |
|
T15 |
1 |
|
T37 |
1 |
| others[2] |
452 |
1 |
|
T3 |
6 |
|
T71 |
1 |
|
T33 |
1 |
| others[3] |
756 |
1 |
|
T3 |
6 |
|
T14 |
1 |
|
T16 |
1 |
| false |
250 |
1 |
|
T3 |
2 |
|
T22 |
1 |
|
T6 |
1 |
| true |
2222 |
1 |
|
T3 |
27 |
|
T8 |
2 |
|
T13 |
1 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9851 |
1 |
|
T13 |
1 |
|
T17 |
100 |
|
T29 |
62 |
| others[1] |
264 |
1 |
|
T72 |
1 |
|
T109 |
1 |
|
T207 |
1 |
| others[2] |
268 |
1 |
|
T71 |
1 |
|
T22 |
1 |
|
T95 |
1 |
| others[3] |
449 |
1 |
|
T15 |
1 |
|
T37 |
1 |
|
T81 |
1 |
| false |
136 |
1 |
|
T33 |
1 |
|
T38 |
1 |
|
T233 |
1 |
| true |
3267 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
9848 |
1 |
|
T17 |
100 |
|
T29 |
62 |
|
T58 |
159 |
| others[1] |
244 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T32 |
1 |
| others[2] |
247 |
1 |
|
T33 |
1 |
|
T5 |
1 |
|
T79 |
1 |
| others[3] |
432 |
1 |
|
T14 |
1 |
|
T22 |
1 |
|
T62 |
1 |
| false |
147 |
1 |
|
T5 |
1 |
|
T207 |
1 |
|
T28 |
6 |
| true |
3317 |
1 |
|
T2 |
1 |
|
T3 |
51 |
|
T8 |
2 |
Summary for Variable cp_value
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
6 |
0 |
6 |
100.00 |
User Defined Bins for cp_value
Bins
| | | | | | | | | | | |
| others[0] |
10402 |
1 |
|
T2 |
1 |
|
T3 |
7 |
|
T17 |
100 |
| others[1] |
783 |
1 |
|
T3 |
6 |
|
T8 |
1 |
|
T14 |
1 |
| others[2] |
794 |
1 |
|
T3 |
11 |
|
T8 |
1 |
|
T13 |
1 |
| others[3] |
1286 |
1 |
|
T3 |
21 |
|
T65 |
1 |
|
T55 |
17 |
| false |
413 |
1 |
|
T3 |
6 |
|
T392 |
1 |
|
T55 |
6 |
| true |
557 |
1 |
|
T15 |
1 |
|
T16 |
1 |
|
T18 |
1 |
| 0% |
10% |
20% |
30% |
40% |
50% |
60% |
70% |
80% |
90% |
100% |