Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	237104	1		T2	4		T3	27		T16	20
auto[FlashEraseBank]	266410	1		T3	9		T10	14		T11	4

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	256618	1		T2	2		T3	36		T16	20
auto[FlashOpProgram]	229102	1		T2	1		T10	14		T18	89
auto[FlashOpErase]	13794	1		T2	1		T18	89		T30	41
auto[FlashOpInvalid]	4000	1		T18	200		T87	200		T149	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	256618	1		T2	2		T3	36		T16	20
op[FlashOpProgram]	229102	1		T2	1		T10	14		T18	89
op[FlashOpErase]	13794	1		T2	1		T18	89		T30	41
read_erase_read	551	1		T25	2		T31	15		T39	1
read_prog_read	794	1		T11	5		T63	2		T34	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	365322	1		T2	4		T3	36		T16	20
auto[FlashPartInfo]	130107	1		T10	14		T18	144		T29	198
auto[FlashPartInfo1]	2267	1		T18	44		T48	1		T58	1
auto[FlashPartInfo2]	5818	1		T18	102		T29	9		T33	10

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpErase]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	188576	1		T2	2		T3	36		T16	20
auto[FlashPartData]	auto[FlashOpProgram]	172086	1		T2	1		T18	48		T11	6
auto[FlashPartData]	auto[FlashOpErase]	2642	1		T2	1		T18	48		T30	41
auto[FlashPartData]	auto[FlashOpInvalid]	2018	1		T18	96		T87	112		T149	104
auto[FlashPartInfo]	auto[FlashOpRead]	63788	1		T18	48		T63	88		T12	301
auto[FlashPartInfo]	auto[FlashOpProgram]	54938	1		T10	14		T18	24		T29	198
auto[FlashPartInfo]	auto[FlashOpErase]	10765	1		T18	24		T108	289		T31	6
auto[FlashPartInfo]	auto[FlashOpInvalid]	616	1		T18	48		T87	30		T149	30
auto[FlashPartInfo1]	auto[FlashOpRead]	1436	1		T18	22		T48	1		T58	1
auto[FlashPartInfo1]	auto[FlashOpProgram]	165	1		T80	2		T351	1		T138	32
auto[FlashPartInfo1]	auto[FlashOpInvalid]	666	1		T18	22		T87	36		T149	26
auto[FlashPartInfo2]	auto[FlashOpRead]	2818	1		T18	34		T63	2		T12	10
auto[FlashPartInfo2]	auto[FlashOpProgram]	1913	1		T18	17		T29	9		T33	10
auto[FlashPartInfo2]	auto[FlashOpErase]	387	1		T18	17		T31	3		T87	11
auto[FlashPartInfo2]	auto[FlashOpInvalid]	700	1		T18	34		T87	22		T149	40