Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	16	1	15	93.75

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
erase_cp	2	0	2	100.00	100	1	1	0
op_cp	4	0	4	100.00	100	1	1	0
op_evict_cp	5	0	5	100.00	100	1	1	0
part_cp	4	0	4	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::control_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_part_cross	16	1	15	93.75	100	1	1	0

Summary for Variable erase_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for erase_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashErasePage]	233975	1		T2	4		T3	42		T14	20
auto[FlashEraseBank]	256132	1		T3	9		T8	2		T13	14

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Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashOpRead]	250079	1		T2	2		T3	51		T8	1
auto[FlashOpProgram]	220699	1		T2	1		T8	1		T13	14
auto[FlashOpErase]	15329	1		T2	1		T15	1		T17	84
auto[FlashOpInvalid]	4000	1		T17	200		T87	200		T159	200

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Summary for Variable op_evict_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for op_evict_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
op[FlashOpRead]	250079	1		T2	2		T3	51		T8	1
op[FlashOpProgram]	220699	1		T2	1		T8	1		T13	14
op[FlashOpErase]	15329	1		T2	1		T15	1		T17	84
read_erase_read	570	1		T65	2		T37	12		T6	1
read_prog_read	846	1		T32	3		T65	1		T9	1

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Summary for Variable part_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for part_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	343428	1		T2	4		T3	51		T8	2
auto[FlashPartInfo]	139180	1		T17	96		T58	934		T32	132
auto[FlashPartInfo1]	2240	1		T17	64		T32	1		T22	3
auto[FlashPartInfo2]	5259	1		T17	138		T32	6		T9	5

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Summary for Cross op_part_cross

Samples crossed: part_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for op_part_cross

Uncovered bins

part_cp	op_cp	COUNT	AT LEAST	NUMBER
[auto[FlashPartInfo1]]	[auto[FlashOpErase]]	0	1	1

Covered bins

part_cp	op_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[FlashPartData]	auto[FlashOpRead]	176367	1		T2	2		T3	51		T8	1
auto[FlashPartData]	auto[FlashOpProgram]	162377	1		T2	1		T8	1		T13	14
auto[FlashPartData]	auto[FlashOpErase]	2648	1		T2	1		T15	1		T17	45
auto[FlashPartData]	auto[FlashOpInvalid]	2036	1		T17	90		T87	106		T159	110
auto[FlashPartInfo]	auto[FlashOpRead]	69837	1		T17	32		T58	474		T32	99
auto[FlashPartInfo]	auto[FlashOpProgram]	56399	1		T17	16		T58	230		T32	33
auto[FlashPartInfo]	auto[FlashOpErase]	12314	1		T17	16		T58	230		T37	5
auto[FlashPartInfo]	auto[FlashOpInvalid]	630	1		T17	32		T87	22		T159	20
auto[FlashPartInfo1]	auto[FlashOpRead]	1411	1		T17	32		T32	1		T22	3
auto[FlashPartInfo1]	auto[FlashOpProgram]	161	1		T163	32		T146	32		T165	32
auto[FlashPartInfo1]	auto[FlashOpInvalid]	668	1		T17	32		T87	34		T159	24
auto[FlashPartInfo2]	auto[FlashOpRead]	2464	1		T17	46		T32	2		T9	3
auto[FlashPartInfo2]	auto[FlashOpProgram]	1762	1		T17	23		T32	4		T9	2
auto[FlashPartInfo2]	auto[FlashOpErase]	367	1		T17	23		T37	2		T87	19
auto[FlashPartInfo2]	auto[FlashOpInvalid]	666	1		T17	46		T87	38		T159	46