Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	29517	1		T2	4		T8	4		T17	336
auto[1]	45	1		T35	1		T430	3		T268	1
auto[2]	47	1		T35	1		T86	4		T312	8
auto[3]	264	1		T37	12		T36	1		T158	6

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	7461	1		T2	1		T8	1		T17	84
evic_idx[1]	7469	1		T2	1		T8	1		T17	84
evic_idx[2]	7471	1		T2	1		T8	1		T17	84
evic_idx[3]	7472	1		T2	1		T8	1		T17	84

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	28957	1		T2	4		T17	336		T58	488
evic_op[2]	335	1		T8	4		T65	16		T35	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	7172	1		T2	1		T17	84		T58	122
evic_idx[0]	evic_op[1]	auto[1]	6	1		T431	1		T432	5		-	-
evic_idx[0]	evic_op[1]	auto[2]	6	1		T312	1		T433	2		T431	2
evic_idx[0]	evic_op[1]	auto[3]	56	1		T37	3		T158	2		T434	2
evic_idx[0]	evic_op[2]	auto[0]	62	1		T8	1		T65	4		T100	6
evic_idx[0]	evic_op[2]	auto[1]	3	1		T435	1		T436	1		T437	1
evic_idx[0]	evic_op[2]	auto[2]	5	1		T438	2		T439	1		T436	1
evic_idx[0]	evic_op[2]	auto[3]	5	1		T440	1		T441	1		T442	1
evic_idx[1]	evic_op[1]	auto[0]	7169	1		T2	1		T17	84		T58	122
evic_idx[1]	evic_op[1]	auto[1]	7	1		T443	1		T444	1		T431	1
evic_idx[1]	evic_op[1]	auto[2]	5	1		T312	1		T433	1		T431	3
evic_idx[1]	evic_op[1]	auto[3]	57	1		T37	3		T434	3		T268	3
evic_idx[1]	evic_op[2]	auto[0]	66	1		T8	1		T65	4		T100	6
evic_idx[1]	evic_op[2]	auto[1]	6	1		T35	1		T430	1		T445	1
evic_idx[1]	evic_op[2]	auto[2]	2	1		T439	1		T446	1		-	-
evic_idx[1]	evic_op[2]	auto[3]	12	1		T36	1		T447	1		T448	1
evic_idx[2]	evic_op[1]	auto[0]	7166	1		T2	1		T17	84		T58	122
evic_idx[2]	evic_op[1]	auto[1]	8	1		T449	2		T444	1		T431	2
evic_idx[2]	evic_op[1]	auto[2]	7	1		T312	1		T433	1		T450	1
evic_idx[2]	evic_op[1]	auto[3]	61	1		T37	3		T158	2		T434	2
evic_idx[2]	evic_op[2]	auto[0]	67	1		T8	1		T65	4		T100	6
evic_idx[2]	evic_op[2]	auto[1]	3	1		T430	1		T451	1		T452	1
evic_idx[2]	evic_op[2]	auto[2]	4	1		T453	1		T439	1		T454	1
evic_idx[2]	evic_op[2]	auto[3]	10	1		T455	1		T313	1		T456	1
evic_idx[3]	evic_op[1]	auto[0]	7170	1		T2	1		T17	84		T58	122
evic_idx[3]	evic_op[1]	auto[1]	8	1		T268	1		T457	1		T449	1
evic_idx[3]	evic_op[1]	auto[2]	6	1		T312	1		T433	2		T457	1
evic_idx[3]	evic_op[1]	auto[3]	53	1		T37	3		T158	2		T434	2
evic_idx[3]	evic_op[2]	auto[0]	72	1		T8	1		T65	4		T100	6
evic_idx[3]	evic_op[2]	auto[1]	4	1		T430	1		T451	1		T458	1
evic_idx[3]	evic_op[2]	auto[2]	4	1		T35	1		T438	1		T459	1
evic_idx[3]	evic_op[2]	auto[3]	10	1		T460	1		T461	1		T338	1