Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
evic_cfg_cp	4	0	4	100.00	100	1	1	4
evic_idx_cp	4	0	4	100.00	100	1	1	0
evic_op_cp	2	0	2	100.00	100	1	1	0

Crosses for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::eviction_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
evic_all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for evic_cfg_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	26480	1		T2	4		T18	356		T11	24
auto[1]	22	1		T50	2		T148	1		T215	1
auto[2]	44	1		T35	1		T36	1		T148	14
auto[3]	265	1		T31	18		T36	1		T148	11

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Summary for Variable evic_idx_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for evic_idx_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	6703	1		T2	1		T18	89		T11	6
evic_idx[1]	6711	1		T2	1		T18	89		T11	6
evic_idx[2]	6703	1		T2	1		T18	89		T11	6
evic_idx[3]	6694	1		T2	1		T18	89		T11	6

---

Summary for Variable evic_op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for evic_op_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_op[1]	25866	1		T2	4		T18	356		T25	12
evic_op[2]	325	1		T11	24		T25	16		T50	2

---

Summary for Cross evic_all_cross

Samples crossed: evic_idx_cp evic_op_cp evic_cfg_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for evic_all_cross

Bins

evic_idx_cp	evic_op_cp	evic_cfg_cp	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
evic_idx[0]	evic_op[1]	auto[0]	6402	1		T2	1		T18	89		T25	3
evic_idx[0]	evic_op[1]	auto[1]	4	1		T410	2		T236	2		-	-
evic_idx[0]	evic_op[1]	auto[2]	5	1		T148	4		T411	1		-	-
evic_idx[0]	evic_op[1]	auto[3]	58	1		T31	6		T148	4		T412	7
evic_idx[0]	evic_op[2]	auto[0]	65	1		T11	6		T25	4		T221	5
evic_idx[0]	evic_op[2]	auto[1]	2	1		T413	1		T414	1		-	-
evic_idx[0]	evic_op[2]	auto[2]	2	1		T415	1		T416	1		-	-
evic_idx[0]	evic_op[2]	auto[3]	10	1		T239	1		T417	1		T418	1
evic_idx[1]	evic_op[1]	auto[0]	6406	1		T2	1		T18	89		T25	3
evic_idx[1]	evic_op[1]	auto[1]	4	1		T148	1		T410	1		T236	2
evic_idx[1]	evic_op[1]	auto[2]	3	1		T148	3		-	-		-	-
evic_idx[1]	evic_op[1]	auto[3]	59	1		T31	5		T148	3		T412	5
evic_idx[1]	evic_op[2]	auto[0]	64	1		T11	6		T25	4		T221	5
evic_idx[1]	evic_op[2]	auto[1]	1	1		T419	1		-	-		-	-
evic_idx[1]	evic_op[2]	auto[2]	4	1		T420	2		T415	1		T421	1
evic_idx[1]	evic_op[2]	auto[3]	15	1		T36	1		T239	1		T53	1
evic_idx[2]	evic_op[1]	auto[0]	6403	1		T2	1		T18	89		T25	3
evic_idx[2]	evic_op[1]	auto[1]	2	1		T410	1		T236	1		-	-
evic_idx[2]	evic_op[1]	auto[2]	4	1		T148	4		-	-		-	-
evic_idx[2]	evic_op[1]	auto[3]	55	1		T31	3		T148	1		T150	1
evic_idx[2]	evic_op[2]	auto[0]	67	1		T11	6		T25	4		T133	1
evic_idx[2]	evic_op[2]	auto[1]	5	1		T50	1		T215	1		T422	1
evic_idx[2]	evic_op[2]	auto[2]	2	1		T245	1		T415	1		-	-
evic_idx[2]	evic_op[2]	auto[3]	10	1		T239	1		T52	1		T199	1
evic_idx[3]	evic_op[1]	auto[0]	6403	1		T2	1		T18	89		T25	3
evic_idx[3]	evic_op[1]	auto[1]	3	1		T410	1		T236	2		-	-
evic_idx[3]	evic_op[1]	auto[2]	4	1		T148	3		T411	1		-	-
evic_idx[3]	evic_op[1]	auto[3]	51	1		T31	4		T148	3		T150	1
evic_idx[3]	evic_op[2]	auto[0]	66	1		T11	6		T25	4		T221	5
evic_idx[3]	evic_op[2]	auto[1]	1	1		T50	1		-	-		-	-
evic_idx[3]	evic_op[2]	auto[2]	4	1		T35	1		T36	1		T420	1
evic_idx[3]	evic_op[2]	auto[3]	7	1		T239	1		T423	1		T424	1