Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	50862	1		T44	1945		T312	16388		T328	2082
rd_lvl[2]	64925	1		T44	1189		T312	11996		T328	1053
rd_lvl[3]	19081	1		T44	519		T328	359		T342	304
rd_lvl[4]	45431	1		T44	511		T343	5528		T328	409
rd_lvl[5]	14911	1		T44	200		T343	980		T344	1519
rd_lvl[6]	17141	1		T44	10		T344	1295		T328	11
rd_lvl[7]	12619	1		T44	160		T45	124		T47	494
rd_lvl[8]	10800	1		T44	159		T45	36		T47	339
rd_lvl[9]	3382	1		T44	227		T47	154		T322	259
rd_lvl[10]	7772	1		T44	90		T47	88		T322	1338
rd_lvl[11]	4758	1		T44	161		T345	453		T344	1
rd_lvl[12]	9118	1		T44	2		T345	1139		T328	1
rd_lvl[13]	2745	1		T346	399		T41	161		T42	318
rd_lvl[14]	6393	1		T44	161		T328	155		T41	59
rd_lvl[15]	2557	1		T43	161		T347	142		T348	285