Unified Coverage Report :: Group :: flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

Group : flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_flash_ctrl_env_0.1/flash_ctrl_env_cov.sv

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Summary for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	3	15	83.33

Variables for Group flash_ctrl_env_pkg::flash_ctrl_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
prog_lvl_cp	3	3	0	0.00	100	1	1	0
rd_lvl_cp	15	0	15	100.00	100	1	1	0

Summary for Variable prog_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	3	0	0.00

User Defined Bins for prog_lvl_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
prog_lvl[1]	0	1	1
prog_lvl[2]	0	1	1
prog_lvl[3]	0	1	1

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Summary for Variable rd_lvl_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for rd_lvl_cp

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
rd_lvl[1]	31132	1		T49	15676		T348	2001		T349	2658
rd_lvl[2]	24671	1		T49	11220		T350	1954		T348	1205
rd_lvl[3]	10017	1		T350	1189		T348	501		T351	1238
rd_lvl[4]	39087	1		T48	1002		T350	500		T352	1779
rd_lvl[5]	19976	1		T46	879		T48	298		T350	932
rd_lvl[6]	18943	1		T46	400		T48	50		T350	1410
rd_lvl[7]	11066	1		T46	45		T48	190		T352	198
rd_lvl[8]	11753	1		T46	70		T48	83		T352	498
rd_lvl[9]	4633	1		T48	1		T353	127		T354	159
rd_lvl[10]	6569	1		T48	1		T353	6		T354	161
rd_lvl[11]	2773	1		T46	72		T348	184		T349	28
rd_lvl[12]	4181	1		T48	150		T43	298		T350	6
rd_lvl[13]	1605	1		T43	166		T350	6		T355	323
rd_lvl[14]	5401	1		T348	74		T356	1175		T357	1381
rd_lvl[15]	4371	1		T43	6		T44	279		T45	170