Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	412121	1		T1	1		T2	2		T3	2
all_pins[1]	412121	1		T1	1		T2	2		T3	2
all_pins[2]	412121	1		T1	1		T2	2		T3	2
all_pins[3]	412121	1		T1	1		T2	2		T3	2
all_pins[4]	412121	1		T1	1		T2	2		T3	2
all_pins[5]	412121	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2073291	1		T1	6		T2	12		T3	12
values[0x1]	399435	1		T33	1550		T44	5941		T45	240
transitions[0x0=>0x1]	363260	1		T33	1550		T44	5351		T45	240
transitions[0x1=>0x0]	363241	1		T33	1550		T44	5351		T45	240

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	411964	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	157	1		T269	5		T270	3		T277	3
all_pins[0]	transitions[0x0=>0x1]	79	1		T269	3		T270	1		T277	3
all_pins[0]	transitions[0x1=>0x0]	81	1		T269	1		T337	6		T338	1
all_pins[1]	values[0x0]	411962	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	159	1		T269	3		T270	2		T337	6
all_pins[1]	transitions[0x0=>0x1]	128	1		T269	2		T270	1		T337	4
all_pins[1]	transitions[0x1=>0x0]	2577	1		T43	128		T347	110		T348	200
all_pins[2]	values[0x0]	409513	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	2608	1		T43	128		T347	110		T348	200
all_pins[2]	transitions[0x0=>0x1]	39	1		T269	2		T270	2		T337	3
all_pins[2]	transitions[0x1=>0x0]	272560	1		T44	5334		T45	160		T47	1075
all_pins[3]	values[0x0]	136992	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	275129	1		T44	5334		T45	160		T47	1075
all_pins[3]	transitions[0x0=>0x1]	241686	1		T44	4744		T45	160		T47	966
all_pins[3]	transitions[0x1=>0x0]	87870	1		T33	1550		T44	17		T45	80
all_pins[4]	values[0x0]	290808	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	121313	1		T33	1550		T44	607		T45	80
all_pins[4]	transitions[0x0=>0x1]	121295	1		T33	1550		T44	607		T45	80
all_pins[4]	transitions[0x1=>0x0]	51	1		T269	1		T337	3		T338	2
all_pins[5]	values[0x0]	412052	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	69	1		T269	2		T337	3		T338	2
all_pins[5]	transitions[0x0=>0x1]	33	1		T269	1		T337	3		T338	1
all_pins[5]	transitions[0x1=>0x0]	102	1		T269	3		T270	2		T277	2