Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	6	0	6	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	311323	1		T1	1		T2	2		T3	2
all_pins[1]	311323	1		T1	1		T2	2		T3	2
all_pins[2]	311323	1		T1	1		T2	2		T3	2
all_pins[3]	311323	1		T1	1		T2	2		T3	2
all_pins[4]	311323	1		T1	1		T2	2		T3	2
all_pins[5]	311323	1		T1	1		T2	2		T3	2

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1551613	1		T1	6		T2	12		T3	12
values[0x1]	316325	1		T33	1602		T46	2101		T38	1326
transitions[0x0=>0x1]	280017	1		T33	1602		T46	1921		T38	1326
transitions[0x1=>0x0]	280001	1		T33	1602		T46	1921		T38	1326

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	311179	1		T1	1		T2	2		T3	2
all_pins[0]	values[0x1]	144	1		T339	2		T340	2		T341	5
all_pins[0]	transitions[0x0=>0x1]	86	1		T339	2		T341	4		T342	2
all_pins[0]	transitions[0x1=>0x0]	64	1		T250	1		T257	2		T342	2
all_pins[1]	values[0x0]	311201	1		T1	1		T2	2		T3	2
all_pins[1]	values[0x1]	122	1		T250	1		T257	2		T340	2
all_pins[1]	transitions[0x0=>0x1]	99	1		T250	1		T257	1		T340	1
all_pins[1]	transitions[0x1=>0x0]	4454	1		T44	312		T45	556		T360	1112
all_pins[2]	values[0x0]	306846	1		T1	1		T2	2		T3	2
all_pins[2]	values[0x1]	4477	1		T44	312		T45	556		T360	1112
all_pins[2]	transitions[0x0=>0x1]	36	1		T257	1		T340	1		T341	1
all_pins[2]	transitions[0x1=>0x0]	196603	1		T46	1466		T48	1775		T49	26896
all_pins[3]	values[0x0]	110279	1		T1	1		T2	2		T3	2
all_pins[3]	values[0x1]	201044	1		T46	1466		T48	1775		T49	26896
all_pins[3]	transitions[0x0=>0x1]	169309	1		T46	1286		T48	1188		T49	24171
all_pins[3]	transitions[0x1=>0x0]	78745	1		T33	1602		T46	455		T38	1326
all_pins[4]	values[0x0]	200843	1		T1	1		T2	2		T3	2
all_pins[4]	values[0x1]	110480	1		T33	1602		T46	635		T38	1326
all_pins[4]	transitions[0x0=>0x1]	110466	1		T33	1602		T46	635		T38	1326
all_pins[4]	transitions[0x1=>0x0]	44	1		T250	1		T341	3		T342	2
all_pins[5]	values[0x0]	311265	1		T1	1		T2	2		T3	2
all_pins[5]	values[0x1]	58	1		T250	1		T341	3		T342	2
all_pins[5]	transitions[0x0=>0x1]	21	1		T250	1		T361	1		T362	1
all_pins[5]	transitions[0x1=>0x0]	91	1		T339	2		T340	2		T341	1