Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	36	8	28	77.78

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	6	0	6	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=5}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	36	8	28	77.78	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	260	1		T250	4		T257	4		T339	4
all_values[1]	260	1		T250	4		T257	4		T339	4
all_values[2]	260	1		T250	4		T257	4		T339	4
all_values[3]	260	1		T250	4		T257	4		T339	4
all_values[4]	260	1		T250	4		T257	4		T339	4
all_values[5]	260	1		T250	4		T257	4		T339	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	842	1		T250	16		T257	17		T339	16
auto[1]	718	1		T250	8		T257	7		T339	8

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	525	1		T250	9		T257	12		T339	9
auto[1]	1035	1		T250	15		T257	12		T339	15

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	933	1		T250	16		T257	19		T339	17
auto[1]	627	1		T250	8		T257	5		T339	7

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	36	8	28	77.78	8
Automatically Generated Cross Bins	36	8	28	77.78	8
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[0]]	--	--	4
[all_values[2] , all_values[3]]	[auto[0]]	*	[auto[1]]	--	--	4

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[1]	85	1		T250	2		T257	4		T339	2
all_values[0]	auto[0]	auto[1]	auto[1]	74	1		T339	1		T340	3		T341	3
all_values[0]	auto[1]	auto[0]	auto[1]	60	1		T250	2		T341	1		T342	1
all_values[0]	auto[1]	auto[1]	auto[1]	41	1		T339	1		T343	1		T344	1
all_values[1]	auto[0]	auto[0]	auto[1]	97	1		T250	2		T257	3		T339	2
all_values[1]	auto[0]	auto[1]	auto[1]	58	1		T250	1		T340	2		T342	1
all_values[1]	auto[1]	auto[0]	auto[1]	57	1		T339	2		T341	1		T342	3
all_values[1]	auto[1]	auto[1]	auto[1]	48	1		T250	1		T257	1		T340	1
all_values[2]	auto[0]	auto[0]	auto[0]	79	1		T250	2		T339	1		T340	2
all_values[2]	auto[0]	auto[1]	auto[0]	80	1		T257	2		T339	3		T341	1
all_values[2]	auto[1]	auto[0]	auto[1]	48	1		T250	2		T257	1		T340	1
all_values[2]	auto[1]	auto[1]	auto[1]	53	1		T257	1		T340	1		T341	1
all_values[3]	auto[0]	auto[0]	auto[0]	88	1		T250	1		T257	1		T339	2
all_values[3]	auto[0]	auto[1]	auto[0]	63	1		T250	2		T257	3		T340	1
all_values[3]	auto[1]	auto[0]	auto[1]	46	1		T250	1		T339	2		T340	1
all_values[3]	auto[1]	auto[1]	auto[1]	63	1		T340	2		T342	3		T343	1
all_values[4]	auto[0]	auto[0]	auto[0]	52	1		T250	2		T257	3		T341	4
all_values[4]	auto[0]	auto[0]	auto[1]	25	1		T339	2		T340	1		T342	1
all_values[4]	auto[0]	auto[1]	auto[0]	48	1		T250	1		T340	2		T342	1
all_values[4]	auto[0]	auto[1]	auto[1]	29	1		T339	1		T342	1		T345	1
all_values[4]	auto[1]	auto[0]	auto[1]	58	1		T257	1		T339	1		T340	1
all_values[4]	auto[1]	auto[1]	auto[1]	48	1		T250	1		T342	3		T343	2
all_values[5]	auto[0]	auto[0]	auto[0]	70	1		T257	3		T339	1		T340	4
all_values[5]	auto[0]	auto[0]	auto[1]	16	1		T250	2		T342	1		T343	1
all_values[5]	auto[0]	auto[1]	auto[0]	45	1		T250	1		T339	2		T346	1
all_values[5]	auto[0]	auto[1]	auto[1]	24	1		T341	2		T346	1		T347	1
all_values[5]	auto[1]	auto[0]	auto[1]	61	1		T257	1		T339	1		T341	1
all_values[5]	auto[1]	auto[1]	auto[1]	44	1		T250	1		T341	1		T342	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal