Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29109190	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	7471564	1		T1	238		T2	161		T3	245

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	32324371	1		T1	420		T2	1132		T3	431
values[0x0]	2125917	1		T1	47		T2	83		T3	49
values[0x1]	2130466	1		T1	59		T2	83		T3	57

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	19486241	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17094513	1		T1	332		T2	539		T3	354

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	156307	1		T1	1		T2	2		T3	1
valid_sources[0x01]	118137	1		T3	2		T4	1		T10	2
valid_sources[0x02]	116089	1		T1	2		T16	8		T17	1
valid_sources[0x03]	136075	1		T1	2		T2	7		T9	3
valid_sources[0x04]	149351	1		T1	4		T3	3		T16	4
valid_sources[0x05]	121746	1		T1	2		T3	2		T4	21
valid_sources[0x06]	117483	1		T1	3		T2	4		T3	7
valid_sources[0x07]	124228	1		T1	3		T2	1		T3	6
valid_sources[0x08]	114922	1		T1	3		T2	2		T3	3
valid_sources[0x09]	116118	1		T2	1		T3	1		T4	4
valid_sources[0x0a]	116134	1		T1	5		T3	1		T4	3
valid_sources[0x0b]	139453	1		T2	5		T3	2		T4	2
valid_sources[0x0c]	142239	1		T1	1		T2	3		T3	7
valid_sources[0x0d]	118587	1		T1	2		T2	2		T3	3
valid_sources[0x0e]	178421	1		T1	2		T2	4		T5	1
valid_sources[0x0f]	199122	1		T1	1		T2	2		T3	1
valid_sources[0x10]	116111	1		T2	1		T17	1		T10	1
valid_sources[0x11]	134802	1		T1	1		T3	3		T16	1
valid_sources[0x12]	118435	1		T1	2		T2	2		T3	3
valid_sources[0x13]	117487	1		T1	2		T2	14		T4	3
valid_sources[0x14]	118937	1		T1	5		T2	9		T3	1
valid_sources[0x15]	210745	1		T2	6		T3	4		T4	4
valid_sources[0x16]	114009	1		T2	5		T3	1		T5	1
valid_sources[0x17]	117084	1		T2	3		T3	1		T4	1
valid_sources[0x18]	155536	1		T1	1		T2	5		T16	10
valid_sources[0x19]	183859	1		T1	1		T2	1		T3	2
valid_sources[0x1a]	117407	1		T1	9		T3	3		T4	1
valid_sources[0x1b]	116108	1		T1	1		T2	9		T3	3
valid_sources[0x1c]	116396	1		T1	8		T2	15		T5	3
valid_sources[0x1d]	117289	1		T1	4		T2	9		T4	8
valid_sources[0x1e]	132348	1		T2	2		T3	2		T4	1
valid_sources[0x1f]	118012	1		T1	1		T2	3		T3	3
valid_sources[0x20]	116379	1		T1	5		T2	5		T17	1
valid_sources[0x21]	148584	1		T3	1		T4	1		T25	1
valid_sources[0x22]	867443	1		T2	7		T16	5		T10	2
valid_sources[0x23]	515461	1		T1	3		T2	1		T3	2
valid_sources[0x24]	116237	1		T3	3		T16	1		T17	1
valid_sources[0x25]	116036	1		T1	5		T2	1		T3	3
valid_sources[0x26]	117316	1		T1	1		T2	10		T16	3
valid_sources[0x27]	215775	1		T3	2		T4	1		T16	2
valid_sources[0x28]	117765	1		T2	10		T3	3		T16	7
valid_sources[0x29]	115381	1		T2	8		T3	2		T4	3
valid_sources[0x2a]	115398	1		T1	7		T2	8		T3	1
valid_sources[0x2b]	117845	1		T2	2		T3	2		T4	10
valid_sources[0x2c]	116226	1		T1	1		T2	5		T3	4
valid_sources[0x2d]	137059	1		T1	1		T2	3		T3	4
valid_sources[0x2e]	206964	1		T1	2		T2	11		T3	4
valid_sources[0x2f]	119843	1		T1	5		T3	1		T16	1
valid_sources[0x30]	135500	1		T1	3		T2	13		T4	4
valid_sources[0x31]	155694	1		T1	1		T2	11		T3	1
valid_sources[0x32]	116430	1		T2	5		T3	4		T4	4
valid_sources[0x33]	114856	1		T2	3		T3	1		T17	1
valid_sources[0x34]	257492	1		T3	3		T5	2		T25	9
valid_sources[0x35]	132356	1		T1	2		T2	3		T3	6
valid_sources[0x36]	138424	1		T1	2		T2	17		T25	2
valid_sources[0x37]	135610	1		T1	2		T3	2		T9	3
valid_sources[0x38]	117190	1		T1	4		T2	2		T3	2
valid_sources[0x39]	117129	1		T1	2		T2	4		T3	5
valid_sources[0x3a]	115672	1		T1	1		T2	5		T3	2
valid_sources[0x3b]	115673	1		T2	16		T3	1		T31	1
valid_sources[0x3c]	115580	1		T2	11		T3	3		T4	1
valid_sources[0x3d]	134749	1		T1	1		T2	5		T3	2
valid_sources[0x3e]	116420	1		T2	3		T3	7		T5	1
valid_sources[0x3f]	116918	1		T1	3		T2	4		T16	2
valid_sources[0x40]	116563	1		T1	2		T2	5		T5	3
valid_sources[0x41]	116473	1		T2	1		T3	1		T5	1
valid_sources[0x42]	116329	1		T1	5		T2	1		T3	1
valid_sources[0x43]	154507	1		T1	4		T2	3		T3	3
valid_sources[0x44]	139205	1		T1	3		T2	3		T3	1
valid_sources[0x45]	116880	1		T1	4		T3	2		T17	1
valid_sources[0x46]	136419	1		T1	3		T2	4		T3	1
valid_sources[0x47]	119139	1		T1	1		T2	8		T3	2
valid_sources[0x48]	116605	1		T1	3		T3	1		T16	9
valid_sources[0x49]	116983	1		T3	2		T9	3		T31	2
valid_sources[0x4a]	116583	1		T1	2		T3	2		T5	3
valid_sources[0x4b]	117159	1		T1	9		T2	3		T3	7
valid_sources[0x4c]	115385	1		T1	2		T2	7		T3	3
valid_sources[0x4d]	120255	1		T3	3		T9	2		T25	6
valid_sources[0x4e]	116131	1		T2	12		T3	2		T10	2
valid_sources[0x4f]	116291	1		T1	1		T3	4		T4	1
valid_sources[0x50]	120333	1		T1	3		T3	6		T16	3
valid_sources[0x51]	116080	1		T2	3		T3	3		T5	2
valid_sources[0x52]	115067	1		T1	3		T2	20		T3	3
valid_sources[0x53]	155449	1		T1	1		T2	1		T3	3
valid_sources[0x54]	115861	1		T1	1		T3	2		T5	1
valid_sources[0x55]	167220	1		T3	2		T16	2		T10	3
valid_sources[0x56]	134459	1		T2	15		T3	1		T4	4
valid_sources[0x57]	131109	1		T2	14		T3	1		T16	5
valid_sources[0x58]	115658	1		T1	2		T2	11		T3	3
valid_sources[0x59]	117333	1		T1	3		T2	10		T3	1
valid_sources[0x5a]	116276	1		T1	6		T2	10		T3	3
valid_sources[0x5b]	126101	1		T1	2		T2	5		T3	1
valid_sources[0x5c]	117262	1		T1	1		T2	4		T3	1
valid_sources[0x5d]	136056	1		T3	4		T4	11		T10	1
valid_sources[0x5e]	118815	1		T1	1		T2	4		T3	3
valid_sources[0x5f]	140167	1		T2	2		T3	4		T5	1
valid_sources[0x60]	148287	1		T1	3		T2	1		T3	1
valid_sources[0x61]	150912	1		T1	3		T4	6		T5	1
valid_sources[0x62]	115387	1		T2	2		T4	2		T9	3
valid_sources[0x63]	115599	1		T1	3		T2	6		T3	6
valid_sources[0x64]	192222	1		T1	2		T2	2		T3	3
valid_sources[0x65]	173579	1		T2	3		T3	4		T5	1
valid_sources[0x66]	262208	1		T1	5		T2	3		T3	3
valid_sources[0x67]	142849	1		T2	10		T3	3		T16	2
valid_sources[0x68]	222958	1		T1	3		T2	5		T3	3
valid_sources[0x69]	117543	1		T1	6		T2	1		T3	1
valid_sources[0x6a]	152763	1		T1	5		T3	3		T4	2
valid_sources[0x6b]	117789	1		T2	8		T3	4		T16	2
valid_sources[0x6c]	304084	1		T2	6		T4	1		T17	1
valid_sources[0x6d]	115904	1		T1	4		T2	6		T3	4
valid_sources[0x6e]	117579	1		T2	2		T3	4		T16	2
valid_sources[0x6f]	205828	1		T1	3		T3	4		T4	1
valid_sources[0x70]	116522	1		T1	2		T2	5		T3	6
valid_sources[0x71]	117179	1		T2	10		T3	1		T16	5
valid_sources[0x72]	117039	1		T1	2		T2	11		T3	3
valid_sources[0x73]	161634	1		T1	2		T3	1		T5	1
valid_sources[0x74]	153636	1		T3	3		T31	1		T25	7
valid_sources[0x75]	114697	1		T1	1		T2	10		T3	2
valid_sources[0x76]	117025	1		T3	4		T4	4		T31	5
valid_sources[0x77]	117665	1		T1	4		T3	4		T16	2
valid_sources[0x78]	116944	1		T1	4		T2	11		T3	3
valid_sources[0x79]	128538	1		T3	8		T16	6		T62	2
valid_sources[0x7a]	117653	1		T1	4		T2	8		T3	3
valid_sources[0x7b]	115858	1		T2	8		T3	2		T16	3
valid_sources[0x7c]	115895	1		T2	12		T3	2		T17	1
valid_sources[0x7d]	116796	1		T1	1		T2	6		T4	7
valid_sources[0x7e]	122511	1		T1	3		T2	4		T3	2
valid_sources[0x7f]	262542	1		T3	1		T4	2		T16	1
valid_sources[0x80]	115654	1		T1	1		T2	1		T3	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3866392

1

T1

158

T2

10

T3

159

values[0x0]

all_enables

biggest_size

1891837

1

T1

39

T2

77

T3

43

values[0x1]

all_enables

biggest_size

1713335

1

T1

41

T2

74

T3

43

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1576	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4034431	1		T5	8		T8	621		T9	10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4028739	1		T5	8		T8	621		T9	10
values[0x0]	3092	1		T134	123		T135	15		T138	134
values[0x1]	4176	1		T134	119		T135	27		T138	183

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	615	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4035392	1		T5	8		T8	621		T9	10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15182	1		T8	2		T22	1		T12	1
valid_sources[0x01]	15740	1		T8	3		T22	2		T48	2
valid_sources[0x02]	15797	1		T8	4		T22	2		T48	1
valid_sources[0x03]	15152	1		T8	2		T22	1		T48	1
valid_sources[0x04]	15505	1		T8	1		T22	2		T48	5
valid_sources[0x05]	14917	1		T8	2		T22	1		T48	8
valid_sources[0x06]	15448	1		T8	2		T22	3		T48	3
valid_sources[0x07]	15672	1		T8	5		T22	1		T30	8
valid_sources[0x08]	15219	1		T5	1		T8	3		T22	2
valid_sources[0x09]	15319	1		T8	3		T22	2		T48	4
valid_sources[0x0a]	14995	1		T8	3		T22	3		T12	1
valid_sources[0x0b]	15103	1		T8	1		T22	3		T48	1
valid_sources[0x0c]	15247	1		T8	2		T22	1		T52	1
valid_sources[0x0d]	14971	1		T8	4		T22	1		T12	1
valid_sources[0x0e]	15207	1		T8	1		T22	1		T52	8
valid_sources[0x0f]	15284	1		T8	2		T22	1		T48	3
valid_sources[0x10]	14468	1		T8	3		T11	12		T22	3
valid_sources[0x11]	14938	1		T8	3		T48	3		T52	5
valid_sources[0x12]	15204	1		T22	1		T52	3		T103	1
valid_sources[0x13]	15302	1		T8	3		T22	2		T52	3
valid_sources[0x14]	15159	1		T8	4		T11	6		T22	1
valid_sources[0x15]	14919	1		T8	1		T22	5		T12	3
valid_sources[0x16]	15618	1		T8	2		T22	2		T52	2
valid_sources[0x17]	15124	1		T8	9		T22	3		T48	2
valid_sources[0x18]	15551	1		T8	2		T22	3		T12	1
valid_sources[0x19]	15421	1		T8	4		T22	3		T30	1
valid_sources[0x1a]	15059	1		T52	4		T104	64		T68	93
valid_sources[0x1b]	15236	1		T8	8		T22	2		T52	4
valid_sources[0x1c]	15190	1		T8	1		T11	2		T22	5
valid_sources[0x1d]	15336	1		T8	4		T22	3		T52	6
valid_sources[0x1e]	15143	1		T8	4		T22	1		T52	1
valid_sources[0x1f]	15712	1		T8	1		T22	2		T52	4
valid_sources[0x20]	15035	1		T8	3		T22	1		T52	2
valid_sources[0x21]	15440	1		T8	3		T22	6		T52	5
valid_sources[0x22]	15454	1		T5	1		T8	5		T22	2
valid_sources[0x23]	14928	1		T8	1		T22	1		T30	2
valid_sources[0x24]	14901	1		T8	5		T48	1		T52	2
valid_sources[0x25]	15196	1		T8	2		T22	1		T12	1
valid_sources[0x26]	15644	1		T8	3		T22	1		T52	1
valid_sources[0x27]	14966	1		T8	1		T22	3		T52	2
valid_sources[0x28]	15084	1		T8	1		T22	4		T30	2
valid_sources[0x29]	15641	1		T8	1		T52	1		T104	75
valid_sources[0x2a]	15243	1		T8	2		T22	2		T30	3
valid_sources[0x2b]	14995	1		T8	5		T22	4		T52	2
valid_sources[0x2c]	14895	1		T8	2		T52	4		T104	61
valid_sources[0x2d]	15094	1		T8	4		T22	2		T52	2
valid_sources[0x2e]	15420	1		T8	1		T22	2		T30	3
valid_sources[0x2f]	15130	1		T22	1		T219	1		T52	8
valid_sources[0x30]	15706	1		T8	4		T22	3		T52	4
valid_sources[0x31]	15637	1		T8	3		T22	1		T48	1
valid_sources[0x32]	15830	1		T8	4		T22	1		T48	5
valid_sources[0x33]	15334	1		T8	3		T22	1		T52	2
valid_sources[0x34]	14670	1		T8	5		T22	1		T52	3
valid_sources[0x35]	14950	1		T8	2		T22	2		T48	6
valid_sources[0x36]	14636	1		T8	2		T22	2		T48	1
valid_sources[0x37]	14950	1		T8	5		T48	2		T52	3
valid_sources[0x38]	15153	1		T8	1		T22	4		T12	3
valid_sources[0x39]	15179	1		T5	1		T8	4		T22	3
valid_sources[0x3a]	15366	1		T8	3		T22	3		T48	4
valid_sources[0x3b]	15510	1		T8	2		T22	2		T30	9
valid_sources[0x3c]	15198	1		T8	1		T22	2		T30	4
valid_sources[0x3d]	14749	1		T8	2		T22	3		T52	2
valid_sources[0x3e]	14968	1		T5	1		T8	2		T22	2
valid_sources[0x3f]	15110	1		T8	3		T11	11		T22	1
valid_sources[0x40]	15230	1		T8	1		T52	4		T104	63
valid_sources[0x41]	14957	1		T8	2		T22	1		T12	5
valid_sources[0x42]	15050	1		T8	1		T52	3		T104	58
valid_sources[0x43]	15305	1		T22	1		T52	3		T103	1
valid_sources[0x44]	15588	1		T8	2		T52	2		T103	2
valid_sources[0x45]	15350	1		T8	3		T22	5		T48	2
valid_sources[0x46]	15242	1		T8	1		T61	4		T48	4
valid_sources[0x47]	15757	1		T8	1		T12	4		T52	5
valid_sources[0x48]	15664	1		T8	4		T22	2		T30	15
valid_sources[0x49]	14940	1		T8	4		T22	1		T52	1
valid_sources[0x4a]	15245	1		T30	1		T48	3		T52	3
valid_sources[0x4b]	14713	1		T8	2		T22	1		T48	3
valid_sources[0x4c]	14951	1		T8	2		T52	4		T103	1
valid_sources[0x4d]	15431	1		T8	3		T22	1		T48	7
valid_sources[0x4e]	15621	1		T8	4		T22	2		T52	5
valid_sources[0x4f]	15059	1		T8	2		T22	4		T52	4
valid_sources[0x50]	15061	1		T8	2		T22	4		T48	6
valid_sources[0x51]	15249	1		T8	3		T22	1		T48	5
valid_sources[0x52]	15173	1		T8	2		T22	2		T104	72
valid_sources[0x53]	15217	1		T8	3		T22	2		T48	1
valid_sources[0x54]	14961	1		T8	5		T219	1		T103	4
valid_sources[0x55]	15049	1		T8	3		T52	1		T104	67
valid_sources[0x56]	15380	1		T8	1		T22	1		T48	3
valid_sources[0x57]	15017	1		T8	1		T22	4		T52	3
valid_sources[0x58]	14872	1		T8	4		T22	1		T12	4
valid_sources[0x59]	15255	1		T8	2		T22	5		T12	1
valid_sources[0x5a]	15178	1		T8	5		T22	3		T52	4
valid_sources[0x5b]	15711	1		T8	3		T22	1		T48	5
valid_sources[0x5c]	15368	1		T8	2		T48	1		T52	6
valid_sources[0x5d]	14956	1		T8	2		T22	1		T52	2
valid_sources[0x5e]	15778	1		T8	3		T22	1		T12	3
valid_sources[0x5f]	14843	1		T8	3		T22	3		T52	7
valid_sources[0x60]	15355	1		T8	3		T22	2		T52	8
valid_sources[0x61]	15099	1		T8	1		T22	1		T52	5
valid_sources[0x62]	15845	1		T8	2		T22	3		T48	3
valid_sources[0x63]	146512	1		T8	1		T11	4		T219	1
valid_sources[0x64]	15024	1		T8	1		T22	1		T48	6
valid_sources[0x65]	15504	1		T8	9		T22	1		T30	1
valid_sources[0x66]	15359	1		T8	1		T22	1		T104	75
valid_sources[0x67]	14885	1		T8	3		T22	4		T52	3
valid_sources[0x68]	15303	1		T8	2		T22	2		T52	2
valid_sources[0x69]	15044	1		T8	1		T22	1		T30	1
valid_sources[0x6a]	14693	1		T8	4		T22	2		T52	3
valid_sources[0x6b]	15598	1		T8	1		T22	1		T12	1
valid_sources[0x6c]	14911	1		T8	1		T22	2		T52	5
valid_sources[0x6d]	14949	1		T22	1		T48	8		T52	3
valid_sources[0x6e]	15643	1		T22	1		T12	2		T48	9
valid_sources[0x6f]	15621	1		T8	2		T22	2		T219	1
valid_sources[0x70]	15194	1		T8	1		T22	2		T52	4
valid_sources[0x71]	15887	1		T8	4		T22	1		T48	3
valid_sources[0x72]	15081	1		T8	3		T22	1		T48	1
valid_sources[0x73]	15261	1		T8	2		T22	1		T12	4
valid_sources[0x74]	15510	1		T8	1		T22	4		T48	1
valid_sources[0x75]	15042	1		T8	1		T22	3		T52	2
valid_sources[0x76]	15395	1		T8	2		T22	1		T48	4
valid_sources[0x77]	15228	1		T8	2		T25	16		T22	5
valid_sources[0x78]	15293	1		T8	2		T22	1		T30	1
valid_sources[0x79]	15596	1		T22	2		T52	1		T104	66
valid_sources[0x7a]	15408	1		T8	3		T22	1		T52	4
valid_sources[0x7b]	14972	1		T22	1		T52	1		T104	65
valid_sources[0x7c]	14940	1		T8	5		T22	1		T52	4
valid_sources[0x7d]	14657	1		T8	1		T22	2		T12	10
valid_sources[0x7e]	14931	1		T8	3		T22	3		T52	1
valid_sources[0x7f]	15306	1		T8	5		T22	2		T52	2
valid_sources[0x80]	15097	1		T8	2		T22	2		T12	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4028637

1

T5

8

T8

621

T9

10

values[0x0]

all_enables

biggest_size

2936

1

T134

121

T135

15

T138

130

values[0x1]

all_enables

biggest_size

2858

1

T134

117

T135

16

T138

105

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	29737	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	28145	1		T134	349		T73	19		T75	1427

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	37794	1		T134	85		T73	36		T75	1344
values[0x0]	9773	1		T134	126		T73	10		T75	667
values[0x1]	10315	1		T134	161		T73	11		T75	677