Unified Coverage Report :: Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_flash_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	23875761	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	7505874	1		T1	4		T2	57		T3	2967

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	27024571	1		T1	15		T2	323		T3	1423
values[0x0]	2176377	1		T1	1		T2	16		T3	1288
values[0x1]	2180687	1		T1	3		T2	25		T3	1213

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15989477	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	15392158	1		T1	8		T2	165		T3	3374

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	83925	1		T3	15		T9	2		T10	20
valid_sources[0x01]	84012	1		T3	19		T9	7		T10	24
valid_sources[0x02]	83897	1		T3	17		T9	6		T10	1
valid_sources[0x03]	84995	1		T3	36		T9	6		T26	13
valid_sources[0x04]	127177	1		T3	16		T9	10		T26	16
valid_sources[0x05]	86165	1		T3	19		T9	1		T10	14
valid_sources[0x06]	107509	1		T1	1		T3	29		T9	3
valid_sources[0x07]	122289	1		T3	21		T9	4		T17	16
valid_sources[0x08]	130697	1		T1	1		T3	2		T9	2
valid_sources[0x09]	96981	1		T3	2		T9	4		T10	4
valid_sources[0x0a]	111851	1		T3	11		T9	5		T10	11
valid_sources[0x0b]	84418	1		T3	17		T9	5		T10	4
valid_sources[0x0c]	86620	1		T3	20		T9	4		T10	19
valid_sources[0x0d]	86830	1		T3	5		T9	5		T10	15
valid_sources[0x0e]	85619	1		T3	1		T9	6		T10	9
valid_sources[0x0f]	83020	1		T1	1		T3	12		T9	4
valid_sources[0x10]	91762	1		T3	11		T9	2		T26	13
valid_sources[0x11]	84668	1		T3	15		T9	3		T10	6
valid_sources[0x12]	84136	1		T3	18		T9	7		T10	22
valid_sources[0x13]	125735	1		T3	1		T9	4		T10	6
valid_sources[0x14]	323202	1		T3	3		T9	5		T26	19
valid_sources[0x15]	84889	1		T1	1		T3	13		T9	7
valid_sources[0x16]	84352	1		T3	5		T9	2		T10	3
valid_sources[0x17]	85650	1		T3	4		T9	7		T26	17
valid_sources[0x18]	174847	1		T3	12		T9	1		T10	13
valid_sources[0x19]	101628	1		T3	1		T9	3		T26	24
valid_sources[0x1a]	84976	1		T9	2		T26	15		T70	2
valid_sources[0x1b]	84705	1		T3	37		T9	5		T26	16
valid_sources[0x1c]	85501	1		T3	19		T9	4		T10	3
valid_sources[0x1d]	85763	1		T3	1		T9	7		T10	10
valid_sources[0x1e]	84831	1		T3	20		T9	4		T17	16
valid_sources[0x1f]	86150	1		T3	30		T9	3		T10	4
valid_sources[0x20]	87515	1		T3	31		T9	3		T10	41
valid_sources[0x21]	84349	1		T3	15		T9	4		T10	31
valid_sources[0x22]	84279	1		T3	12		T9	5		T10	17
valid_sources[0x23]	87491	1		T3	8		T9	3		T10	7
valid_sources[0x24]	84072	1		T3	15		T9	5		T10	4
valid_sources[0x25]	84561	1		T3	14		T9	7		T10	4
valid_sources[0x26]	85397	1		T3	27		T9	6		T10	6
valid_sources[0x27]	102648	1		T3	13		T9	3		T10	11
valid_sources[0x28]	85841	1		T3	21		T9	1		T10	8
valid_sources[0x29]	85237	1		T3	25		T9	4		T10	19
valid_sources[0x2a]	84297	1		T3	15		T10	3		T26	17
valid_sources[0x2b]	157479	1		T1	1		T3	12		T9	6
valid_sources[0x2c]	85198	1		T3	8		T9	11		T10	5
valid_sources[0x2d]	103879	1		T3	27		T9	7		T26	25
valid_sources[0x2e]	117632	1		T3	42		T9	6		T10	7
valid_sources[0x2f]	85343	1		T3	3		T9	6		T10	18
valid_sources[0x30]	84727	1		T3	33		T9	4		T10	10
valid_sources[0x31]	83890	1		T3	15		T9	10		T26	17
valid_sources[0x32]	133014	1		T3	6		T9	5		T10	5
valid_sources[0x33]	84806	1		T3	12		T9	4		T10	36
valid_sources[0x34]	84675	1		T3	32		T9	5		T10	9
valid_sources[0x35]	84850	1		T3	20		T9	4		T10	28
valid_sources[0x36]	84621	1		T3	22		T9	7		T10	23
valid_sources[0x37]	109566	1		T3	3		T9	4		T26	22
valid_sources[0x38]	85338	1		T3	2		T9	3		T10	2
valid_sources[0x39]	84282	1		T3	29		T9	5		T10	15
valid_sources[0x3a]	84384	1		T1	1		T3	15		T9	5
valid_sources[0x3b]	102462	1		T3	4		T9	4		T26	20
valid_sources[0x3c]	84146	1		T3	27		T9	7		T10	19
valid_sources[0x3d]	86609	1		T3	6		T9	2		T10	2
valid_sources[0x3e]	121699	1		T3	35		T9	5		T10	21
valid_sources[0x3f]	104872	1		T3	5		T9	5		T10	1
valid_sources[0x40]	114764	1		T3	6		T9	8		T10	5
valid_sources[0x41]	392259	1		T3	11		T9	3		T26	15
valid_sources[0x42]	84104	1		T3	2		T9	3		T10	1
valid_sources[0x43]	125989	1		T3	33		T9	4		T26	16
valid_sources[0x44]	85254	1		T3	12		T9	6		T17	11
valid_sources[0x45]	197869	1		T3	32		T9	1		T10	7
valid_sources[0x46]	84292	1		T3	23		T9	4		T10	20
valid_sources[0x47]	86666	1		T3	45		T9	7		T10	16
valid_sources[0x48]	85862	1		T3	19		T9	7		T10	28
valid_sources[0x49]	83968	1		T3	7		T9	5		T10	1
valid_sources[0x4a]	123202	1		T3	13		T9	6		T10	10
valid_sources[0x4b]	85730	1		T1	1		T3	16		T9	6
valid_sources[0x4c]	83669	1		T3	8		T9	5		T17	2
valid_sources[0x4d]	450676	1		T3	7		T9	1		T10	9
valid_sources[0x4e]	85093	1		T3	13		T9	8		T10	9
valid_sources[0x4f]	85254	1		T3	2		T9	8		T10	13
valid_sources[0x50]	86659	1		T3	18		T9	5		T10	5
valid_sources[0x51]	107711	1		T3	20		T9	5		T26	9
valid_sources[0x52]	83651	1		T3	8		T9	6		T10	23
valid_sources[0x53]	84584	1		T3	13		T9	3		T10	6
valid_sources[0x54]	86280	1		T3	21		T9	3		T10	8
valid_sources[0x55]	148344	1		T3	3		T9	7		T17	10
valid_sources[0x56]	110930	1		T3	31		T9	3		T10	6
valid_sources[0x57]	84899	1		T3	6		T9	5		T26	19
valid_sources[0x58]	102699	1		T3	8		T9	4		T10	10
valid_sources[0x59]	84127	1		T3	18		T9	9		T10	4
valid_sources[0x5a]	86224	1		T3	22		T9	11		T10	23
valid_sources[0x5b]	141910	1		T3	23		T9	5		T10	12
valid_sources[0x5c]	105669	1		T3	42		T9	8		T10	11
valid_sources[0x5d]	109748	1		T3	59		T9	3		T10	7
valid_sources[0x5e]	84455	1		T3	47		T9	7		T10	2
valid_sources[0x5f]	86023	1		T3	18		T9	4		T10	12
valid_sources[0x60]	134034	1		T3	14		T9	4		T10	3
valid_sources[0x61]	85854	1		T3	14		T9	6		T10	12
valid_sources[0x62]	84342	1		T3	25		T9	8		T26	14
valid_sources[0x63]	220211	1		T3	34		T9	7		T10	3
valid_sources[0x64]	84865	1		T3	15		T9	4		T10	4
valid_sources[0x65]	83906	1		T3	6		T9	5		T10	6
valid_sources[0x66]	84172	1		T3	5		T9	6		T10	10
valid_sources[0x67]	85029	1		T3	15		T9	3		T10	7
valid_sources[0x68]	84776	1		T3	29		T9	7		T10	29
valid_sources[0x69]	85667	1		T3	32		T9	5		T10	1
valid_sources[0x6a]	105472	1		T3	19		T9	12		T17	7
valid_sources[0x6b]	86394	1		T1	1		T3	6		T9	4
valid_sources[0x6c]	83911	1		T3	5		T9	7		T26	12
valid_sources[0x6d]	84071	1		T3	28		T9	5		T10	10
valid_sources[0x6e]	184620	1		T2	364		T9	7		T10	11
valid_sources[0x6f]	122634	1		T3	27		T9	9		T10	8
valid_sources[0x70]	94175	1		T3	12		T9	5		T10	11
valid_sources[0x71]	84123	1		T3	18		T9	5		T10	6
valid_sources[0x72]	84069	1		T3	9		T9	5		T10	22
valid_sources[0x73]	103361	1		T1	2		T3	9		T9	5
valid_sources[0x74]	131912	1		T3	11		T9	6		T10	13
valid_sources[0x75]	105885	1		T3	19		T9	3		T10	3
valid_sources[0x76]	85522	1		T3	20		T9	7		T10	39
valid_sources[0x77]	83557	1		T3	23		T9	8		T10	10
valid_sources[0x78]	84313	1		T3	21		T9	7		T10	5
valid_sources[0x79]	153122	1		T3	10		T9	8		T10	23
valid_sources[0x7a]	85100	1		T3	18		T9	9		T26	23
valid_sources[0x7b]	83745	1		T3	9		T9	4		T26	20
valid_sources[0x7c]	84761	1		T3	7		T9	7		T10	2
valid_sources[0x7d]	100459	1		T1	1		T3	11		T9	1
valid_sources[0x7e]	85601	1		T3	5		T9	8		T10	2
valid_sources[0x7f]	83750	1		T3	37		T9	5		T10	26
valid_sources[0x80]	83653	1		T3	23		T9	2		T26	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

3816356

1

T2

26

T3

672

T15

6

values[0x0]

all_enables

biggest_size

1937657

1

T1

1

T2

13

T3

1255

values[0x1]

all_enables

biggest_size

1751861

1

T1

3

T2

18

T3

1040

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1774	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	4028920	1		T1	10		T3	643		T10	232

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4024074	1		T1	10		T3	643		T10	232
values[0x0]	2677	1		T77	143		T79	29		T134	57
values[0x1]	3943	1		T77	179		T79	23		T134	85

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	698	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	4029996	1		T1	10		T3	643		T10	232

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	15753	1		T3	2		T67	82		T55	75
valid_sources[0x01]	14918	1		T3	4		T11	1		T67	85
valid_sources[0x02]	15253	1		T3	3		T11	1		T67	62
valid_sources[0x03]	15668	1		T10	2		T67	79		T55	58
valid_sources[0x04]	15240	1		T3	3		T67	33		T59	1
valid_sources[0x05]	15195	1		T3	5		T10	1		T67	49
valid_sources[0x06]	15111	1		T67	42		T55	66		T62	3
valid_sources[0x07]	14976	1		T10	4		T67	74		T55	77
valid_sources[0x08]	15245	1		T3	1		T10	1		T67	117
valid_sources[0x09]	14903	1		T3	2		T10	1		T67	88
valid_sources[0x0a]	14817	1		T10	1		T67	89		T55	82
valid_sources[0x0b]	15101	1		T3	1		T11	1		T67	38
valid_sources[0x0c]	15040	1		T3	3		T10	1		T67	75
valid_sources[0x0d]	14899	1		T3	3		T67	42		T59	1
valid_sources[0x0e]	15279	1		T3	4		T10	1		T67	78
valid_sources[0x0f]	15440	1		T3	1		T67	66		T59	1
valid_sources[0x10]	15188	1		T3	2		T10	1		T67	76
valid_sources[0x11]	15034	1		T3	1		T10	1		T11	1
valid_sources[0x12]	15273	1		T3	2		T11	1		T67	91
valid_sources[0x13]	15082	1		T3	1		T67	83		T59	2
valid_sources[0x14]	15037	1		T3	1		T67	66		T59	1
valid_sources[0x15]	15494	1		T3	1		T10	2		T67	41
valid_sources[0x16]	14964	1		T3	4		T67	57		T59	1
valid_sources[0x17]	15512	1		T10	1		T67	71		T59	1
valid_sources[0x18]	15119	1		T3	2		T10	1		T67	67
valid_sources[0x19]	147666	1		T3	2		T67	79		T55	58
valid_sources[0x1a]	15250	1		T3	9		T10	1		T11	1
valid_sources[0x1b]	15173	1		T3	3		T67	33		T55	52
valid_sources[0x1c]	15146	1		T11	1		T67	40		T59	1
valid_sources[0x1d]	14983	1		T3	1		T67	60		T55	60
valid_sources[0x1e]	15118	1		T3	4		T67	76		T59	1
valid_sources[0x1f]	14951	1		T3	1		T10	2		T11	1
valid_sources[0x20]	15148	1		T67	100		T59	3		T55	70
valid_sources[0x21]	14930	1		T10	1		T11	1		T67	83
valid_sources[0x22]	14921	1		T3	4		T10	1		T67	49
valid_sources[0x23]	15350	1		T3	2		T67	88		T55	50
valid_sources[0x24]	15108	1		T3	4		T67	61		T59	2
valid_sources[0x25]	14887	1		T3	4		T10	2		T11	2
valid_sources[0x26]	15622	1		T3	3		T67	22		T55	76
valid_sources[0x27]	15279	1		T3	3		T67	64		T55	75
valid_sources[0x28]	15111	1		T3	3		T10	2		T67	64
valid_sources[0x29]	14923	1		T3	1		T10	2		T67	43
valid_sources[0x2a]	14800	1		T3	4		T10	1		T11	2
valid_sources[0x2b]	15221	1		T10	2		T11	1		T67	85
valid_sources[0x2c]	14873	1		T67	38		T55	81		T63	59
valid_sources[0x2d]	15501	1		T3	2		T10	1		T67	63
valid_sources[0x2e]	14901	1		T3	1		T10	2		T67	38
valid_sources[0x2f]	15732	1		T3	3		T11	1		T67	105
valid_sources[0x30]	15253	1		T3	1		T67	38		T59	3
valid_sources[0x31]	15031	1		T3	4		T67	90		T55	63
valid_sources[0x32]	15242	1		T3	5		T10	5		T11	1
valid_sources[0x33]	15111	1		T3	3		T67	51		T5	3
valid_sources[0x34]	14776	1		T3	3		T10	2		T20	6
valid_sources[0x35]	15258	1		T3	4		T10	1		T67	50
valid_sources[0x36]	15244	1		T3	2		T10	1		T11	1
valid_sources[0x37]	15482	1		T3	4		T10	5		T67	77
valid_sources[0x38]	15341	1		T10	3		T67	22		T59	1
valid_sources[0x39]	14832	1		T3	3		T67	27		T55	40
valid_sources[0x3a]	14693	1		T3	3		T67	11		T55	52
valid_sources[0x3b]	15588	1		T3	4		T11	1		T67	36
valid_sources[0x3c]	15609	1		T10	1		T67	51		T55	56
valid_sources[0x3d]	15708	1		T3	5		T10	1		T20	1
valid_sources[0x3e]	15393	1		T3	3		T10	3		T67	47
valid_sources[0x3f]	14945	1		T3	4		T10	1		T67	55
valid_sources[0x40]	15552	1		T3	7		T67	52		T55	57
valid_sources[0x41]	15145	1		T3	2		T67	50		T59	1
valid_sources[0x42]	15364	1		T3	2		T67	95		T59	1
valid_sources[0x43]	15410	1		T3	3		T10	1		T67	79
valid_sources[0x44]	15650	1		T3	3		T10	1		T67	78
valid_sources[0x45]	15226	1		T3	3		T67	39		T55	43
valid_sources[0x46]	15597	1		T3	4		T10	3		T67	72
valid_sources[0x47]	15800	1		T67	77		T59	1		T55	69
valid_sources[0x48]	14769	1		T67	43		T55	72		T63	87
valid_sources[0x49]	15571	1		T3	1		T67	53		T55	70
valid_sources[0x4a]	15092	1		T3	3		T10	2		T11	1
valid_sources[0x4b]	15750	1		T3	1		T10	1		T67	81
valid_sources[0x4c]	15875	1		T3	4		T20	13		T67	67
valid_sources[0x4d]	14506	1		T3	5		T10	1		T67	72
valid_sources[0x4e]	14996	1		T3	2		T67	66		T55	59
valid_sources[0x4f]	15135	1		T3	3		T11	1		T67	90
valid_sources[0x50]	15735	1		T3	1		T10	1		T67	71
valid_sources[0x51]	15080	1		T11	1		T67	105		T55	71
valid_sources[0x52]	15477	1		T11	1		T67	99		T59	1
valid_sources[0x53]	15032	1		T10	4		T67	95		T55	71
valid_sources[0x54]	15825	1		T3	4		T10	2		T67	109
valid_sources[0x55]	15411	1		T3	2		T11	2		T67	41
valid_sources[0x56]	14974	1		T3	2		T10	1		T67	42
valid_sources[0x57]	14818	1		T3	4		T67	88		T59	1
valid_sources[0x58]	15618	1		T3	3		T10	3		T67	63
valid_sources[0x59]	15130	1		T3	2		T10	2		T67	49
valid_sources[0x5a]	15127	1		T3	3		T67	39		T55	77
valid_sources[0x5b]	14912	1		T3	1		T67	43		T55	80
valid_sources[0x5c]	15806	1		T3	1		T10	2		T67	44
valid_sources[0x5d]	15076	1		T67	116		T59	1		T55	57
valid_sources[0x5e]	14935	1		T3	2		T67	48		T59	1
valid_sources[0x5f]	15235	1		T3	5		T11	1		T67	70
valid_sources[0x60]	15742	1		T3	4		T10	1		T11	1
valid_sources[0x61]	15534	1		T3	1		T10	1		T67	78
valid_sources[0x62]	14763	1		T3	4		T10	1		T67	52
valid_sources[0x63]	15434	1		T3	1		T10	3		T67	104
valid_sources[0x64]	14728	1		T3	5		T10	1		T67	66
valid_sources[0x65]	14705	1		T3	4		T67	68		T55	70
valid_sources[0x66]	15364	1		T3	3		T67	46		T55	61
valid_sources[0x67]	14969	1		T3	4		T67	51		T59	1
valid_sources[0x68]	15227	1		T3	5		T67	80		T55	76
valid_sources[0x69]	14818	1		T3	3		T67	37		T55	74
valid_sources[0x6a]	15162	1		T67	79		T59	3		T55	80
valid_sources[0x6b]	15113	1		T3	3		T10	1		T67	60
valid_sources[0x6c]	15219	1		T3	1		T10	1		T11	1
valid_sources[0x6d]	14964	1		T3	4		T10	2		T67	54
valid_sources[0x6e]	15383	1		T3	6		T67	61		T55	56
valid_sources[0x6f]	15444	1		T3	1		T10	2		T67	96
valid_sources[0x70]	14945	1		T3	2		T67	72		T59	3
valid_sources[0x71]	14810	1		T3	3		T10	2		T67	87
valid_sources[0x72]	15345	1		T3	1		T67	46		T59	1
valid_sources[0x73]	15162	1		T3	2		T10	3		T67	57
valid_sources[0x74]	15114	1		T3	6		T20	5		T67	79
valid_sources[0x75]	16009	1		T3	1		T20	6		T67	56
valid_sources[0x76]	15260	1		T3	5		T10	1		T11	1
valid_sources[0x77]	15590	1		T3	2		T10	2		T11	1
valid_sources[0x78]	15018	1		T10	1		T67	83		T59	1
valid_sources[0x79]	15079	1		T3	2		T10	2		T11	1
valid_sources[0x7a]	15506	1		T3	3		T10	2		T67	64
valid_sources[0x7b]	15896	1		T3	1		T10	2		T67	58
valid_sources[0x7c]	15024	1		T3	2		T10	1		T67	55
valid_sources[0x7d]	14947	1		T3	5		T67	86		T55	64
valid_sources[0x7e]	15915	1		T3	7		T20	5		T67	55
valid_sources[0x7f]	15105	1		T3	2		T10	1		T67	51
valid_sources[0x80]	15355	1		T3	6		T67	68		T55	68

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4023945

1

T1

10

T3

643

T10

232

values[0x0]

all_enables

biggest_size

2503

1

T77

132

T79

29

T134

54

values[0x1]

all_enables

biggest_size

2472

1

T77

103

T79

22

T134

46

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34885	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	34441	1		T77	210		T78	14		T79	66

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	44293	1		T77	55		T78	57		T79	57
values[0x0]	12050	1		T77	82		T78	9		T79	17
values[0x1]	12983	1		T77	120		T78	12		T79	25

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25039	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	44287	1		T77	242		T78	38		T79	75