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Summary for Variable cp_size

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 1 0 1 100.00


User Defined Bins for cp_size

Excluded/Illegal bins
NAMECOUNTSTATUS
others 21295 Excluded


Covered bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
biggest_size 36587 1 T134 358 T73 33 T75 1701



Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 166 1 T134 3 T75 7 T138 1
valid_sources[0x01] 157 1 T134 1 T73 1 T75 12
valid_sources[0x02] 181 1 T134 5 T75 9 T138 1
valid_sources[0x03] 186 1 T73 2 T75 11 T135 1
valid_sources[0x04] 234 1 T73 1 T75 19 T135 1
valid_sources[0x05] 186 1 T134 1 T75 13 T135 1
valid_sources[0x06] 336 1 T134 2 T75 8 T135 1
valid_sources[0x07] 145 1 T75 10 T135 1 T136 1
valid_sources[0x08] 202 1 T134 1 T75 17 T135 1
valid_sources[0x09] 177 1 T134 2 T75 10 T135 1
valid_sources[0x0a] 152 1 T134 4 T75 17 T138 1
valid_sources[0x0b] 180 1 T134 6 T75 7 T313 8
valid_sources[0x0c] 542 1 T134 2 T75 10 T135 3
valid_sources[0x0d] 281 1 T134 4 T75 15 T135 1
valid_sources[0x0e] 225 1 T75 18 T135 1 T138 6
valid_sources[0x0f] 197 1 T134 3 T75 5 T138 2
valid_sources[0x10] 180 1 T134 4 T75 12 T250 1
valid_sources[0x11] 241 1 T134 2 T73 1 T75 6
valid_sources[0x12] 334 1 T134 4 T75 15 T135 2
valid_sources[0x13] 202 1 T134 1 T75 11 T313 6
valid_sources[0x14] 194 1 T75 12 T138 1 T270 14
valid_sources[0x15] 312 1 T134 1 T73 1 T75 9
valid_sources[0x16] 165 1 T134 2 T75 8 T135 1
valid_sources[0x17] 242 1 T134 5 T75 8 T138 1
valid_sources[0x18] 371 1 T134 1 T75 9 T135 1
valid_sources[0x19] 233 1 T134 1 T75 11 T135 1
valid_sources[0x1a] 936 1 T75 14 T135 1 T214 9
valid_sources[0x1b] 246 1 T134 5 T75 10 T135 1
valid_sources[0x1c] 208 1 T73 1 T75 6 T138 2
valid_sources[0x1d] 262 1 T134 2 T75 8 T135 3
valid_sources[0x1e] 140 1 T134 1 T75 5 T138 3
valid_sources[0x1f] 200 1 T75 15 T135 2 T138 1
valid_sources[0x20] 146 1 T134 1 T75 8 T135 2
valid_sources[0x21] 188 1 T134 1 T75 8 T138 1
valid_sources[0x22] 152 1 T134 1 T75 5 T135 3
valid_sources[0x23] 143 1 T75 13 T135 1 T136 1
valid_sources[0x24] 221 1 T134 3 T75 9 T135 1
valid_sources[0x25] 219 1 T75 12 T138 2 T313 2
valid_sources[0x26] 158 1 T134 4 T75 13 T214 5
valid_sources[0x27] 287 1 T134 1 T75 7 T138 1
valid_sources[0x28] 187 1 T134 1 T75 12 T135 3
valid_sources[0x29] 311 1 T134 1 T75 8 T270 21
valid_sources[0x2a] 209 1 T134 1 T75 12 T135 1
valid_sources[0x2b] 153 1 T75 14 T135 1 T136 3
valid_sources[0x2c] 166 1 T134 3 T75 8 T135 1
valid_sources[0x2d] 188 1 T134 2 T75 9 T136 1
valid_sources[0x2e] 169 1 T75 8 T135 1 T138 1
valid_sources[0x2f] 196 1 T134 2 T75 11 T214 1
valid_sources[0x30] 229 1 T134 2 T73 1 T75 22
valid_sources[0x31] 123 1 T134 2 T75 9 T135 1
valid_sources[0x32] 213 1 T134 1 T73 1 T75 10
valid_sources[0x33] 231 1 T73 1 T75 9 T135 1
valid_sources[0x34] 188 1 T75 13 T135 3 T138 2
valid_sources[0x35] 227 1 T134 1 T75 12 T135 4
valid_sources[0x36] 227 1 T134 2 T75 11 T135 1
valid_sources[0x37] 189 1 T75 9 T270 14 T313 12
valid_sources[0x38] 219 1 T134 1 T75 6 T135 1
valid_sources[0x39] 265 1 T75 15 T313 11 T137 2
valid_sources[0x3a] 272 1 T134 3 T75 11 T135 1
valid_sources[0x3b] 156 1 T134 1 T75 9 T135 1
valid_sources[0x3c] 200 1 T134 2 T75 9 T135 2
valid_sources[0x3d] 191 1 T75 7 T135 1 T138 3
valid_sources[0x3e] 271 1 T75 16 T135 1 T270 14
valid_sources[0x3f] 231 1 T134 1 T75 7 T138 1
valid_sources[0x40] 315 1 T134 1 T73 1 T75 9
valid_sources[0x41] 186 1 T134 2 T75 9 T138 3
valid_sources[0x42] 146 1 T75 8 T135 1 T138 3
valid_sources[0x43] 239 1 T134 1 T75 12 T135 1
valid_sources[0x44] 175 1 T75 6 T138 2 T270 14
valid_sources[0x45] 670 1 T134 1 T75 16 T135 2
valid_sources[0x46] 1471 1 T134 3 T73 1 T75 6
valid_sources[0x47] 172 1 T134 4 T75 11 T135 1
valid_sources[0x48] 192 1 T134 1 T75 11 T135 4
valid_sources[0x49] 229 1 T134 2 T73 1 T75 13
valid_sources[0x4a] 253 1 T134 3 T75 7 T270 14
valid_sources[0x4b] 192 1 T134 3 T75 7 T135 1
valid_sources[0x4c] 184 1 T134 1 T73 1 T75 9
valid_sources[0x4d] 166 1 T134 1 T75 9 T250 1
valid_sources[0x4e] 184 1 T134 1 T75 10 T135 1
valid_sources[0x4f] 196 1 T75 8 T138 2 T214 1
valid_sources[0x50] 181 1 T134 1 T75 10 T135 2
valid_sources[0x51] 191 1 T134 2 T75 7 T214 6
valid_sources[0x52] 191 1 T134 1 T75 14 T138 1
valid_sources[0x53] 174 1 T75 12 T135 2 T138 2
valid_sources[0x54] 167 1 T134 3 T75 15 T135 2
valid_sources[0x55] 168 1 T134 3 T75 6 T270 28
valid_sources[0x56] 162 1 T75 18 T135 2 T138 1
valid_sources[0x57] 214 1 T73 1 T75 10 T250 1
valid_sources[0x58] 218 1 T75 10 T135 1 T138 1
valid_sources[0x59] 169 1 T134 2 T75 16 T138 1
valid_sources[0x5a] 176 1 T73 1 T75 20 T269 2
valid_sources[0x5b] 185 1 T134 2 T75 7 T135 1
valid_sources[0x5c] 120 1 T134 1 T75 4 T313 7
valid_sources[0x5d] 220 1 T75 10 T135 1 T270 14
valid_sources[0x5e] 166 1 T75 13 T135 1 T138 2
valid_sources[0x5f] 189 1 T134 1 T75 18 T135 1
valid_sources[0x60] 322 1 T75 16 T135 2 T270 14
valid_sources[0x61] 221 1 T134 1 T75 6 T138 3
valid_sources[0x62] 186 1 T134 4 T75 5 T138 1
valid_sources[0x63] 119 1 T134 2 T75 12 T135 1
valid_sources[0x64] 219 1 T73 2 T75 8 T138 1
valid_sources[0x65] 249 1 T75 11 T270 22 T313 7
valid_sources[0x66] 185 1 T134 3 T75 14 T135 1
valid_sources[0x67] 146 1 T134 2 T75 7 T250 1
valid_sources[0x68] 150 1 T134 2 T75 8 T138 3
valid_sources[0x69] 122 1 T134 2 T75 11 T135 1
valid_sources[0x6a] 216 1 T75 15 T135 1 T138 1
valid_sources[0x6b] 229 1 T134 4 T75 11 T138 2
valid_sources[0x6c] 141 1 T134 1 T75 12 T250 2
valid_sources[0x6d] 131 1 T134 3 T75 9 T138 1
valid_sources[0x6e] 204 1 T75 16 T135 4 T250 1
valid_sources[0x6f] 187 1 T75 9 T136 1 T313 8
valid_sources[0x70] 184 1 T75 10 T135 3 T313 5
valid_sources[0x71] 161 1 T134 1 T73 1 T75 4
valid_sources[0x72] 195 1 T134 1 T75 10 T135 2
valid_sources[0x73] 249 1 T75 15 T270 36 T313 4
valid_sources[0x74] 137 1 T134 1 T75 7 T138 1
valid_sources[0x75] 222 1 T134 1 T75 8 T135 2
valid_sources[0x76] 184 1 T134 1 T75 5 T135 1
valid_sources[0x77] 224 1 T134 1 T75 3 T135 2
valid_sources[0x78] 188 1 T134 1 T73 1 T75 13
valid_sources[0x79] 237 1 T134 2 T73 3 T75 10
valid_sources[0x7a] 172 1 T75 13 T136 2 T313 1
valid_sources[0x7b] 119 1 T134 3 T75 14 T138 3
valid_sources[0x7c] 171 1 T134 2 T75 11 T135 2
valid_sources[0x7d] 154 1 T134 1 T75 8 T270 36
valid_sources[0x7e] 167 1 T134 1 T75 14 T250 1
valid_sources[0x7f] 174 1 T134 2 T75 10 T270 21
valid_sources[0x80] 152 1 T134 3 T75 8 T250 2



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 14863 1 T134 83 T73 6 T75 649
values[0x0] all_enables biggest_size 7327 1 T134 124 T73 6 T75 461
values[0x1] all_enables biggest_size 5955 1 T134 142 T73 7 T75 317

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%