dashboard | hierarchy | modlist | groups | tests | asserts


Summary for Variable cp_source

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 129 0 129 100.00


User Defined Bins for cp_source

Bins
NAMECOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
valid_sources[0x00] 264 1 T78 6 T79 1 T134 2
valid_sources[0x01] 273 1 T134 1 T80 10 T232 5
valid_sources[0x02] 283 1 T134 6 T80 12 T232 17
valid_sources[0x03] 253 1 T78 1 T79 1 T134 3
valid_sources[0x04] 258 1 T77 18 T134 1 T80 18
valid_sources[0x05] 220 1 T134 1 T80 4 T232 3
valid_sources[0x06] 244 1 T134 1 T80 7 T232 6
valid_sources[0x07] 323 1 T78 2 T134 2 T80 14
valid_sources[0x08] 242 1 T77 2 T134 1 T80 12
valid_sources[0x09] 207 1 T79 1 T134 1 T80 8
valid_sources[0x0a] 262 1 T79 1 T134 3 T80 8
valid_sources[0x0b] 235 1 T134 4 T80 10 T232 12
valid_sources[0x0c] 243 1 T78 10 T80 15 T263 2
valid_sources[0x0d] 238 1 T78 4 T79 1 T134 3
valid_sources[0x0e] 294 1 T80 10 T263 1 T232 3
valid_sources[0x0f] 248 1 T79 1 T134 1 T80 10
valid_sources[0x10] 312 1 T80 7 T232 8 T266 14
valid_sources[0x11] 204 1 T77 10 T79 1 T134 1
valid_sources[0x12] 219 1 T80 22 T232 9 T266 5
valid_sources[0x13] 322 1 T134 3 T80 12 T232 7
valid_sources[0x14] 290 1 T134 1 T80 10 T232 10
valid_sources[0x15] 204 1 T134 1 T80 11 T232 9
valid_sources[0x16] 385 1 T79 2 T80 11 T232 23
valid_sources[0x17] 225 1 T134 4 T80 4 T232 7
valid_sources[0x18] 304 1 T80 10 T263 4 T232 8
valid_sources[0x19] 379 1 T77 1 T79 1 T80 10
valid_sources[0x1a] 273 1 T79 1 T134 1 T80 4
valid_sources[0x1b] 250 1 T134 2 T80 6 T232 7
valid_sources[0x1c] 238 1 T80 12 T232 9 T266 12
valid_sources[0x1d] 326 1 T134 1 T80 10 T232 12
valid_sources[0x1e] 263 1 T79 1 T134 4 T80 6
valid_sources[0x1f] 219 1 T134 2 T80 6 T232 3
valid_sources[0x20] 236 1 T77 1 T80 14 T232 10
valid_sources[0x21] 383 1 T77 11 T79 2 T134 1
valid_sources[0x22] 250 1 T80 13 T263 9 T232 8
valid_sources[0x23] 430 1 T80 16 T232 1 T266 4
valid_sources[0x24] 223 1 T134 1 T80 10 T232 15
valid_sources[0x25] 215 1 T80 7 T232 10 T266 12
valid_sources[0x26] 384 1 T79 1 T80 12 T232 4
valid_sources[0x27] 237 1 T78 1 T79 1 T134 1
valid_sources[0x28] 226 1 T80 13 T232 8 T266 11
valid_sources[0x29] 217 1 T134 1 T80 14 T232 6
valid_sources[0x2a] 211 1 T79 1 T80 8 T232 8
valid_sources[0x2b] 209 1 T80 8 T232 4 T266 14
valid_sources[0x2c] 341 1 T134 1 T80 9 T232 6
valid_sources[0x2d] 402 1 T134 3 T80 14 T263 2
valid_sources[0x2e] 433 1 T77 24 T134 2 T80 8
valid_sources[0x2f] 226 1 T80 2 T232 12 T266 15
valid_sources[0x30] 202 1 T79 1 T80 12 T232 5
valid_sources[0x31] 287 1 T79 1 T80 18 T232 11
valid_sources[0x32] 247 1 T80 6 T232 6 T266 13
valid_sources[0x33] 249 1 T134 1 T80 11 T232 4
valid_sources[0x34] 300 1 T80 11 T232 8 T266 5
valid_sources[0x35] 303 1 T79 1 T80 14 T263 2
valid_sources[0x36] 192 1 T134 1 T80 20 T232 1
valid_sources[0x37] 260 1 T77 10 T80 17 T232 5
valid_sources[0x38] 226 1 T80 10 T232 7 T266 11
valid_sources[0x39] 337 1 T78 1 T134 2 T80 7
valid_sources[0x3a] 251 1 T134 5 T80 13 T232 7
valid_sources[0x3b] 327 1 T134 1 T80 8 T232 6
valid_sources[0x3c] 273 1 T134 2 T80 8 T232 6
valid_sources[0x3d] 303 1 T77 2 T80 9 T232 12
valid_sources[0x3e] 272 1 T80 11 T232 3 T266 18
valid_sources[0x3f] 257 1 T80 14 T232 11 T266 13
valid_sources[0x40] 224 1 T134 2 T80 9 T232 6
valid_sources[0x41] 357 1 T77 27 T80 10 T232 5
valid_sources[0x42] 199 1 T79 1 T134 2 T80 13
valid_sources[0x43] 237 1 T78 7 T134 4 T80 5
valid_sources[0x44] 227 1 T77 6 T134 1 T80 7
valid_sources[0x45] 266 1 T134 1 T80 14 T232 12
valid_sources[0x46] 174 1 T79 1 T134 1 T80 7
valid_sources[0x47] 333 1 T134 1 T80 15 T232 6
valid_sources[0x48] 220 1 T134 4 T80 4 T232 4
valid_sources[0x49] 298 1 T134 2 T80 6 T232 20
valid_sources[0x4a] 390 1 T79 1 T134 1 T80 11
valid_sources[0x4b] 262 1 T134 1 T80 5 T232 5
valid_sources[0x4c] 232 1 T78 4 T79 1 T134 1
valid_sources[0x4d] 206 1 T80 9 T232 16 T266 8
valid_sources[0x4e] 291 1 T79 1 T134 1 T80 23
valid_sources[0x4f] 203 1 T77 20 T79 1 T134 5
valid_sources[0x50] 325 1 T134 2 T80 5 T232 8
valid_sources[0x51] 302 1 T80 3 T232 8 T266 7
valid_sources[0x52] 278 1 T134 1 T80 9 T232 9
valid_sources[0x53] 213 1 T79 1 T134 4 T80 6
valid_sources[0x54] 203 1 T134 3 T80 16 T232 7
valid_sources[0x55] 224 1 T79 2 T80 6 T232 9
valid_sources[0x56] 371 1 T134 1 T80 10 T232 11
valid_sources[0x57] 287 1 T79 1 T134 1 T80 10
valid_sources[0x58] 272 1 T80 8 T232 10 T266 4
valid_sources[0x59] 208 1 T79 1 T134 2 T80 7
valid_sources[0x5a] 247 1 T134 3 T80 20 T232 10
valid_sources[0x5b] 277 1 T80 10 T232 15 T266 11
valid_sources[0x5c] 239 1 T80 21 T232 12 T266 2
valid_sources[0x5d] 364 1 T134 1 T80 9 T232 3
valid_sources[0x5e] 238 1 T80 9 T232 6 T266 8
valid_sources[0x5f] 287 1 T134 2 T80 12 T232 9
valid_sources[0x60] 322 1 T80 11 T232 9 T266 6
valid_sources[0x61] 298 1 T134 2 T80 26 T232 2
valid_sources[0x62] 239 1 T79 1 T134 1 T80 12
valid_sources[0x63] 224 1 T79 1 T134 1 T80 9
valid_sources[0x64] 252 1 T78 1 T134 2 T80 18
valid_sources[0x65] 204 1 T134 4 T80 7 T232 13
valid_sources[0x66] 239 1 T134 1 T80 12 T232 12
valid_sources[0x67] 282 1 T80 16 T232 3 T266 6
valid_sources[0x68] 276 1 T79 2 T134 3 T80 3
valid_sources[0x69] 258 1 T77 7 T80 10 T232 2
valid_sources[0x6a] 431 1 T79 3 T134 1 T80 7
valid_sources[0x6b] 277 1 T79 2 T80 13 T232 9
valid_sources[0x6c] 274 1 T79 1 T134 1 T80 12
valid_sources[0x6d] 239 1 T80 12 T263 2 T232 1
valid_sources[0x6e] 239 1 T79 1 T80 12 T232 8
valid_sources[0x6f] 247 1 T79 1 T134 2 T80 11
valid_sources[0x70] 250 1 T134 1 T80 10 T263 4
valid_sources[0x71] 401 1 T134 6 T80 10 T232 7
valid_sources[0x72] 216 1 T134 4 T80 8 T232 7
valid_sources[0x73] 350 1 T79 1 T134 1 T80 9
valid_sources[0x74] 245 1 T80 8 T232 6 T266 11
valid_sources[0x75] 235 1 T134 3 T80 11 T232 1
valid_sources[0x76] 254 1 T134 1 T80 6 T232 8
valid_sources[0x77] 176 1 T134 1 T80 14 T232 9
valid_sources[0x78] 267 1 T77 6 T79 1 T80 5
valid_sources[0x79] 223 1 T134 1 T80 5 T232 11
valid_sources[0x7a] 243 1 T80 16 T232 9 T266 9
valid_sources[0x7b] 260 1 T134 4 T80 10 T232 5
valid_sources[0x7c] 294 1 T134 1 T80 11 T232 5
valid_sources[0x7d] 263 1 T80 12 T232 5 T250 16
valid_sources[0x7e] 275 1 T78 10 T80 19 T232 3
valid_sources[0x7f] 256 1 T80 16 T232 3 T266 4
valid_sources[0x80] 237 1 T79 1 T80 10 T232 6



Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 3 0 3 100.00


Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins
cp_opcodecp_maskcp_sizeCOUNTAT LEASTTESTCOUNTTESTCOUNTTESTCOUNT
values[0x4] all_enables biggest_size 17916 1 T77 50 T78 5 T79 34
values[0x0] all_enables biggest_size 9083 1 T77 80 T78 6 T79 13
values[0x1] all_enables biggest_size 7442 1 T77 80 T78 3 T79 19

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%