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67 always_ff @(posedge clk_i or negedge rst_ni) begin
68 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
69 1/1 err_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (intg_err || reg_we_err) begin
Tests: T1 T2 T3
71 1/1 err_q <= 1'b1;
Tests: T13 T14 T15
72 end
MISSING_ELSE
73 end
74
75 // integrity error output is permanent and should be used for alert generation
76 // register errors are transactional
77 1/1 assign intg_err_o = err_q | intg_err | reg_we_err;
Tests: T1 T2 T3
78
79 // outgoing integrity generation
80 tlul_pkg::tl_d2h_t tl_o_pre;
81 tlul_rsp_intg_gen #(
82 .EnableRspIntgGen(1),
83 .EnableDataIntgGen(1)
84 ) u_rsp_intg_gen (
85 .tl_i(tl_o_pre),
86 .tl_o(tl_o)
87 );
88
89 1/1 assign tl_reg_h2d = tl_i;
Tests: T1 T2 T3
90 1/1 assign tl_o_pre = tl_reg_d2h;
Tests: T1 T2 T3
91
92 tlul_adapter_reg #(
93 .RegAw(AW),
94 .RegDw(DW),
95 .EnableDataIntgGen(0)
96 ) u_reg_if (
97 .clk_i (clk_i),
98 .rst_ni (rst_ni),
99
100 .tl_i (tl_reg_h2d),
101 .tl_o (tl_reg_d2h),
102
103 .en_ifetch_i(prim_mubi_pkg::MuBi4False),
104 .intg_error_o(),
105
106 .we_o (reg_we),
107 .re_o (reg_re),
108 .addr_o (reg_addr),
109 .wdata_o (reg_wdata),
110 .be_o (reg_be),
111 .busy_i (reg_busy),
112 .rdata_i (reg_rdata),
113 .error_i (reg_error)
114 );
115
116 // cdc oversampling signals
117
118 1/1 assign reg_rdata = reg_rdata_next ;
Tests: T2 T5 T17
119 1/1 assign reg_error = addrmiss | wr_err | intg_err;
Tests: T134 T73 T135
120
121 // Define SW related signals
122 // Format: <reg>_<field>_{wd|we|qs}
123 // or <reg>_{wd|we|qs} if field == 1 or 0
124 logic csr0_regwen_we;
125 logic csr0_regwen_qs;
126 logic csr0_regwen_wd;
127 logic csr1_we;
128 logic [7:0] csr1_field0_qs;
129 logic [7:0] csr1_field0_wd;
130 logic [4:0] csr1_field1_qs;
131 logic [4:0] csr1_field1_wd;
132 logic csr2_we;
133 logic csr2_field0_qs;
134 logic csr2_field0_wd;
135 logic csr2_field1_qs;
136 logic csr2_field1_wd;
137 logic csr2_field2_qs;
138 logic csr2_field2_wd;
139 logic csr2_field3_qs;
140 logic csr2_field3_wd;
141 logic csr2_field4_qs;
142 logic csr2_field4_wd;
143 logic csr2_field5_qs;
144 logic csr2_field5_wd;
145 logic csr2_field6_qs;
146 logic csr2_field6_wd;
147 logic csr2_field7_qs;
148 logic csr2_field7_wd;
149 logic csr3_we;
150 logic [3:0] csr3_field0_qs;
151 logic [3:0] csr3_field0_wd;
152 logic [3:0] csr3_field1_qs;
153 logic [3:0] csr3_field1_wd;
154 logic [2:0] csr3_field2_qs;
155 logic [2:0] csr3_field2_wd;
156 logic [2:0] csr3_field3_qs;
157 logic [2:0] csr3_field3_wd;
158 logic [2:0] csr3_field4_qs;
159 logic [2:0] csr3_field4_wd;
160 logic [2:0] csr3_field5_qs;
161 logic [2:0] csr3_field5_wd;
162 logic csr3_field6_qs;
163 logic csr3_field6_wd;
164 logic [2:0] csr3_field7_qs;
165 logic [2:0] csr3_field7_wd;
166 logic [1:0] csr3_field8_qs;
167 logic [1:0] csr3_field8_wd;
168 logic [1:0] csr3_field9_qs;
169 logic [1:0] csr3_field9_wd;
170 logic csr4_we;
171 logic [2:0] csr4_field0_qs;
172 logic [2:0] csr4_field0_wd;
173 logic [2:0] csr4_field1_qs;
174 logic [2:0] csr4_field1_wd;
175 logic [2:0] csr4_field2_qs;
176 logic [2:0] csr4_field2_wd;
177 logic [2:0] csr4_field3_qs;
178 logic [2:0] csr4_field3_wd;
179 logic csr5_we;
180 logic [2:0] csr5_field0_qs;
181 logic [2:0] csr5_field0_wd;
182 logic [1:0] csr5_field1_qs;
183 logic [1:0] csr5_field1_wd;
184 logic [8:0] csr5_field2_qs;
185 logic [8:0] csr5_field2_wd;
186 logic [4:0] csr5_field3_qs;
187 logic [4:0] csr5_field3_wd;
188 logic [3:0] csr5_field4_qs;
189 logic [3:0] csr5_field4_wd;
190 logic csr6_we;
191 logic [2:0] csr6_field0_qs;
192 logic [2:0] csr6_field0_wd;
193 logic [2:0] csr6_field1_qs;
194 logic [2:0] csr6_field1_wd;
195 logic [7:0] csr6_field2_qs;
196 logic [7:0] csr6_field2_wd;
197 logic [2:0] csr6_field3_qs;
198 logic [2:0] csr6_field3_wd;
199 logic [1:0] csr6_field4_qs;
200 logic [1:0] csr6_field4_wd;
201 logic [1:0] csr6_field5_qs;
202 logic [1:0] csr6_field5_wd;
203 logic [1:0] csr6_field6_qs;
204 logic [1:0] csr6_field6_wd;
205 logic csr6_field7_qs;
206 logic csr6_field7_wd;
207 logic csr6_field8_qs;
208 logic csr6_field8_wd;
209 logic csr7_we;
210 logic [7:0] csr7_field0_qs;
211 logic [7:0] csr7_field0_wd;
212 logic [8:0] csr7_field1_qs;
213 logic [8:0] csr7_field1_wd;
214 logic csr8_we;
215 logic [31:0] csr8_qs;
216 logic [31:0] csr8_wd;
217 logic csr9_we;
218 logic [31:0] csr9_qs;
219 logic [31:0] csr9_wd;
220 logic csr10_we;
221 logic [31:0] csr10_qs;
222 logic [31:0] csr10_wd;
223 logic csr11_we;
224 logic [31:0] csr11_qs;
225 logic [31:0] csr11_wd;
226 logic csr12_we;
227 logic [9:0] csr12_qs;
228 logic [9:0] csr12_wd;
229 logic csr13_we;
230 logic [19:0] csr13_field0_qs;
231 logic [19:0] csr13_field0_wd;
232 logic csr13_field1_qs;
233 logic csr13_field1_wd;
234 logic csr14_we;
235 logic [7:0] csr14_field0_qs;
236 logic [7:0] csr14_field0_wd;
237 logic csr14_field1_qs;
238 logic csr14_field1_wd;
239 logic csr15_we;
240 logic [7:0] csr15_field0_qs;
241 logic [7:0] csr15_field0_wd;
242 logic csr15_field1_qs;
243 logic csr15_field1_wd;
244 logic csr16_we;
245 logic [7:0] csr16_field0_qs;
246 logic [7:0] csr16_field0_wd;
247 logic csr16_field1_qs;
248 logic csr16_field1_wd;
249 logic csr17_we;
250 logic [7:0] csr17_field0_qs;
251 logic [7:0] csr17_field0_wd;
252 logic csr17_field1_qs;
253 logic csr17_field1_wd;
254 logic csr18_we;
255 logic csr18_qs;
256 logic csr18_wd;
257 logic csr19_we;
258 logic csr19_qs;
259 logic csr19_wd;
260 logic csr20_we;
261 logic csr20_field0_qs;
262 logic csr20_field0_wd;
263 logic csr20_field1_qs;
264 logic csr20_field1_wd;
265 logic csr20_field2_qs;
266
267 // Register instances
268 // R[csr0_regwen]: V(False)
269 prim_subreg #(
270 .DW (1),
271 .SwAccess(prim_subreg_pkg::SwAccessW0C),
272 .RESVAL (1'h1),
273 .Mubi (1'b0)
274 ) u_csr0_regwen (
275 .clk_i (clk_i),
276 .rst_ni (rst_ni),
277
278 // from register interface
279 .we (csr0_regwen_we),
280 .wd (csr0_regwen_wd),
281
282 // from internal hardware
283 .de (1'b0),
284 .d ('0),
285
286 // to internal hardware
287 .qe (),
288 .q (),
289 .ds (),
290
291 // to register interface (read)
292 .qs (csr0_regwen_qs)
293 );
294
295
296 // R[csr1]: V(False)
297 // Create REGWEN-gated WE signal
298 logic csr1_gated_we;
299 1/1 assign csr1_gated_we = csr1_we & csr0_regwen_qs;
Tests: T1 T2 T3
300 // F[field0]: 7:0
301 prim_subreg #(
302 .DW (8),
303 .SwAccess(prim_subreg_pkg::SwAccessRW),
304 .RESVAL (8'h0),
305 .Mubi (1'b0)
306 ) u_csr1_field0 (
307 .clk_i (clk_i),
308 .rst_ni (rst_ni),
309
310 // from register interface
311 .we (csr1_gated_we),
312 .wd (csr1_field0_wd),
313
314 // from internal hardware
315 .de (1'b0),
316 .d ('0),
317
318 // to internal hardware
319 .qe (),
320 .q (reg2hw.csr1.field0.q),
321 .ds (),
322
323 // to register interface (read)
324 .qs (csr1_field0_qs)
325 );
326
327 // F[field1]: 12:8
328 prim_subreg #(
329 .DW (5),
330 .SwAccess(prim_subreg_pkg::SwAccessRW),
331 .RESVAL (5'h0),
332 .Mubi (1'b0)
333 ) u_csr1_field1 (
334 .clk_i (clk_i),
335 .rst_ni (rst_ni),
336
337 // from register interface
338 .we (csr1_gated_we),
339 .wd (csr1_field1_wd),
340
341 // from internal hardware
342 .de (1'b0),
343 .d ('0),
344
345 // to internal hardware
346 .qe (),
347 .q (reg2hw.csr1.field1.q),
348 .ds (),
349
350 // to register interface (read)
351 .qs (csr1_field1_qs)
352 );
353
354
355 // R[csr2]: V(False)
356 // F[field0]: 0:0
357 prim_subreg #(
358 .DW (1),
359 .SwAccess(prim_subreg_pkg::SwAccessW1C),
360 .RESVAL (1'h0),
361 .Mubi (1'b0)
362 ) u_csr2_field0 (
363 .clk_i (clk_i),
364 .rst_ni (rst_ni),
365
366 // from register interface
367 .we (csr2_we),
368 .wd (csr2_field0_wd),
369
370 // from internal hardware
371 .de (hw2reg.csr2.field0.de),
372 .d (hw2reg.csr2.field0.d),
373
374 // to internal hardware
375 .qe (),
376 .q (reg2hw.csr2.field0.q),
377 .ds (),
378
379 // to register interface (read)
380 .qs (csr2_field0_qs)
381 );
382
383 // F[field1]: 1:1
384 prim_subreg #(
385 .DW (1),
386 .SwAccess(prim_subreg_pkg::SwAccessW1C),
387 .RESVAL (1'h0),
388 .Mubi (1'b0)
389 ) u_csr2_field1 (
390 .clk_i (clk_i),
391 .rst_ni (rst_ni),
392
393 // from register interface
394 .we (csr2_we),
395 .wd (csr2_field1_wd),
396
397 // from internal hardware
398 .de (hw2reg.csr2.field1.de),
399 .d (hw2reg.csr2.field1.d),
400
401 // to internal hardware
402 .qe (),
403 .q (reg2hw.csr2.field1.q),
404 .ds (),
405
406 // to register interface (read)
407 .qs (csr2_field1_qs)
408 );
409
410 // F[field2]: 2:2
411 prim_subreg #(
412 .DW (1),
413 .SwAccess(prim_subreg_pkg::SwAccessW1C),
414 .RESVAL (1'h0),
415 .Mubi (1'b0)
416 ) u_csr2_field2 (
417 .clk_i (clk_i),
418 .rst_ni (rst_ni),
419
420 // from register interface
421 .we (csr2_we),
422 .wd (csr2_field2_wd),
423
424 // from internal hardware
425 .de (hw2reg.csr2.field2.de),
426 .d (hw2reg.csr2.field2.d),
427
428 // to internal hardware
429 .qe (),
430 .q (reg2hw.csr2.field2.q),
431 .ds (),
432
433 // to register interface (read)
434 .qs (csr2_field2_qs)
435 );
436
437 // F[field3]: 3:3
438 prim_subreg #(
439 .DW (1),
440 .SwAccess(prim_subreg_pkg::SwAccessRW),
441 .RESVAL (1'h0),
442 .Mubi (1'b0)
443 ) u_csr2_field3 (
444 .clk_i (clk_i),
445 .rst_ni (rst_ni),
446
447 // from register interface
448 .we (csr2_we),
449 .wd (csr2_field3_wd),
450
451 // from internal hardware
452 .de (hw2reg.csr2.field3.de),
453 .d (hw2reg.csr2.field3.d),
454
455 // to internal hardware
456 .qe (),
457 .q (reg2hw.csr2.field3.q),
458 .ds (),
459
460 // to register interface (read)
461 .qs (csr2_field3_qs)
462 );
463
464 // F[field4]: 4:4
465 prim_subreg #(
466 .DW (1),
467 .SwAccess(prim_subreg_pkg::SwAccessW1C),
468 .RESVAL (1'h0),
469 .Mubi (1'b0)
470 ) u_csr2_field4 (
471 .clk_i (clk_i),
472 .rst_ni (rst_ni),
473
474 // from register interface
475 .we (csr2_we),
476 .wd (csr2_field4_wd),
477
478 // from internal hardware
479 .de (hw2reg.csr2.field4.de),
480 .d (hw2reg.csr2.field4.d),
481
482 // to internal hardware
483 .qe (),
484 .q (reg2hw.csr2.field4.q),
485 .ds (),
486
487 // to register interface (read)
488 .qs (csr2_field4_qs)
489 );
490
491 // F[field5]: 5:5
492 prim_subreg #(
493 .DW (1),
494 .SwAccess(prim_subreg_pkg::SwAccessW1C),
495 .RESVAL (1'h0),
496 .Mubi (1'b0)
497 ) u_csr2_field5 (
498 .clk_i (clk_i),
499 .rst_ni (rst_ni),
500
501 // from register interface
502 .we (csr2_we),
503 .wd (csr2_field5_wd),
504
505 // from internal hardware
506 .de (hw2reg.csr2.field5.de),
507 .d (hw2reg.csr2.field5.d),
508
509 // to internal hardware
510 .qe (),
511 .q (reg2hw.csr2.field5.q),
512 .ds (),
513
514 // to register interface (read)
515 .qs (csr2_field5_qs)
516 );
517
518 // F[field6]: 6:6
519 prim_subreg #(
520 .DW (1),
521 .SwAccess(prim_subreg_pkg::SwAccessW1C),
522 .RESVAL (1'h0),
523 .Mubi (1'b0)
524 ) u_csr2_field6 (
525 .clk_i (clk_i),
526 .rst_ni (rst_ni),
527
528 // from register interface
529 .we (csr2_we),
530 .wd (csr2_field6_wd),
531
532 // from internal hardware
533 .de (hw2reg.csr2.field6.de),
534 .d (hw2reg.csr2.field6.d),
535
536 // to internal hardware
537 .qe (),
538 .q (reg2hw.csr2.field6.q),
539 .ds (),
540
541 // to register interface (read)
542 .qs (csr2_field6_qs)
543 );
544
545 // F[field7]: 7:7
546 prim_subreg #(
547 .DW (1),
548 .SwAccess(prim_subreg_pkg::SwAccessRW),
549 .RESVAL (1'h0),
550 .Mubi (1'b0)
551 ) u_csr2_field7 (
552 .clk_i (clk_i),
553 .rst_ni (rst_ni),
554
555 // from register interface
556 .we (csr2_we),
557 .wd (csr2_field7_wd),
558
559 // from internal hardware
560 .de (hw2reg.csr2.field7.de),
561 .d (hw2reg.csr2.field7.d),
562
563 // to internal hardware
564 .qe (),
565 .q (reg2hw.csr2.field7.q),
566 .ds (),
567
568 // to register interface (read)
569 .qs (csr2_field7_qs)
570 );
571
572
573 // R[csr3]: V(False)
574 // Create REGWEN-gated WE signal
575 logic csr3_gated_we;
576 1/1 assign csr3_gated_we = csr3_we & csr0_regwen_qs;
Tests: T1 T2 T3
577 // F[field0]: 3:0
578 prim_subreg #(
579 .DW (4),
580 .SwAccess(prim_subreg_pkg::SwAccessRW),
581 .RESVAL (4'h0),
582 .Mubi (1'b0)
583 ) u_csr3_field0 (
584 .clk_i (clk_i),
585 .rst_ni (rst_ni),
586
587 // from register interface
588 .we (csr3_gated_we),
589 .wd (csr3_field0_wd),
590
591 // from internal hardware
592 .de (1'b0),
593 .d ('0),
594
595 // to internal hardware
596 .qe (),
597 .q (reg2hw.csr3.field0.q),
598 .ds (),
599
600 // to register interface (read)
601 .qs (csr3_field0_qs)
602 );
603
604 // F[field1]: 7:4
605 prim_subreg #(
606 .DW (4),
607 .SwAccess(prim_subreg_pkg::SwAccessRW),
608 .RESVAL (4'h0),
609 .Mubi (1'b0)
610 ) u_csr3_field1 (
611 .clk_i (clk_i),
612 .rst_ni (rst_ni),
613
614 // from register interface
615 .we (csr3_gated_we),
616 .wd (csr3_field1_wd),
617
618 // from internal hardware
619 .de (1'b0),
620 .d ('0),
621
622 // to internal hardware
623 .qe (),
624 .q (reg2hw.csr3.field1.q),
625 .ds (),
626
627 // to register interface (read)
628 .qs (csr3_field1_qs)
629 );
630
631 // F[field2]: 10:8
632 prim_subreg #(
633 .DW (3),
634 .SwAccess(prim_subreg_pkg::SwAccessRW),
635 .RESVAL (3'h0),
636 .Mubi (1'b0)
637 ) u_csr3_field2 (
638 .clk_i (clk_i),
639 .rst_ni (rst_ni),
640
641 // from register interface
642 .we (csr3_gated_we),
643 .wd (csr3_field2_wd),
644
645 // from internal hardware
646 .de (1'b0),
647 .d ('0),
648
649 // to internal hardware
650 .qe (),
651 .q (reg2hw.csr3.field2.q),
652 .ds (),
653
654 // to register interface (read)
655 .qs (csr3_field2_qs)
656 );
657
658 // F[field3]: 13:11
659 prim_subreg #(
660 .DW (3),
661 .SwAccess(prim_subreg_pkg::SwAccessRW),
662 .RESVAL (3'h0),
663 .Mubi (1'b0)
664 ) u_csr3_field3 (
665 .clk_i (clk_i),
666 .rst_ni (rst_ni),
667
668 // from register interface
669 .we (csr3_gated_we),
670 .wd (csr3_field3_wd),
671
672 // from internal hardware
673 .de (1'b0),
674 .d ('0),
675
676 // to internal hardware
677 .qe (),
678 .q (reg2hw.csr3.field3.q),
679 .ds (),
680
681 // to register interface (read)
682 .qs (csr3_field3_qs)
683 );
684
685 // F[field4]: 16:14
686 prim_subreg #(
687 .DW (3),
688 .SwAccess(prim_subreg_pkg::SwAccessRW),
689 .RESVAL (3'h0),
690 .Mubi (1'b0)
691 ) u_csr3_field4 (
692 .clk_i (clk_i),
693 .rst_ni (rst_ni),
694
695 // from register interface
696 .we (csr3_gated_we),
697 .wd (csr3_field4_wd),
698
699 // from internal hardware
700 .de (1'b0),
701 .d ('0),
702
703 // to internal hardware
704 .qe (),
705 .q (reg2hw.csr3.field4.q),
706 .ds (),
707
708 // to register interface (read)
709 .qs (csr3_field4_qs)
710 );
711
712 // F[field5]: 19:17
713 prim_subreg #(
714 .DW (3),
715 .SwAccess(prim_subreg_pkg::SwAccessRW),
716 .RESVAL (3'h0),
717 .Mubi (1'b0)
718 ) u_csr3_field5 (
719 .clk_i (clk_i),
720 .rst_ni (rst_ni),
721
722 // from register interface
723 .we (csr3_gated_we),
724 .wd (csr3_field5_wd),
725
726 // from internal hardware
727 .de (1'b0),
728 .d ('0),
729
730 // to internal hardware
731 .qe (),
732 .q (reg2hw.csr3.field5.q),
733 .ds (),
734
735 // to register interface (read)
736 .qs (csr3_field5_qs)
737 );
738
739 // F[field6]: 20:20
740 prim_subreg #(
741 .DW (1),
742 .SwAccess(prim_subreg_pkg::SwAccessRW),
743 .RESVAL (1'h0),
744 .Mubi (1'b0)
745 ) u_csr3_field6 (
746 .clk_i (clk_i),
747 .rst_ni (rst_ni),
748
749 // from register interface
750 .we (csr3_gated_we),
751 .wd (csr3_field6_wd),
752
753 // from internal hardware
754 .de (1'b0),
755 .d ('0),
756
757 // to internal hardware
758 .qe (),
759 .q (reg2hw.csr3.field6.q),
760 .ds (),
761
762 // to register interface (read)
763 .qs (csr3_field6_qs)
764 );
765
766 // F[field7]: 23:21
767 prim_subreg #(
768 .DW (3),
769 .SwAccess(prim_subreg_pkg::SwAccessRW),
770 .RESVAL (3'h0),
771 .Mubi (1'b0)
772 ) u_csr3_field7 (
773 .clk_i (clk_i),
774 .rst_ni (rst_ni),
775
776 // from register interface
777 .we (csr3_gated_we),
778 .wd (csr3_field7_wd),
779
780 // from internal hardware
781 .de (1'b0),
782 .d ('0),
783
784 // to internal hardware
785 .qe (),
786 .q (reg2hw.csr3.field7.q),
787 .ds (),
788
789 // to register interface (read)
790 .qs (csr3_field7_qs)
791 );
792
793 // F[field8]: 25:24
794 prim_subreg #(
795 .DW (2),
796 .SwAccess(prim_subreg_pkg::SwAccessRW),
797 .RESVAL (2'h0),
798 .Mubi (1'b0)
799 ) u_csr3_field8 (
800 .clk_i (clk_i),
801 .rst_ni (rst_ni),
802
803 // from register interface
804 .we (csr3_gated_we),
805 .wd (csr3_field8_wd),
806
807 // from internal hardware
808 .de (1'b0),
809 .d ('0),
810
811 // to internal hardware
812 .qe (),
813 .q (reg2hw.csr3.field8.q),
814 .ds (),
815
816 // to register interface (read)
817 .qs (csr3_field8_qs)
818 );
819
820 // F[field9]: 27:26
821 prim_subreg #(
822 .DW (2),
823 .SwAccess(prim_subreg_pkg::SwAccessRW),
824 .RESVAL (2'h0),
825 .Mubi (1'b0)
826 ) u_csr3_field9 (
827 .clk_i (clk_i),
828 .rst_ni (rst_ni),
829
830 // from register interface
831 .we (csr3_gated_we),
832 .wd (csr3_field9_wd),
833
834 // from internal hardware
835 .de (1'b0),
836 .d ('0),
837
838 // to internal hardware
839 .qe (),
840 .q (reg2hw.csr3.field9.q),
841 .ds (),
842
843 // to register interface (read)
844 .qs (csr3_field9_qs)
845 );
846
847
848 // R[csr4]: V(False)
849 // Create REGWEN-gated WE signal
850 logic csr4_gated_we;
851 1/1 assign csr4_gated_we = csr4_we & csr0_regwen_qs;
Tests: T1 T2 T3
852 // F[field0]: 2:0
853 prim_subreg #(
854 .DW (3),
855 .SwAccess(prim_subreg_pkg::SwAccessRW),
856 .RESVAL (3'h0),
857 .Mubi (1'b0)
858 ) u_csr4_field0 (
859 .clk_i (clk_i),
860 .rst_ni (rst_ni),
861
862 // from register interface
863 .we (csr4_gated_we),
864 .wd (csr4_field0_wd),
865
866 // from internal hardware
867 .de (1'b0),
868 .d ('0),
869
870 // to internal hardware
871 .qe (),
872 .q (reg2hw.csr4.field0.q),
873 .ds (),
874
875 // to register interface (read)
876 .qs (csr4_field0_qs)
877 );
878
879 // F[field1]: 5:3
880 prim_subreg #(
881 .DW (3),
882 .SwAccess(prim_subreg_pkg::SwAccessRW),
883 .RESVAL (3'h0),
884 .Mubi (1'b0)
885 ) u_csr4_field1 (
886 .clk_i (clk_i),
887 .rst_ni (rst_ni),
888
889 // from register interface
890 .we (csr4_gated_we),
891 .wd (csr4_field1_wd),
892
893 // from internal hardware
894 .de (1'b0),
895 .d ('0),
896
897 // to internal hardware
898 .qe (),
899 .q (reg2hw.csr4.field1.q),
900 .ds (),
901
902 // to register interface (read)
903 .qs (csr4_field1_qs)
904 );
905
906 // F[field2]: 8:6
907 prim_subreg #(
908 .DW (3),
909 .SwAccess(prim_subreg_pkg::SwAccessRW),
910 .RESVAL (3'h0),
911 .Mubi (1'b0)
912 ) u_csr4_field2 (
913 .clk_i (clk_i),
914 .rst_ni (rst_ni),
915
916 // from register interface
917 .we (csr4_gated_we),
918 .wd (csr4_field2_wd),
919
920 // from internal hardware
921 .de (1'b0),
922 .d ('0),
923
924 // to internal hardware
925 .qe (),
926 .q (reg2hw.csr4.field2.q),
927 .ds (),
928
929 // to register interface (read)
930 .qs (csr4_field2_qs)
931 );
932
933 // F[field3]: 11:9
934 prim_subreg #(
935 .DW (3),
936 .SwAccess(prim_subreg_pkg::SwAccessRW),
937 .RESVAL (3'h0),
938 .Mubi (1'b0)
939 ) u_csr4_field3 (
940 .clk_i (clk_i),
941 .rst_ni (rst_ni),
942
943 // from register interface
944 .we (csr4_gated_we),
945 .wd (csr4_field3_wd),
946
947 // from internal hardware
948 .de (1'b0),
949 .d ('0),
950
951 // to internal hardware
952 .qe (),
953 .q (reg2hw.csr4.field3.q),
954 .ds (),
955
956 // to register interface (read)
957 .qs (csr4_field3_qs)
958 );
959
960
961 // R[csr5]: V(False)
962 // Create REGWEN-gated WE signal
963 logic csr5_gated_we;
964 1/1 assign csr5_gated_we = csr5_we & csr0_regwen_qs;
Tests: T1 T2 T3
965 // F[field0]: 2:0
966 prim_subreg #(
967 .DW (3),
968 .SwAccess(prim_subreg_pkg::SwAccessRW),
969 .RESVAL (3'h0),
970 .Mubi (1'b0)
971 ) u_csr5_field0 (
972 .clk_i (clk_i),
973 .rst_ni (rst_ni),
974
975 // from register interface
976 .we (csr5_gated_we),
977 .wd (csr5_field0_wd),
978
979 // from internal hardware
980 .de (1'b0),
981 .d ('0),
982
983 // to internal hardware
984 .qe (),
985 .q (reg2hw.csr5.field0.q),
986 .ds (),
987
988 // to register interface (read)
989 .qs (csr5_field0_qs)
990 );
991
992 // F[field1]: 4:3
993 prim_subreg #(
994 .DW (2),
995 .SwAccess(prim_subreg_pkg::SwAccessRW),
996 .RESVAL (2'h0),
997 .Mubi (1'b0)
998 ) u_csr5_field1 (
999 .clk_i (clk_i),
1000 .rst_ni (rst_ni),
1001
1002 // from register interface
1003 .we (csr5_gated_we),
1004 .wd (csr5_field1_wd),
1005
1006 // from internal hardware
1007 .de (1'b0),
1008 .d ('0),
1009
1010 // to internal hardware
1011 .qe (),
1012 .q (reg2hw.csr5.field1.q),
1013 .ds (),
1014
1015 // to register interface (read)
1016 .qs (csr5_field1_qs)
1017 );
1018
1019 // F[field2]: 13:5
1020 prim_subreg #(
1021 .DW (9),
1022 .SwAccess(prim_subreg_pkg::SwAccessRW),
1023 .RESVAL (9'h0),
1024 .Mubi (1'b0)
1025 ) u_csr5_field2 (
1026 .clk_i (clk_i),
1027 .rst_ni (rst_ni),
1028
1029 // from register interface
1030 .we (csr5_gated_we),
1031 .wd (csr5_field2_wd),
1032
1033 // from internal hardware
1034 .de (1'b0),
1035 .d ('0),
1036
1037 // to internal hardware
1038 .qe (),
1039 .q (reg2hw.csr5.field2.q),
1040 .ds (),
1041
1042 // to register interface (read)
1043 .qs (csr5_field2_qs)
1044 );
1045
1046 // F[field3]: 18:14
1047 prim_subreg #(
1048 .DW (5),
1049 .SwAccess(prim_subreg_pkg::SwAccessRW),
1050 .RESVAL (5'h0),
1051 .Mubi (1'b0)
1052 ) u_csr5_field3 (
1053 .clk_i (clk_i),
1054 .rst_ni (rst_ni),
1055
1056 // from register interface
1057 .we (csr5_gated_we),
1058 .wd (csr5_field3_wd),
1059
1060 // from internal hardware
1061 .de (1'b0),
1062 .d ('0),
1063
1064 // to internal hardware
1065 .qe (),
1066 .q (reg2hw.csr5.field3.q),
1067 .ds (),
1068
1069 // to register interface (read)
1070 .qs (csr5_field3_qs)
1071 );
1072
1073 // F[field4]: 22:19
1074 prim_subreg #(
1075 .DW (4),
1076 .SwAccess(prim_subreg_pkg::SwAccessRW),
1077 .RESVAL (4'h0),
1078 .Mubi (1'b0)
1079 ) u_csr5_field4 (
1080 .clk_i (clk_i),
1081 .rst_ni (rst_ni),
1082
1083 // from register interface
1084 .we (csr5_gated_we),
1085 .wd (csr5_field4_wd),
1086
1087 // from internal hardware
1088 .de (1'b0),
1089 .d ('0),
1090
1091 // to internal hardware
1092 .qe (),
1093 .q (reg2hw.csr5.field4.q),
1094 .ds (),
1095
1096 // to register interface (read)
1097 .qs (csr5_field4_qs)
1098 );
1099
1100
1101 // R[csr6]: V(False)
1102 // Create REGWEN-gated WE signal
1103 logic csr6_gated_we;
1104 1/1 assign csr6_gated_we = csr6_we & csr0_regwen_qs;
Tests: T1 T2 T3
1105 // F[field0]: 2:0
1106 prim_subreg #(
1107 .DW (3),
1108 .SwAccess(prim_subreg_pkg::SwAccessRW),
1109 .RESVAL (3'h0),
1110 .Mubi (1'b0)
1111 ) u_csr6_field0 (
1112 .clk_i (clk_i),
1113 .rst_ni (rst_ni),
1114
1115 // from register interface
1116 .we (csr6_gated_we),
1117 .wd (csr6_field0_wd),
1118
1119 // from internal hardware
1120 .de (1'b0),
1121 .d ('0),
1122
1123 // to internal hardware
1124 .qe (),
1125 .q (reg2hw.csr6.field0.q),
1126 .ds (),
1127
1128 // to register interface (read)
1129 .qs (csr6_field0_qs)
1130 );
1131
1132 // F[field1]: 5:3
1133 prim_subreg #(
1134 .DW (3),
1135 .SwAccess(prim_subreg_pkg::SwAccessRW),
1136 .RESVAL (3'h0),
1137 .Mubi (1'b0)
1138 ) u_csr6_field1 (
1139 .clk_i (clk_i),
1140 .rst_ni (rst_ni),
1141
1142 // from register interface
1143 .we (csr6_gated_we),
1144 .wd (csr6_field1_wd),
1145
1146 // from internal hardware
1147 .de (1'b0),
1148 .d ('0),
1149
1150 // to internal hardware
1151 .qe (),
1152 .q (reg2hw.csr6.field1.q),
1153 .ds (),
1154
1155 // to register interface (read)
1156 .qs (csr6_field1_qs)
1157 );
1158
1159 // F[field2]: 13:6
1160 prim_subreg #(
1161 .DW (8),
1162 .SwAccess(prim_subreg_pkg::SwAccessRW),
1163 .RESVAL (8'h0),
1164 .Mubi (1'b0)
1165 ) u_csr6_field2 (
1166 .clk_i (clk_i),
1167 .rst_ni (rst_ni),
1168
1169 // from register interface
1170 .we (csr6_gated_we),
1171 .wd (csr6_field2_wd),
1172
1173 // from internal hardware
1174 .de (1'b0),
1175 .d ('0),
1176
1177 // to internal hardware
1178 .qe (),
1179 .q (reg2hw.csr6.field2.q),
1180 .ds (),
1181
1182 // to register interface (read)
1183 .qs (csr6_field2_qs)
1184 );
1185
1186 // F[field3]: 16:14
1187 prim_subreg #(
1188 .DW (3),
1189 .SwAccess(prim_subreg_pkg::SwAccessRW),
1190 .RESVAL (3'h0),
1191 .Mubi (1'b0)
1192 ) u_csr6_field3 (
1193 .clk_i (clk_i),
1194 .rst_ni (rst_ni),
1195
1196 // from register interface
1197 .we (csr6_gated_we),
1198 .wd (csr6_field3_wd),
1199
1200 // from internal hardware
1201 .de (1'b0),
1202 .d ('0),
1203
1204 // to internal hardware
1205 .qe (),
1206 .q (reg2hw.csr6.field3.q),
1207 .ds (),
1208
1209 // to register interface (read)
1210 .qs (csr6_field3_qs)
1211 );
1212
1213 // F[field4]: 18:17
1214 prim_subreg #(
1215 .DW (2),
1216 .SwAccess(prim_subreg_pkg::SwAccessRW),
1217 .RESVAL (2'h0),
1218 .Mubi (1'b0)
1219 ) u_csr6_field4 (
1220 .clk_i (clk_i),
1221 .rst_ni (rst_ni),
1222
1223 // from register interface
1224 .we (csr6_gated_we),
1225 .wd (csr6_field4_wd),
1226
1227 // from internal hardware
1228 .de (1'b0),
1229 .d ('0),
1230
1231 // to internal hardware
1232 .qe (),
1233 .q (reg2hw.csr6.field4.q),
1234 .ds (),
1235
1236 // to register interface (read)
1237 .qs (csr6_field4_qs)
1238 );
1239
1240 // F[field5]: 20:19
1241 prim_subreg #(
1242 .DW (2),
1243 .SwAccess(prim_subreg_pkg::SwAccessRW),
1244 .RESVAL (2'h0),
1245 .Mubi (1'b0)
1246 ) u_csr6_field5 (
1247 .clk_i (clk_i),
1248 .rst_ni (rst_ni),
1249
1250 // from register interface
1251 .we (csr6_gated_we),
1252 .wd (csr6_field5_wd),
1253
1254 // from internal hardware
1255 .de (1'b0),
1256 .d ('0),
1257
1258 // to internal hardware
1259 .qe (),
1260 .q (reg2hw.csr6.field5.q),
1261 .ds (),
1262
1263 // to register interface (read)
1264 .qs (csr6_field5_qs)
1265 );
1266
1267 // F[field6]: 22:21
1268 prim_subreg #(
1269 .DW (2),
1270 .SwAccess(prim_subreg_pkg::SwAccessRW),
1271 .RESVAL (2'h0),
1272 .Mubi (1'b0)
1273 ) u_csr6_field6 (
1274 .clk_i (clk_i),
1275 .rst_ni (rst_ni),
1276
1277 // from register interface
1278 .we (csr6_gated_we),
1279 .wd (csr6_field6_wd),
1280
1281 // from internal hardware
1282 .de (1'b0),
1283 .d ('0),
1284
1285 // to internal hardware
1286 .qe (),
1287 .q (reg2hw.csr6.field6.q),
1288 .ds (),
1289
1290 // to register interface (read)
1291 .qs (csr6_field6_qs)
1292 );
1293
1294 // F[field7]: 23:23
1295 prim_subreg #(
1296 .DW (1),
1297 .SwAccess(prim_subreg_pkg::SwAccessRW),
1298 .RESVAL (1'h0),
1299 .Mubi (1'b0)
1300 ) u_csr6_field7 (
1301 .clk_i (clk_i),
1302 .rst_ni (rst_ni),
1303
1304 // from register interface
1305 .we (csr6_gated_we),
1306 .wd (csr6_field7_wd),
1307
1308 // from internal hardware
1309 .de (1'b0),
1310 .d ('0),
1311
1312 // to internal hardware
1313 .qe (),
1314 .q (reg2hw.csr6.field7.q),
1315 .ds (),
1316
1317 // to register interface (read)
1318 .qs (csr6_field7_qs)
1319 );
1320
1321 // F[field8]: 24:24
1322 prim_subreg #(
1323 .DW (1),
1324 .SwAccess(prim_subreg_pkg::SwAccessRW),
1325 .RESVAL (1'h0),
1326 .Mubi (1'b0)
1327 ) u_csr6_field8 (
1328 .clk_i (clk_i),
1329 .rst_ni (rst_ni),
1330
1331 // from register interface
1332 .we (csr6_gated_we),
1333 .wd (csr6_field8_wd),
1334
1335 // from internal hardware
1336 .de (1'b0),
1337 .d ('0),
1338
1339 // to internal hardware
1340 .qe (),
1341 .q (reg2hw.csr6.field8.q),
1342 .ds (),
1343
1344 // to register interface (read)
1345 .qs (csr6_field8_qs)
1346 );
1347
1348
1349 // R[csr7]: V(False)
1350 // Create REGWEN-gated WE signal
1351 logic csr7_gated_we;
1352 1/1 assign csr7_gated_we = csr7_we & csr0_regwen_qs;
Tests: T1 T2 T3
1353 // F[field0]: 7:0
1354 prim_subreg #(
1355 .DW (8),
1356 .SwAccess(prim_subreg_pkg::SwAccessRW),
1357 .RESVAL (8'h0),
1358 .Mubi (1'b0)
1359 ) u_csr7_field0 (
1360 .clk_i (clk_i),
1361 .rst_ni (rst_ni),
1362
1363 // from register interface
1364 .we (csr7_gated_we),
1365 .wd (csr7_field0_wd),
1366
1367 // from internal hardware
1368 .de (1'b0),
1369 .d ('0),
1370
1371 // to internal hardware
1372 .qe (),
1373 .q (reg2hw.csr7.field0.q),
1374 .ds (),
1375
1376 // to register interface (read)
1377 .qs (csr7_field0_qs)
1378 );
1379
1380 // F[field1]: 16:8
1381 prim_subreg #(
1382 .DW (9),
1383 .SwAccess(prim_subreg_pkg::SwAccessRW),
1384 .RESVAL (9'h0),
1385 .Mubi (1'b0)
1386 ) u_csr7_field1 (
1387 .clk_i (clk_i),
1388 .rst_ni (rst_ni),
1389
1390 // from register interface
1391 .we (csr7_gated_we),
1392 .wd (csr7_field1_wd),
1393
1394 // from internal hardware
1395 .de (1'b0),
1396 .d ('0),
1397
1398 // to internal hardware
1399 .qe (),
1400 .q (reg2hw.csr7.field1.q),
1401 .ds (),
1402
1403 // to register interface (read)
1404 .qs (csr7_field1_qs)
1405 );
1406
1407
1408 // R[csr8]: V(False)
1409 // Create REGWEN-gated WE signal
1410 logic csr8_gated_we;
1411 1/1 assign csr8_gated_we = csr8_we & csr0_regwen_qs;
Tests: T1 T2 T3
1412 prim_subreg #(
1413 .DW (32),
1414 .SwAccess(prim_subreg_pkg::SwAccessRW),
1415 .RESVAL (32'h0),
1416 .Mubi (1'b0)
1417 ) u_csr8 (
1418 .clk_i (clk_i),
1419 .rst_ni (rst_ni),
1420
1421 // from register interface
1422 .we (csr8_gated_we),
1423 .wd (csr8_wd),
1424
1425 // from internal hardware
1426 .de (1'b0),
1427 .d ('0),
1428
1429 // to internal hardware
1430 .qe (),
1431 .q (reg2hw.csr8.q),
1432 .ds (),
1433
1434 // to register interface (read)
1435 .qs (csr8_qs)
1436 );
1437
1438
1439 // R[csr9]: V(False)
1440 // Create REGWEN-gated WE signal
1441 logic csr9_gated_we;
1442 1/1 assign csr9_gated_we = csr9_we & csr0_regwen_qs;
Tests: T1 T2 T3
1443 prim_subreg #(
1444 .DW (32),
1445 .SwAccess(prim_subreg_pkg::SwAccessRW),
1446 .RESVAL (32'h0),
1447 .Mubi (1'b0)
1448 ) u_csr9 (
1449 .clk_i (clk_i),
1450 .rst_ni (rst_ni),
1451
1452 // from register interface
1453 .we (csr9_gated_we),
1454 .wd (csr9_wd),
1455
1456 // from internal hardware
1457 .de (1'b0),
1458 .d ('0),
1459
1460 // to internal hardware
1461 .qe (),
1462 .q (reg2hw.csr9.q),
1463 .ds (),
1464
1465 // to register interface (read)
1466 .qs (csr9_qs)
1467 );
1468
1469
1470 // R[csr10]: V(False)
1471 // Create REGWEN-gated WE signal
1472 logic csr10_gated_we;
1473 1/1 assign csr10_gated_we = csr10_we & csr0_regwen_qs;
Tests: T1 T2 T3
1474 prim_subreg #(
1475 .DW (32),
1476 .SwAccess(prim_subreg_pkg::SwAccessRW),
1477 .RESVAL (32'h0),
1478 .Mubi (1'b0)
1479 ) u_csr10 (
1480 .clk_i (clk_i),
1481 .rst_ni (rst_ni),
1482
1483 // from register interface
1484 .we (csr10_gated_we),
1485 .wd (csr10_wd),
1486
1487 // from internal hardware
1488 .de (1'b0),
1489 .d ('0),
1490
1491 // to internal hardware
1492 .qe (),
1493 .q (reg2hw.csr10.q),
1494 .ds (),
1495
1496 // to register interface (read)
1497 .qs (csr10_qs)
1498 );
1499
1500
1501 // R[csr11]: V(False)
1502 // Create REGWEN-gated WE signal
1503 logic csr11_gated_we;
1504 1/1 assign csr11_gated_we = csr11_we & csr0_regwen_qs;
Tests: T1 T2 T3
1505 prim_subreg #(
1506 .DW (32),
1507 .SwAccess(prim_subreg_pkg::SwAccessRW),
1508 .RESVAL (32'h0),
1509 .Mubi (1'b0)
1510 ) u_csr11 (
1511 .clk_i (clk_i),
1512 .rst_ni (rst_ni),
1513
1514 // from register interface
1515 .we (csr11_gated_we),
1516 .wd (csr11_wd),
1517
1518 // from internal hardware
1519 .de (1'b0),
1520 .d ('0),
1521
1522 // to internal hardware
1523 .qe (),
1524 .q (reg2hw.csr11.q),
1525 .ds (),
1526
1527 // to register interface (read)
1528 .qs (csr11_qs)
1529 );
1530
1531
1532 // R[csr12]: V(False)
1533 // Create REGWEN-gated WE signal
1534 logic csr12_gated_we;
1535 1/1 assign csr12_gated_we = csr12_we & csr0_regwen_qs;
Tests: T1 T2 T3
1536 prim_subreg #(
1537 .DW (10),
1538 .SwAccess(prim_subreg_pkg::SwAccessRW),
1539 .RESVAL (10'h0),
1540 .Mubi (1'b0)
1541 ) u_csr12 (
1542 .clk_i (clk_i),
1543 .rst_ni (rst_ni),
1544
1545 // from register interface
1546 .we (csr12_gated_we),
1547 .wd (csr12_wd),
1548
1549 // from internal hardware
1550 .de (1'b0),
1551 .d ('0),
1552
1553 // to internal hardware
1554 .qe (),
1555 .q (reg2hw.csr12.q),
1556 .ds (),
1557
1558 // to register interface (read)
1559 .qs (csr12_qs)
1560 );
1561
1562
1563 // R[csr13]: V(False)
1564 // Create REGWEN-gated WE signal
1565 logic csr13_gated_we;
1566 1/1 assign csr13_gated_we = csr13_we & csr0_regwen_qs;
Tests: T1 T2 T3
1567 // F[field0]: 19:0
1568 prim_subreg #(
1569 .DW (20),
1570 .SwAccess(prim_subreg_pkg::SwAccessRW),
1571 .RESVAL (20'h0),
1572 .Mubi (1'b0)
1573 ) u_csr13_field0 (
1574 .clk_i (clk_i),
1575 .rst_ni (rst_ni),
1576
1577 // from register interface
1578 .we (csr13_gated_we),
1579 .wd (csr13_field0_wd),
1580
1581 // from internal hardware
1582 .de (1'b0),
1583 .d ('0),
1584
1585 // to internal hardware
1586 .qe (),
1587 .q (reg2hw.csr13.field0.q),
1588 .ds (),
1589
1590 // to register interface (read)
1591 .qs (csr13_field0_qs)
1592 );
1593
1594 // F[field1]: 20:20
1595 prim_subreg #(
1596 .DW (1),
1597 .SwAccess(prim_subreg_pkg::SwAccessRW),
1598 .RESVAL (1'h0),
1599 .Mubi (1'b0)
1600 ) u_csr13_field1 (
1601 .clk_i (clk_i),
1602 .rst_ni (rst_ni),
1603
1604 // from register interface
1605 .we (csr13_gated_we),
1606 .wd (csr13_field1_wd),
1607
1608 // from internal hardware
1609 .de (1'b0),
1610 .d ('0),
1611
1612 // to internal hardware
1613 .qe (),
1614 .q (reg2hw.csr13.field1.q),
1615 .ds (),
1616
1617 // to register interface (read)
1618 .qs (csr13_field1_qs)
1619 );
1620
1621
1622 // R[csr14]: V(False)
1623 // Create REGWEN-gated WE signal
1624 logic csr14_gated_we;
1625 1/1 assign csr14_gated_we = csr14_we & csr0_regwen_qs;
Tests: T1 T2 T3
1626 // F[field0]: 7:0
1627 prim_subreg #(
1628 .DW (8),
1629 .SwAccess(prim_subreg_pkg::SwAccessRW),
1630 .RESVAL (8'h0),
1631 .Mubi (1'b0)
1632 ) u_csr14_field0 (
1633 .clk_i (clk_i),
1634 .rst_ni (rst_ni),
1635
1636 // from register interface
1637 .we (csr14_gated_we),
1638 .wd (csr14_field0_wd),
1639
1640 // from internal hardware
1641 .de (1'b0),
1642 .d ('0),
1643
1644 // to internal hardware
1645 .qe (),
1646 .q (reg2hw.csr14.field0.q),
1647 .ds (),
1648
1649 // to register interface (read)
1650 .qs (csr14_field0_qs)
1651 );
1652
1653 // F[field1]: 8:8
1654 prim_subreg #(
1655 .DW (1),
1656 .SwAccess(prim_subreg_pkg::SwAccessRW),
1657 .RESVAL (1'h0),
1658 .Mubi (1'b0)
1659 ) u_csr14_field1 (
1660 .clk_i (clk_i),
1661 .rst_ni (rst_ni),
1662
1663 // from register interface
1664 .we (csr14_gated_we),
1665 .wd (csr14_field1_wd),
1666
1667 // from internal hardware
1668 .de (1'b0),
1669 .d ('0),
1670
1671 // to internal hardware
1672 .qe (),
1673 .q (reg2hw.csr14.field1.q),
1674 .ds (),
1675
1676 // to register interface (read)
1677 .qs (csr14_field1_qs)
1678 );
1679
1680
1681 // R[csr15]: V(False)
1682 // Create REGWEN-gated WE signal
1683 logic csr15_gated_we;
1684 1/1 assign csr15_gated_we = csr15_we & csr0_regwen_qs;
Tests: T1 T2 T3
1685 // F[field0]: 7:0
1686 prim_subreg #(
1687 .DW (8),
1688 .SwAccess(prim_subreg_pkg::SwAccessRW),
1689 .RESVAL (8'h0),
1690 .Mubi (1'b0)
1691 ) u_csr15_field0 (
1692 .clk_i (clk_i),
1693 .rst_ni (rst_ni),
1694
1695 // from register interface
1696 .we (csr15_gated_we),
1697 .wd (csr15_field0_wd),
1698
1699 // from internal hardware
1700 .de (1'b0),
1701 .d ('0),
1702
1703 // to internal hardware
1704 .qe (),
1705 .q (reg2hw.csr15.field0.q),
1706 .ds (),
1707
1708 // to register interface (read)
1709 .qs (csr15_field0_qs)
1710 );
1711
1712 // F[field1]: 8:8
1713 prim_subreg #(
1714 .DW (1),
1715 .SwAccess(prim_subreg_pkg::SwAccessRW),
1716 .RESVAL (1'h0),
1717 .Mubi (1'b0)
1718 ) u_csr15_field1 (
1719 .clk_i (clk_i),
1720 .rst_ni (rst_ni),
1721
1722 // from register interface
1723 .we (csr15_gated_we),
1724 .wd (csr15_field1_wd),
1725
1726 // from internal hardware
1727 .de (1'b0),
1728 .d ('0),
1729
1730 // to internal hardware
1731 .qe (),
1732 .q (reg2hw.csr15.field1.q),
1733 .ds (),
1734
1735 // to register interface (read)
1736 .qs (csr15_field1_qs)
1737 );
1738
1739
1740 // R[csr16]: V(False)
1741 // Create REGWEN-gated WE signal
1742 logic csr16_gated_we;
1743 1/1 assign csr16_gated_we = csr16_we & csr0_regwen_qs;
Tests: T1 T2 T3
1744 // F[field0]: 7:0
1745 prim_subreg #(
1746 .DW (8),
1747 .SwAccess(prim_subreg_pkg::SwAccessRW),
1748 .RESVAL (8'h0),
1749 .Mubi (1'b0)
1750 ) u_csr16_field0 (
1751 .clk_i (clk_i),
1752 .rst_ni (rst_ni),
1753
1754 // from register interface
1755 .we (csr16_gated_we),
1756 .wd (csr16_field0_wd),
1757
1758 // from internal hardware
1759 .de (1'b0),
1760 .d ('0),
1761
1762 // to internal hardware
1763 .qe (),
1764 .q (reg2hw.csr16.field0.q),
1765 .ds (),
1766
1767 // to register interface (read)
1768 .qs (csr16_field0_qs)
1769 );
1770
1771 // F[field1]: 8:8
1772 prim_subreg #(
1773 .DW (1),
1774 .SwAccess(prim_subreg_pkg::SwAccessRW),
1775 .RESVAL (1'h0),
1776 .Mubi (1'b0)
1777 ) u_csr16_field1 (
1778 .clk_i (clk_i),
1779 .rst_ni (rst_ni),
1780
1781 // from register interface
1782 .we (csr16_gated_we),
1783 .wd (csr16_field1_wd),
1784
1785 // from internal hardware
1786 .de (1'b0),
1787 .d ('0),
1788
1789 // to internal hardware
1790 .qe (),
1791 .q (reg2hw.csr16.field1.q),
1792 .ds (),
1793
1794 // to register interface (read)
1795 .qs (csr16_field1_qs)
1796 );
1797
1798
1799 // R[csr17]: V(False)
1800 // Create REGWEN-gated WE signal
1801 logic csr17_gated_we;
1802 1/1 assign csr17_gated_we = csr17_we & csr0_regwen_qs;
Tests: T1 T2 T3
1803 // F[field0]: 7:0
1804 prim_subreg #(
1805 .DW (8),
1806 .SwAccess(prim_subreg_pkg::SwAccessRW),
1807 .RESVAL (8'h0),
1808 .Mubi (1'b0)
1809 ) u_csr17_field0 (
1810 .clk_i (clk_i),
1811 .rst_ni (rst_ni),
1812
1813 // from register interface
1814 .we (csr17_gated_we),
1815 .wd (csr17_field0_wd),
1816
1817 // from internal hardware
1818 .de (1'b0),
1819 .d ('0),
1820
1821 // to internal hardware
1822 .qe (),
1823 .q (reg2hw.csr17.field0.q),
1824 .ds (),
1825
1826 // to register interface (read)
1827 .qs (csr17_field0_qs)
1828 );
1829
1830 // F[field1]: 8:8
1831 prim_subreg #(
1832 .DW (1),
1833 .SwAccess(prim_subreg_pkg::SwAccessRW),
1834 .RESVAL (1'h0),
1835 .Mubi (1'b0)
1836 ) u_csr17_field1 (
1837 .clk_i (clk_i),
1838 .rst_ni (rst_ni),
1839
1840 // from register interface
1841 .we (csr17_gated_we),
1842 .wd (csr17_field1_wd),
1843
1844 // from internal hardware
1845 .de (1'b0),
1846 .d ('0),
1847
1848 // to internal hardware
1849 .qe (),
1850 .q (reg2hw.csr17.field1.q),
1851 .ds (),
1852
1853 // to register interface (read)
1854 .qs (csr17_field1_qs)
1855 );
1856
1857
1858 // R[csr18]: V(False)
1859 // Create REGWEN-gated WE signal
1860 logic csr18_gated_we;
1861 1/1 assign csr18_gated_we = csr18_we & csr0_regwen_qs;
Tests: T1 T2 T3
1862 prim_subreg #(
1863 .DW (1),
1864 .SwAccess(prim_subreg_pkg::SwAccessRW),
1865 .RESVAL (1'h0),
1866 .Mubi (1'b0)
1867 ) u_csr18 (
1868 .clk_i (clk_i),
1869 .rst_ni (rst_ni),
1870
1871 // from register interface
1872 .we (csr18_gated_we),
1873 .wd (csr18_wd),
1874
1875 // from internal hardware
1876 .de (1'b0),
1877 .d ('0),
1878
1879 // to internal hardware
1880 .qe (),
1881 .q (reg2hw.csr18.q),
1882 .ds (),
1883
1884 // to register interface (read)
1885 .qs (csr18_qs)
1886 );
1887
1888
1889 // R[csr19]: V(False)
1890 // Create REGWEN-gated WE signal
1891 logic csr19_gated_we;
1892 1/1 assign csr19_gated_we = csr19_we & csr0_regwen_qs;
Tests: T1 T2 T3
1893 prim_subreg #(
1894 .DW (1),
1895 .SwAccess(prim_subreg_pkg::SwAccessRW),
1896 .RESVAL (1'h0),
1897 .Mubi (1'b0)
1898 ) u_csr19 (
1899 .clk_i (clk_i),
1900 .rst_ni (rst_ni),
1901
1902 // from register interface
1903 .we (csr19_gated_we),
1904 .wd (csr19_wd),
1905
1906 // from internal hardware
1907 .de (1'b0),
1908 .d ('0),
1909
1910 // to internal hardware
1911 .qe (),
1912 .q (reg2hw.csr19.q),
1913 .ds (),
1914
1915 // to register interface (read)
1916 .qs (csr19_qs)
1917 );
1918
1919
1920 // R[csr20]: V(False)
1921 // F[field0]: 0:0
1922 prim_subreg #(
1923 .DW (1),
1924 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1925 .RESVAL (1'h0),
1926 .Mubi (1'b0)
1927 ) u_csr20_field0 (
1928 .clk_i (clk_i),
1929 .rst_ni (rst_ni),
1930
1931 // from register interface
1932 .we (csr20_we),
1933 .wd (csr20_field0_wd),
1934
1935 // from internal hardware
1936 .de (hw2reg.csr20.field0.de),
1937 .d (hw2reg.csr20.field0.d),
1938
1939 // to internal hardware
1940 .qe (),
1941 .q (reg2hw.csr20.field0.q),
1942 .ds (),
1943
1944 // to register interface (read)
1945 .qs (csr20_field0_qs)
1946 );
1947
1948 // F[field1]: 1:1
1949 prim_subreg #(
1950 .DW (1),
1951 .SwAccess(prim_subreg_pkg::SwAccessW1C),
1952 .RESVAL (1'h0),
1953 .Mubi (1'b0)
1954 ) u_csr20_field1 (
1955 .clk_i (clk_i),
1956 .rst_ni (rst_ni),
1957
1958 // from register interface
1959 .we (csr20_we),
1960 .wd (csr20_field1_wd),
1961
1962 // from internal hardware
1963 .de (hw2reg.csr20.field1.de),
1964 .d (hw2reg.csr20.field1.d),
1965
1966 // to internal hardware
1967 .qe (),
1968 .q (reg2hw.csr20.field1.q),
1969 .ds (),
1970
1971 // to register interface (read)
1972 .qs (csr20_field1_qs)
1973 );
1974
1975 // F[field2]: 2:2
1976 prim_subreg #(
1977 .DW (1),
1978 .SwAccess(prim_subreg_pkg::SwAccessRO),
1979 .RESVAL (1'h0),
1980 .Mubi (1'b0)
1981 ) u_csr20_field2 (
1982 .clk_i (clk_i),
1983 .rst_ni (rst_ni),
1984
1985 // from register interface
1986 .we (1'b0),
1987 .wd ('0),
1988
1989 // from internal hardware
1990 .de (hw2reg.csr20.field2.de),
1991 .d (hw2reg.csr20.field2.d),
1992
1993 // to internal hardware
1994 .qe (),
1995 .q (reg2hw.csr20.field2.q),
1996 .ds (),
1997
1998 // to register interface (read)
1999 .qs (csr20_field2_qs)
2000 );
2001
2002
2003
2004 logic [20:0] addr_hit;
2005 always_comb begin
2006 1/1 addr_hit = '0;
Tests: T2 T5 T16
2007 1/1 addr_hit[ 0] = (reg_addr == FLASH_CTRL_CSR0_REGWEN_OFFSET);
Tests: T2 T5 T16
2008 1/1 addr_hit[ 1] = (reg_addr == FLASH_CTRL_CSR1_OFFSET);
Tests: T2 T5 T16
2009 1/1 addr_hit[ 2] = (reg_addr == FLASH_CTRL_CSR2_OFFSET);
Tests: T2 T5 T16
2010 1/1 addr_hit[ 3] = (reg_addr == FLASH_CTRL_CSR3_OFFSET);
Tests: T2 T5 T16
2011 1/1 addr_hit[ 4] = (reg_addr == FLASH_CTRL_CSR4_OFFSET);
Tests: T2 T5 T16
2012 1/1 addr_hit[ 5] = (reg_addr == FLASH_CTRL_CSR5_OFFSET);
Tests: T2 T5 T16
2013 1/1 addr_hit[ 6] = (reg_addr == FLASH_CTRL_CSR6_OFFSET);
Tests: T2 T5 T16
2014 1/1 addr_hit[ 7] = (reg_addr == FLASH_CTRL_CSR7_OFFSET);
Tests: T2 T5 T16
2015 1/1 addr_hit[ 8] = (reg_addr == FLASH_CTRL_CSR8_OFFSET);
Tests: T2 T5 T16
2016 1/1 addr_hit[ 9] = (reg_addr == FLASH_CTRL_CSR9_OFFSET);
Tests: T2 T5 T16
2017 1/1 addr_hit[10] = (reg_addr == FLASH_CTRL_CSR10_OFFSET);
Tests: T2 T5 T16
2018 1/1 addr_hit[11] = (reg_addr == FLASH_CTRL_CSR11_OFFSET);
Tests: T2 T5 T16
2019 1/1 addr_hit[12] = (reg_addr == FLASH_CTRL_CSR12_OFFSET);
Tests: T2 T5 T16
2020 1/1 addr_hit[13] = (reg_addr == FLASH_CTRL_CSR13_OFFSET);
Tests: T2 T5 T16
2021 1/1 addr_hit[14] = (reg_addr == FLASH_CTRL_CSR14_OFFSET);
Tests: T2 T5 T16
2022 1/1 addr_hit[15] = (reg_addr == FLASH_CTRL_CSR15_OFFSET);
Tests: T2 T5 T16
2023 1/1 addr_hit[16] = (reg_addr == FLASH_CTRL_CSR16_OFFSET);
Tests: T2 T5 T16
2024 1/1 addr_hit[17] = (reg_addr == FLASH_CTRL_CSR17_OFFSET);
Tests: T2 T5 T16
2025 1/1 addr_hit[18] = (reg_addr == FLASH_CTRL_CSR18_OFFSET);
Tests: T2 T5 T16
2026 1/1 addr_hit[19] = (reg_addr == FLASH_CTRL_CSR19_OFFSET);
Tests: T2 T5 T16
2027 1/1 addr_hit[20] = (reg_addr == FLASH_CTRL_CSR20_OFFSET);
Tests: T2 T5 T16
2028 end
2029
2030 1/1 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
Tests: T2 T5 T17
2031
2032 // Check sub-word write is permitted
2033 always_comb begin
2034 1/1 wr_err = (reg_we &
Tests: T2 T5 T16
2035 ((addr_hit[ 0] & (|(FLASH_CTRL_PRIM_PERMIT[ 0] & ~reg_be))) |
2036 (addr_hit[ 1] & (|(FLASH_CTRL_PRIM_PERMIT[ 1] & ~reg_be))) |
2037 (addr_hit[ 2] & (|(FLASH_CTRL_PRIM_PERMIT[ 2] & ~reg_be))) |
2038 (addr_hit[ 3] & (|(FLASH_CTRL_PRIM_PERMIT[ 3] & ~reg_be))) |
2039 (addr_hit[ 4] & (|(FLASH_CTRL_PRIM_PERMIT[ 4] & ~reg_be))) |
2040 (addr_hit[ 5] & (|(FLASH_CTRL_PRIM_PERMIT[ 5] & ~reg_be))) |
2041 (addr_hit[ 6] & (|(FLASH_CTRL_PRIM_PERMIT[ 6] & ~reg_be))) |
2042 (addr_hit[ 7] & (|(FLASH_CTRL_PRIM_PERMIT[ 7] & ~reg_be))) |
2043 (addr_hit[ 8] & (|(FLASH_CTRL_PRIM_PERMIT[ 8] & ~reg_be))) |
2044 (addr_hit[ 9] & (|(FLASH_CTRL_PRIM_PERMIT[ 9] & ~reg_be))) |
2045 (addr_hit[10] & (|(FLASH_CTRL_PRIM_PERMIT[10] & ~reg_be))) |
2046 (addr_hit[11] & (|(FLASH_CTRL_PRIM_PERMIT[11] & ~reg_be))) |
2047 (addr_hit[12] & (|(FLASH_CTRL_PRIM_PERMIT[12] & ~reg_be))) |
2048 (addr_hit[13] & (|(FLASH_CTRL_PRIM_PERMIT[13] & ~reg_be))) |
2049 (addr_hit[14] & (|(FLASH_CTRL_PRIM_PERMIT[14] & ~reg_be))) |
2050 (addr_hit[15] & (|(FLASH_CTRL_PRIM_PERMIT[15] & ~reg_be))) |
2051 (addr_hit[16] & (|(FLASH_CTRL_PRIM_PERMIT[16] & ~reg_be))) |
2052 (addr_hit[17] & (|(FLASH_CTRL_PRIM_PERMIT[17] & ~reg_be))) |
2053 (addr_hit[18] & (|(FLASH_CTRL_PRIM_PERMIT[18] & ~reg_be))) |
2054 (addr_hit[19] & (|(FLASH_CTRL_PRIM_PERMIT[19] & ~reg_be))) |
2055 (addr_hit[20] & (|(FLASH_CTRL_PRIM_PERMIT[20] & ~reg_be)))));
2056 end
2057
2058 // Generate write-enables
2059 1/1 assign csr0_regwen_we = addr_hit[0] & reg_we & !reg_error;
Tests: T12 T103 T104
2060
2061 1/1 assign csr0_regwen_wd = reg_wdata[0];
Tests: T2 T5 T6
2062 1/1 assign csr1_we = addr_hit[1] & reg_we & !reg_error;
Tests: T62 T53 T103
2063
2064 1/1 assign csr1_field0_wd = reg_wdata[7:0];
Tests: T2 T5 T16
2065
2066 1/1 assign csr1_field1_wd = reg_wdata[12:8];
Tests: T2 T5 T16
2067 1/1 assign csr2_we = addr_hit[2] & reg_we & !reg_error;
Tests: T6 T53 T19
2068
2069 1/1 assign csr2_field0_wd = reg_wdata[0];
Tests: T2 T5 T6
2070
2071 1/1 assign csr2_field1_wd = reg_wdata[1];
Tests: T16 T17 T6
2072
2073 1/1 assign csr2_field2_wd = reg_wdata[2];
Tests: T17 T62 T12
2074
2075 1/1 assign csr2_field3_wd = reg_wdata[3];
Tests: T2 T5 T62
2076
2077 1/1 assign csr2_field4_wd = reg_wdata[4];
Tests: T2 T16 T62
2078
2079 1/1 assign csr2_field5_wd = reg_wdata[5];
Tests: T2 T5 T6
2080
2081 1/1 assign csr2_field6_wd = reg_wdata[6];
Tests: T16 T17 T6
2082
2083 1/1 assign csr2_field7_wd = reg_wdata[7];
Tests: T2 T5 T6
2084 1/1 assign csr3_we = addr_hit[3] & reg_we & !reg_error;
Tests: T126 T311 T139
2085
2086 1/1 assign csr3_field0_wd = reg_wdata[3:0];
Tests: T2 T5 T16
2087
2088 1/1 assign csr3_field1_wd = reg_wdata[7:4];
Tests: T2 T5 T16
2089
2090 1/1 assign csr3_field2_wd = reg_wdata[10:8];
Tests: T2 T5 T16
2091
2092 1/1 assign csr3_field3_wd = reg_wdata[13:11];
Tests: T2 T5 T16
2093
2094 1/1 assign csr3_field4_wd = reg_wdata[16:14];
Tests: T2 T5 T16
2095
2096 1/1 assign csr3_field5_wd = reg_wdata[19:17];
Tests: T2 T5 T16
2097
2098 1/1 assign csr3_field6_wd = reg_wdata[20];
Tests: T17 T6 T62
2099
2100 1/1 assign csr3_field7_wd = reg_wdata[23:21];
Tests: T2 T5 T16
2101
2102 1/1 assign csr3_field8_wd = reg_wdata[25:24];
Tests: T2 T6 T62
2103
2104 1/1 assign csr3_field9_wd = reg_wdata[27:26];
Tests: T5 T16 T17
2105 1/1 assign csr4_we = addr_hit[4] & reg_we & !reg_error;
Tests: T17 T126 T19
2106
2107 1/1 assign csr4_field0_wd = reg_wdata[2:0];
Tests: T2 T5 T16
2108
2109 1/1 assign csr4_field1_wd = reg_wdata[5:3];
Tests: T2 T5 T16
2110
2111 1/1 assign csr4_field2_wd = reg_wdata[8:6];
Tests: T2 T5 T16
2112
2113 1/1 assign csr4_field3_wd = reg_wdata[11:9];
Tests: T2 T5 T16
2114 1/1 assign csr5_we = addr_hit[5] & reg_we & !reg_error;
Tests: T107 T311 T91
2115
2116 1/1 assign csr5_field0_wd = reg_wdata[2:0];
Tests: T2 T5 T16
2117
2118 1/1 assign csr5_field1_wd = reg_wdata[4:3];
Tests: T2 T5 T16
2119
2120 1/1 assign csr5_field2_wd = reg_wdata[13:5];
Tests: T2 T5 T16
2121
2122 1/1 assign csr5_field3_wd = reg_wdata[18:14];
Tests: T2 T5 T16
2123
2124 1/1 assign csr5_field4_wd = reg_wdata[22:19];
Tests: T2 T5 T17
2125 1/1 assign csr6_we = addr_hit[6] & reg_we & !reg_error;
Tests: T126 T110 T158
2126
2127 1/1 assign csr6_field0_wd = reg_wdata[2:0];
Tests: T2 T5 T16
2128
2129 1/1 assign csr6_field1_wd = reg_wdata[5:3];
Tests: T2 T5 T16
2130
2131 1/1 assign csr6_field2_wd = reg_wdata[13:6];
Tests: T2 T5 T16
2132
2133 1/1 assign csr6_field3_wd = reg_wdata[16:14];
Tests: T2 T5 T16
2134
2135 1/1 assign csr6_field4_wd = reg_wdata[18:17];
Tests: T2 T5 T16
2136
2137 1/1 assign csr6_field5_wd = reg_wdata[20:19];
Tests: T2 T5 T17
2138
2139 1/1 assign csr6_field6_wd = reg_wdata[22:21];
Tests: T2 T5 T62
2140
2141 1/1 assign csr6_field7_wd = reg_wdata[23];
Tests: T2 T16 T17
2142
2143 1/1 assign csr6_field8_wd = reg_wdata[24];
Tests: T2 T6 T62
2144 1/1 assign csr7_we = addr_hit[7] & reg_we & !reg_error;
Tests: T126 T123 T47
2145
2146 1/1 assign csr7_field0_wd = reg_wdata[7:0];
Tests: T2 T5 T16
2147
2148 1/1 assign csr7_field1_wd = reg_wdata[16:8];
Tests: T2 T5 T16
2149 1/1 assign csr8_we = addr_hit[8] & reg_we & !reg_error;
Tests: T126 T90 T223
2150
2151 1/1 assign csr8_wd = reg_wdata[31:0];
Tests: T2 T5 T16
2152 1/1 assign csr9_we = addr_hit[9] & reg_we & !reg_error;
Tests: T132 T126 T107
2153
2154 1/1 assign csr9_wd = reg_wdata[31:0];
Tests: T2 T5 T16
2155 1/1 assign csr10_we = addr_hit[10] & reg_we & !reg_error;
Tests: T17 T103 T126
2156
2157 1/1 assign csr10_wd = reg_wdata[31:0];
Tests: T2 T5 T16
2158 1/1 assign csr11_we = addr_hit[11] & reg_we & !reg_error;
Tests: T126 T19 T47
2159
2160 1/1 assign csr11_wd = reg_wdata[31:0];
Tests: T2 T5 T16
2161 1/1 assign csr12_we = addr_hit[12] & reg_we & !reg_error;
Tests: T126 T234 T21
2162
2163 1/1 assign csr12_wd = reg_wdata[9:0];
Tests: T2 T5 T16
2164 1/1 assign csr13_we = addr_hit[13] & reg_we & !reg_error;
Tests: T62 T104 T236
2165
2166 1/1 assign csr13_field0_wd = reg_wdata[19:0];
Tests: T2 T5 T16
2167
2168 1/1 assign csr13_field1_wd = reg_wdata[20];
Tests: T17 T6 T62
2169 1/1 assign csr14_we = addr_hit[14] & reg_we & !reg_error;
Tests: T5 T126 T71
2170
2171 1/1 assign csr14_field0_wd = reg_wdata[7:0];
Tests: T2 T5 T16
2172
2173 1/1 assign csr14_field1_wd = reg_wdata[8];
Tests: T2 T5 T17
2174 1/1 assign csr15_we = addr_hit[15] & reg_we & !reg_error;
Tests: T20 T126 T312
2175
2176 1/1 assign csr15_field0_wd = reg_wdata[7:0];
Tests: T2 T5 T16
2177
2178 1/1 assign csr15_field1_wd = reg_wdata[8];
Tests: T2 T5 T17
2179 1/1 assign csr16_we = addr_hit[16] & reg_we & !reg_error;
Tests: T6 T53 T30
2180
2181 1/1 assign csr16_field0_wd = reg_wdata[7:0];
Tests: T2 T5 T16
2182
2183 1/1 assign csr16_field1_wd = reg_wdata[8];
Tests: T2 T5 T17
2184 1/1 assign csr17_we = addr_hit[17] & reg_we & !reg_error;
Tests: T30 T126 T262
2185
2186 1/1 assign csr17_field0_wd = reg_wdata[7:0];
Tests: T2 T5 T16
2187
2188 1/1 assign csr17_field1_wd = reg_wdata[8];
Tests: T2 T5 T17
2189 1/1 assign csr18_we = addr_hit[18] & reg_we & !reg_error;
Tests: T2 T126 T38
2190
2191 1/1 assign csr18_wd = reg_wdata[0];
Tests: T2 T5 T6
2192 1/1 assign csr19_we = addr_hit[19] & reg_we & !reg_error;
Tests: T32 T126 T207
2193
2194 1/1 assign csr19_wd = reg_wdata[0];
Tests: T2 T5 T6
2195 1/1 assign csr20_we = addr_hit[20] & reg_we & !reg_error;
Tests: T5 T62 T12
2196
2197 1/1 assign csr20_field0_wd = reg_wdata[0];
Tests: T2 T5 T6
2198
2199 1/1 assign csr20_field1_wd = reg_wdata[1];
Tests: T16 T17 T6
2200
2201 // Assign write-enables to checker logic vector.
2202 always_comb begin
2203 1/1 reg_we_check = '0;
Tests: T134 T73 T75
2204 1/1 reg_we_check[0] = csr0_regwen_we;
Tests: T134 T73 T75
2205 1/1 reg_we_check[1] = csr1_gated_we;
Tests: T134 T73 T75
2206 1/1 reg_we_check[2] = csr2_we;
Tests: T134 T73 T75
2207 1/1 reg_we_check[3] = csr3_gated_we;
Tests: T134 T73 T75
2208 1/1 reg_we_check[4] = csr4_gated_we;
Tests: T134 T73 T75
2209 1/1 reg_we_check[5] = csr5_gated_we;
Tests: T134 T73 T75
2210 1/1 reg_we_check[6] = csr6_gated_we;
Tests: T134 T73 T75
2211 1/1 reg_we_check[7] = csr7_gated_we;
Tests: T134 T73 T75
2212 1/1 reg_we_check[8] = csr8_gated_we;
Tests: T134 T73 T75
2213 1/1 reg_we_check[9] = csr9_gated_we;
Tests: T134 T73 T75
2214 1/1 reg_we_check[10] = csr10_gated_we;
Tests: T134 T73 T75
2215 1/1 reg_we_check[11] = csr11_gated_we;
Tests: T134 T73 T75
2216 1/1 reg_we_check[12] = csr12_gated_we;
Tests: T134 T73 T75
2217 1/1 reg_we_check[13] = csr13_gated_we;
Tests: T134 T73 T75
2218 1/1 reg_we_check[14] = csr14_gated_we;
Tests: T134 T73 T75
2219 1/1 reg_we_check[15] = csr15_gated_we;
Tests: T134 T73 T75
2220 1/1 reg_we_check[16] = csr16_gated_we;
Tests: T134 T73 T75
2221 1/1 reg_we_check[17] = csr17_gated_we;
Tests: T134 T73 T75
2222 1/1 reg_we_check[18] = csr18_gated_we;
Tests: T134 T73 T75
2223 1/1 reg_we_check[19] = csr19_gated_we;
Tests: T134 T73 T75
2224 1/1 reg_we_check[20] = csr20_we;
Tests: T134 T73 T75
2225 end
2226
2227 // Read data return
2228 always_comb begin
2229 1/1 reg_rdata_next = '0;
Tests: T1 T2 T3
2230 1/1 unique case (1'b1)
Tests: T1 T2 T3
2231 addr_hit[0]: begin
2232 1/1 reg_rdata_next[0] = csr0_regwen_qs;
Tests: T1 T3 T4
2233 end
2234
2235 addr_hit[1]: begin
2236 1/1 reg_rdata_next[7:0] = csr1_field0_qs;
Tests: T1 T3 T4
2237 1/1 reg_rdata_next[12:8] = csr1_field1_qs;
Tests: T1 T3 T4
2238 end
2239
2240 addr_hit[2]: begin
2241 1/1 reg_rdata_next[0] = csr2_field0_qs;
Tests: T1 T3 T4
2242 1/1 reg_rdata_next[1] = csr2_field1_qs;
Tests: T1 T3 T4
2243 1/1 reg_rdata_next[2] = csr2_field2_qs;
Tests: T1 T3 T4
2244 1/1 reg_rdata_next[3] = csr2_field3_qs;
Tests: T1 T3 T4
2245 1/1 reg_rdata_next[4] = csr2_field4_qs;
Tests: T1 T3 T4
2246 1/1 reg_rdata_next[5] = csr2_field5_qs;
Tests: T1 T3 T4
2247 1/1 reg_rdata_next[6] = csr2_field6_qs;
Tests: T1 T3 T4
2248 1/1 reg_rdata_next[7] = csr2_field7_qs;
Tests: T1 T3 T4
2249 end
2250
2251 addr_hit[3]: begin
2252 1/1 reg_rdata_next[3:0] = csr3_field0_qs;
Tests: T1 T3 T4
2253 1/1 reg_rdata_next[7:4] = csr3_field1_qs;
Tests: T1 T3 T4
2254 1/1 reg_rdata_next[10:8] = csr3_field2_qs;
Tests: T1 T3 T4
2255 1/1 reg_rdata_next[13:11] = csr3_field3_qs;
Tests: T1 T3 T4
2256 1/1 reg_rdata_next[16:14] = csr3_field4_qs;
Tests: T1 T3 T4
2257 1/1 reg_rdata_next[19:17] = csr3_field5_qs;
Tests: T1 T3 T4
2258 1/1 reg_rdata_next[20] = csr3_field6_qs;
Tests: T1 T3 T4
2259 1/1 reg_rdata_next[23:21] = csr3_field7_qs;
Tests: T1 T3 T4
2260 1/1 reg_rdata_next[25:24] = csr3_field8_qs;
Tests: T1 T3 T4
2261 1/1 reg_rdata_next[27:26] = csr3_field9_qs;
Tests: T1 T3 T4
2262 end
2263
2264 addr_hit[4]: begin
2265 1/1 reg_rdata_next[2:0] = csr4_field0_qs;
Tests: T1 T3 T4
2266 1/1 reg_rdata_next[5:3] = csr4_field1_qs;
Tests: T1 T3 T4
2267 1/1 reg_rdata_next[8:6] = csr4_field2_qs;
Tests: T1 T3 T4
2268 1/1 reg_rdata_next[11:9] = csr4_field3_qs;
Tests: T1 T3 T4
2269 end
2270
2271 addr_hit[5]: begin
2272 1/1 reg_rdata_next[2:0] = csr5_field0_qs;
Tests: T1 T3 T4
2273 1/1 reg_rdata_next[4:3] = csr5_field1_qs;
Tests: T1 T3 T4
2274 1/1 reg_rdata_next[13:5] = csr5_field2_qs;
Tests: T1 T3 T4
2275 1/1 reg_rdata_next[18:14] = csr5_field3_qs;
Tests: T1 T3 T4
2276 1/1 reg_rdata_next[22:19] = csr5_field4_qs;
Tests: T1 T3 T4
2277 end
2278
2279 addr_hit[6]: begin
2280 1/1 reg_rdata_next[2:0] = csr6_field0_qs;
Tests: T1 T3 T4
2281 1/1 reg_rdata_next[5:3] = csr6_field1_qs;
Tests: T1 T3 T4
2282 1/1 reg_rdata_next[13:6] = csr6_field2_qs;
Tests: T1 T3 T4
2283 1/1 reg_rdata_next[16:14] = csr6_field3_qs;
Tests: T1 T3 T4
2284 1/1 reg_rdata_next[18:17] = csr6_field4_qs;
Tests: T1 T3 T4
2285 1/1 reg_rdata_next[20:19] = csr6_field5_qs;
Tests: T1 T3 T4
2286 1/1 reg_rdata_next[22:21] = csr6_field6_qs;
Tests: T1 T3 T4
2287 1/1 reg_rdata_next[23] = csr6_field7_qs;
Tests: T1 T3 T4
2288 1/1 reg_rdata_next[24] = csr6_field8_qs;
Tests: T1 T3 T4
2289 end
2290
2291 addr_hit[7]: begin
2292 1/1 reg_rdata_next[7:0] = csr7_field0_qs;
Tests: T1 T3 T4
2293 1/1 reg_rdata_next[16:8] = csr7_field1_qs;
Tests: T1 T3 T4
2294 end
2295
2296 addr_hit[8]: begin
2297 1/1 reg_rdata_next[31:0] = csr8_qs;
Tests: T1 T3 T4
2298 end
2299
2300 addr_hit[9]: begin
2301 1/1 reg_rdata_next[31:0] = csr9_qs;
Tests: T1 T3 T4
2302 end
2303
2304 addr_hit[10]: begin
2305 1/1 reg_rdata_next[31:0] = csr10_qs;
Tests: T1 T3 T4
2306 end
2307
2308 addr_hit[11]: begin
2309 1/1 reg_rdata_next[31:0] = csr11_qs;
Tests: T1 T3 T4
2310 end
2311
2312 addr_hit[12]: begin
2313 1/1 reg_rdata_next[9:0] = csr12_qs;
Tests: T1 T3 T4
2314 end
2315
2316 addr_hit[13]: begin
2317 1/1 reg_rdata_next[19:0] = csr13_field0_qs;
Tests: T1 T3 T4
2318 1/1 reg_rdata_next[20] = csr13_field1_qs;
Tests: T1 T3 T4
2319 end
2320
2321 addr_hit[14]: begin
2322 1/1 reg_rdata_next[7:0] = csr14_field0_qs;
Tests: T1 T3 T4
2323 1/1 reg_rdata_next[8] = csr14_field1_qs;
Tests: T1 T3 T4
2324 end
2325
2326 addr_hit[15]: begin
2327 1/1 reg_rdata_next[7:0] = csr15_field0_qs;
Tests: T1 T3 T4
2328 1/1 reg_rdata_next[8] = csr15_field1_qs;
Tests: T1 T3 T4
2329 end
2330
2331 addr_hit[16]: begin
2332 1/1 reg_rdata_next[7:0] = csr16_field0_qs;
Tests: T1 T3 T4
2333 1/1 reg_rdata_next[8] = csr16_field1_qs;
Tests: T1 T3 T4
2334 end
2335
2336 addr_hit[17]: begin
2337 1/1 reg_rdata_next[7:0] = csr17_field0_qs;
Tests: T1 T3 T4
2338 1/1 reg_rdata_next[8] = csr17_field1_qs;
Tests: T1 T3 T4
2339 end
2340
2341 addr_hit[18]: begin
2342 1/1 reg_rdata_next[0] = csr18_qs;
Tests: T1 T2 T3
2343 end
2344
2345 addr_hit[19]: begin
2346 1/1 reg_rdata_next[0] = csr19_qs;
Tests: T1 T3 T4
2347 end
2348
2349 addr_hit[20]: begin
2350 1/1 reg_rdata_next[0] = csr20_field0_qs;
Tests: T1 T3 T4
2351 1/1 reg_rdata_next[1] = csr20_field1_qs;
Tests: T1 T3 T4
2352 1/1 reg_rdata_next[2] = csr20_field2_qs;
Tests: T1 T3 T4
2353 end
2354
2355 default: begin
2356 reg_rdata_next = '1;
2357 end
2358 endcase
2359 end
2360
2361 // shadow busy
2362 logic shadow_busy;
2363 assign shadow_busy = 1'b0;
2364
2365 // register busy
2366 unreachable assign reg_busy = shadow_busy;
2367
2368 // Unused signal tieoff
2369
2370 // wdata / byte enable are not always fully used
2371 // add a blanket unused statement to handle lint waivers
2372 logic unused_wdata;
2373 logic unused_be;
2374 1/1 assign unused_wdata = ^reg_wdata;
Tests: T2 T5 T16
2375 1/1 assign unused_be = ^reg_be;
Tests: T2 T5 T16